JPS5870565A - Power supply circuit of intergrated circuit - Google Patents
Power supply circuit of intergrated circuitInfo
- Publication number
- JPS5870565A JPS5870565A JP56168668A JP16866881A JPS5870565A JP S5870565 A JPS5870565 A JP S5870565A JP 56168668 A JP56168668 A JP 56168668A JP 16866881 A JP16866881 A JP 16866881A JP S5870565 A JPS5870565 A JP S5870565A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- analog
- digital
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H10D89/213—Design considerations for internal polarisation in field-effect devices
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はアナログ回路とディジタル回路が同一チップ上
にあるコンプリメンタリ・メタルオキサイドセミコンダ
クタ（以後Ｃ−′Ｍｏ８と略記する）集積回路の基板電
位供給方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate potential supply method for a complementary metal oxide semiconductor (hereinafter abbreviated as C-'Mo8) integrated circuit in which an analog circuit and a digital circuit are on the same chip.
従来からのＣ−ＭＯ８回路は主にディジタル回路用に考
えられてきていた。最近、Ｃ−ＭＯ８構造上に比較的容
易に容量を付加するプロセスが実現された。その結果、
高利得のアナログ回路なＣ・Ｍ）８構造により実現し得
、さらに同一チップ上にディジタル回路を混在させるこ
とが可能となった。ところが、ここでアナログ回路とデ
ィジタル回路を混在させた故に次の問題点を生じもつま
り、ディジタル回路内でＣ−Ｍｏ５構造を構成するＰ−
チャネルＭ）８ ）ランジスタとＮ−チャネルＭ）８ト
ランジスタ（以後Ｐ−ＭＯ８ＴＲ８，Ｎ−ＭＯＢ Ｔμ
ｓと略嘴）が過渡的に同時にＯＮする入力電圧範囲が存
°在し、。Conventional C-MO8 circuits have been considered mainly for digital circuits. Recently, a process for adding capacitance onto a C-MO8 structure with relative ease has been realized. the result,
This can be realized using the C.M.8 structure, which is a high-gain analog circuit, and furthermore, it has become possible to mix digital circuits on the same chip. However, because analog circuits and digital circuits are mixed here, the following problem arises:
Channel M) 8) transistor and N-channel M) 8 transistor (hereinafter referred to as P-MO8TR8, N-MOB Tμ
There is an input voltage range in which both s and beak are simultaneously ON transiently.
これに寄因する貫通電流がディジタル回路部の電源ライ
ンを流れる。この結果、ディジタル部の電源ラインには
配ＩＩ（主にアル建ニウム配線）抵抗に応じた雑音電圧
を発生する。A through current due to this flows through the power supply line of the digital circuit section. As a result, a noise voltage corresponding to the resistance of wiring II (mainly aluminum wiring) is generated in the power supply line of the digital section.
この電源ラインに混入した雑音電圧が、そのままアナロ
グ部への電源２インに混入すると、アナログ部での微弱
な入力信号にこの雑音電圧が重畳し、アナログ部での増
幅動作に障害を与えると言う問題がある。If the noise voltage mixed into this power supply line mixes directly into the power supply 2-in to the analog section, this noise voltage will be superimposed on the weak input signal in the analog section, causing a disturbance to the amplification operation in the analog section. There's a problem.
本発明の目的は、上記した問題点をなくし、アナログ回
路とディジタル回路を同一チップ上に乗せ、かつ安定な
増幅動作を行な５ Ｃ−Ｍｌ）８集積回路を提供すると
とｋある。An object of the present invention is to eliminate the above-mentioned problems, to provide a 5C-Ml)8 integrated circuit in which an analog circuit and a digital circuit are mounted on the same chip, and a stable amplification operation is performed.
上記の目的を達成するために本発明は、ディジタル回路
部とアナ四グ回路部とに独立な電源供給端子を単独にも
うけたところに特徴がある。In order to achieve the above object, the present invention is characterized in that independent power supply terminals are separately provided for the digital circuit section and the analog/4G circuit section.
第１図に本発明の一実施例による、具体的なレイアウト
図、第２図に集積回路の断面図を示す。第１図において
、１は集積回路が搭載されているシリコンチップであり
、２．３はアナ膣グ回路のセル、 ４，５，６．７はア
ナログ回路とディジタル回路へ供給される電源用パッド
であり、パッドより実線で示したものはアルオニウム配
線である。８はディジタル回路の二ニットセルであり９
〜２１は集積回路の入出力用パッド群である。これらの
パッド群は第２図に示したように配＠２４を介してリー
ドフレーム２５ Ｋ接続され外部回路と接続されるもの
である。このようにアナログ回路とディジタル回路との
電源供給配線を別個に設けるととＫより、両者間にフィ
ルタ等を設けることが可能となり前述したディジタル回
路の動作時の雑音電圧がアナログ回路に混入することを
防ぐことが可能となるものである。さらに上記したよう
な電源供給手段をとるととにより、アナログ回路とディ
ジタル回路へ供給する最適な電圧を別個に設定すること
が出来、かつ電源を別々に制御することも出来、省電力
効果にもつながる長所を持つことになる。FIG. 1 shows a specific layout diagram according to an embodiment of the present invention, and FIG. 2 shows a cross-sectional view of an integrated circuit. In Figure 1, 1 is a silicon chip on which an integrated circuit is mounted, 2.3 is a cell of an analog circuit, and 4, 5, and 6.7 are power supply pads that are supplied to analog and digital circuits. , and the solid line from the pad is the Al-onium wiring. 8 is a two-nit cell of a digital circuit, and 9
21 is a group of input/output pads of the integrated circuit. As shown in FIG. 2, these pad groups are connected to the lead frame 25K via wires 24 and connected to an external circuit. If the power supply wiring for the analog circuit and the digital circuit is provided separately in this way, it becomes possible to install a filter etc. between the two, which prevents the noise voltage during the operation of the digital circuit described above from entering the analog circuit. This makes it possible to prevent Furthermore, by using the power supply means as described above, it is possible to separately set the optimal voltage to be supplied to analog circuits and digital circuits, and it is also possible to control the power supplies separately, resulting in a power saving effect. You will have the advantage of being connected.
以上述べたように本発ＱＩＨＣよれば高増幅度を持った
増幅器をディジタル回路と同−集積回路上に混在させた
際に問題となっていたディジタル回路部で発生する雑音
電圧が増幅器に与える影響を低減でき、かつ前述したよ
うな長所を持つことができる。As mentioned above, according to this QIHC, when an amplifier with a high amplification degree is mixed on the same integrated circuit as a digital circuit, the effect of noise voltage generated in the digital circuit section on the amplifier is a problem. can be reduced, and can have the advantages mentioned above.
１１４１図は本発明の一実施例を示すレイアウト図、纂
２図は集積回路の構造を示す断面図である。
１・・・シリコンチップ
２．５・・・アナログ回路セル
８・・・ディジタル回路セル
４〜７，９〜２１・・・パッド ２５・・・リードフ
レーム代理人弁塊士 薄 １）利 幸FIG. 1141 is a layout diagram showing one embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of an integrated circuit. 1...Silicon chip 2.5...Analog circuit cell 8...Digital circuit cell 4-7, 9-21...Pad 25...Lead frame representative valve engineer Usui 1) Toshiyuki
Claims (1)
構造を持ち、アナログ回路とディジタル回路を同一チッ
プ上に具備した集積回路において、該集積回路に電源を
供給する電源回路を、アナログ部とディジタル部に分け
て、各々独立に集積回路の端子より電源供給することを
特徴とした集積回路の電源供給回路。Complementary Metal Oxide In an integrated circuit that has a semiconductor structure and has an analog circuit and a digital circuit on the same chip, the power supply circuit that supplies power to the integrated circuit is divided into an analog part and a digital part, and each part is integrated independently. A power supply circuit for an integrated circuit characterized by supplying power from the terminals of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56168668A JPS5870565A (en) | 1981-10-23 | 1981-10-23 | Power supply circuit of intergrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56168668A JPS5870565A (en) | 1981-10-23 | 1981-10-23 | Power supply circuit of intergrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5870565A true JPS5870565A (en) | 1983-04-27 |
| JPH0330303B2 JPH0330303B2 (en) | 1991-04-26 |
Family
ID=15872279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56168668A Granted JPS5870565A (en) | 1981-10-23 | 1981-10-23 | Power supply circuit of intergrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5870565A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6398872A (en) * | 1986-10-15 | 1988-04-30 | Rohm Co Ltd | Analog/digital ic |
| JPS6424857U (en) * | 1987-08-05 | 1989-02-10 | ||
| JPH01258459A (en) * | 1988-04-08 | 1989-10-16 | Seikosha Co Ltd | Integrated circuit using battery as power source |
| JPH0290666A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Power wiring structure of integrated circuit |
| JPH02143553A (en) * | 1988-11-25 | 1990-06-01 | Nec Corp | Semiconductor device |
| JPH02110352U (en) * | 1989-02-21 | 1990-09-04 | ||
| JPH02110818U (en) * | 1989-02-22 | 1990-09-05 | ||
| JPH02238657A (en) * | 1989-03-13 | 1990-09-20 | Fujitsu Ltd | semiconductor equipment |
| JPH03102913A (en) * | 1989-09-15 | 1991-04-30 | Rohm Co Ltd | Interface for cmos circuit |
| WO1993009599A2 (en) * | 1991-10-30 | 1993-05-13 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| US5649160A (en) * | 1995-05-23 | 1997-07-15 | Microunity Systems Engineering, Inc. | Noise reduction in integrated circuits and circuit assemblies |
| US6219909B1 (en) | 1990-11-28 | 2001-04-24 | Hitachi, Ltd. | Method of mounting disk drive apparatus |
| JP2016025199A (en) * | 2014-07-18 | 2016-02-08 | セイコーエプソン株式会社 | Circuit device, electronic device and moving body |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420680A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Large scale integrated circuit |
-
1981
- 1981-10-23 JP JP56168668A patent/JPS5870565A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420680A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Large scale integrated circuit |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6398872A (en) * | 1986-10-15 | 1988-04-30 | Rohm Co Ltd | Analog/digital ic |
| JPS6424857U (en) * | 1987-08-05 | 1989-02-10 | ||
| JPH01258459A (en) * | 1988-04-08 | 1989-10-16 | Seikosha Co Ltd | Integrated circuit using battery as power source |
| JPH0290666A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Power wiring structure of integrated circuit |
| JPH02143553A (en) * | 1988-11-25 | 1990-06-01 | Nec Corp | Semiconductor device |
| JPH02110352U (en) * | 1989-02-21 | 1990-09-04 | ||
| JPH02110818U (en) * | 1989-02-22 | 1990-09-05 | ||
| JPH02238657A (en) * | 1989-03-13 | 1990-09-20 | Fujitsu Ltd | semiconductor equipment |
| JPH03102913A (en) * | 1989-09-15 | 1991-04-30 | Rohm Co Ltd | Interface for cmos circuit |
| US6219909B1 (en) | 1990-11-28 | 2001-04-24 | Hitachi, Ltd. | Method of mounting disk drive apparatus |
| US6856482B2 (en) | 1990-11-28 | 2005-02-15 | Hitachi, Ltd. | Disk drive apparatus and method of mounting same |
| US7227712B2 (en) | 1990-11-28 | 2007-06-05 | Hitachi Global Storage Technologies Japan, Ltd. | Disk drive apparatus and method of mounting same |
| WO1993009599A2 (en) * | 1991-10-30 | 1993-05-13 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| US5649160A (en) * | 1995-05-23 | 1997-07-15 | Microunity Systems Engineering, Inc. | Noise reduction in integrated circuits and circuit assemblies |
| JP2016025199A (en) * | 2014-07-18 | 2016-02-08 | セイコーエプソン株式会社 | Circuit device, electronic device and moving body |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0330303B2 (en) | 1991-04-26 |
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