JPS5868962A - Semiconductor memory storage - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to static random access memory cells.

The present invention is particularly effective in devices using MI8 (in M2S) type transistors, but is not limited thereto.

1m Conventional technology and problems Conventionally, static m random access memory cells are J
[Two transistors Q cross-connected as shown in Figure 1
1* Qs and load transistors Q8 and Q4KL, which are arranged in a matrix and a pair of identical bits B
For convenience of connecting a large number of cells on L, BL, optional transistors Qi, Q controlled by word 1iWLK are provided.
It consists of a 6gIA transistor with @.

In order to reduce the area occupied per bit and to avoid increasing the tape area of the integrated circuit in response to the same requirements for the number of integrated pits in the memory, the load transistors Qi and Q were replaced with fixed resistors (1111), and 1 bit was processed using 1111 transistors. sg
Measures were now taken to do so.

Figure 2 shows the TGL circuit diagram of such a cell, and high-resistance polysilicon is generally used as the load resistor. ◇In order to further miniaturize the memory cell, a well-known technology announced in recent years (Ta0bxone et al s 18800
1 in Dig, Tech, pZ116 (1980))
The polysilicon forming the gates of the transistors Qy' and Qa in the @z diagram and the polysilicon serving as the load resistor are formed in separate processes, and the four structures are placed three-dimensionally on the load resistor or transistor. Figure 8 is a plan view showing this, and the load resistance and bit-1 power supply are shown for ease of understanding.
1 Abbreviation for grounding. For details, please refer to the above-mentioned known document. 0 A buried contact BNI e BNm is made between the gate electrode l-2 and the drain region 8.4. In this configuration, the electrically connected transistors Qy, Qa, Qe, Q are arranged on the same plane.
In order to further increase the 4C integration of I/O, the only methods left are, for example, narrowing the gap between the twisted gates and the gates, or shortening the length of the gate itself by 1-1, and what are these methods? n
◎ However, in reality, there is a limit to the reduction of the gate length for transistors to function properly, and it is not possible to make them too small. Also the gate,
The spacing between the gates is also determined by the minimum allowable loe dimension, which can be narrowed further.

For example, it is necessary to change the manufacturing equipment to one that is capable of finer processing (for example, to use a photomask that was conventionally used, or to change from the conventional 2-fi process to one that uses an electron beam or X-ray). 〇 (3) Structure of the Invention In view of this point, the present invention is designed to reduce the distance between the gate electrodes of the eight transistors 1111*f: the first transistor and the third transistor.
LD to make the gate electrode of the transistor in a separate process
, ail, the gate electrodes of both transistors are electrically separated from each other via interlayer insulation Jll formed around the gates of the transistors, thereby providing an FTG-structured memory cell. Since the interlayer insulating metal film thickness is 8N degrees, the gap between the base and gate is 8N degrees, so the goo
OA-800OA allows public treasury at regular intervals.

Furthermore, by using the present invention, field oxidation is applied to a part of the MIS transistor in order to prevent the performance of the transistor from deteriorating even if the pattern position between the gate, electrode, and active region is changed. Extend it to the top 2
Perhaps because of stone formation, the unnecessary surface structure of the extended part of the gate is reduced, and the area occupied by the memory can be reduced without reducing the size of the sword. This will be explained in detail below.

(4) Embodiment of the invention FIG. 4 shows a plan view of a memory cell according to an embodiment of the present invention. The rotation height corresponds to FIG. 8, and the minimum width M of the gate length is drawn the same. . The transistor Q is a P-type silicon substrate fabricated by a known method, for example, and has a gate electrode L formed of a polysilicon layer or a metal silicide having similar properties to a high melting point metal.゛ is plated, SiO□ with a thickness of 800A is formed as a gate insulating film, and OVD (Chemical V
Polysilicon deposited by the apor deposition method is processed to obtain the gate electrode of Q. If an opening is made in a part of the gate oxide film prior to gate formation, the gate electrode will come into contact with the silicon substrate in that part, and if the impurities in the gate storage material are diffused into the substrate, a buried contact will occur. ) BNs are formed. At this part, the gate of Q and the drain of Q' are connected. Next, unnecessary gate oxide films are removed, and interlayer insulation 1N is formed on the same gate of gate electrodes Q and I. Several known methods can be used for this method, but for example, when using enhanced heat transfer, polysilicon doped with impurities at a high concentration is thermally oxidized several times faster than a silicon substrate. Therefore, in the process of forming the gate modification film of transistor Qa, (A thick 840. film, for example gsooA, is formed around the gate electrodes #&l.) Q and Q are basically the same gate oxide film thickness, but these transistors When the transistor has a channel doped structure, it is better to purposely increase the thickness of the gate oxide film or to custom-make both transistors, which balances electrically and is desirable as a flip-flop circuit.In other words, the channel at the 98th part is Q? After gate oxidation, this oxide film is once removed and oxidized again, resulting in a change in the dose weight of the channel dope, so the gate oxide film thicknesses of both transistors are made different to compensate for the resulting vj variation. Good too.

Of course, even if the channel doping is redone after forming the electrode 1 of Q and before forming the gate of Q, the gate polysilicon will not be doped in the area 7 in this case because the gate polysilicon becomes a mask. Comparing Mayu Q and Qak, the gate part of Q is made before Q8 in terms of process, so the channel doped impurities are easily redistributed.
y, Qs to be electrically balanced within the range of Q.

After forming the gate electrode, the device's channel dome (the non-N material may have the same conductivity type as the substrate or the same conductivity type) is performed, and the gate oxide film thickness is controlled independently by Qt and Qs (2).
However, it is desirable to install them at different thicknesses.

By providing an opening in a part of the goo gate insulating film prior to forming the gate polysilicon of Q8, a buried contact BNlft can be formed in OQ, , Q.

After formation, gold EIK arsenic is ion-implanted to form source and drain regions.Q9. QIO and peripheral circuit transistors are formed at the same time as Q or at the same time as Ql.

FIG. 5 shows the cross-sectional shape of the line-X' immediately after the formation of the source write and drain regions. In the same figure, 10 is PAL silicon substrate%1
1 is a field oxide layer, and the mouth is a transistor 4. a gate oxide film 18 for insulating between the gate electrodes 1.3;
jυ, it is a membrane.

Next, a thin film load resistor is connected to the buried contact BNx*BN" and connected to the power source. If this load resistor is made of polysilicone '71X, the memory cell of the present invention will have an 8-layer polysilicon structure. However, if a part of the second layer of polysilicon is selectively doped with impurities to make it resistive to gold, a two-layer polysilicon structure is also possible. The polysilicon layer formed at the same time as the gate 1.1 billion may be used, or a part of the 8th layer of polysilicon may be used with a lower resistance.Next, after covering the interlayer insulating film, contact holes are formed. N Os e N O4e N (forms 3% and forms a wiring layer on aluminum etc. to form ground wiring and bit line pairs. The former is NOa, the latter is No4eN
Contact each person through OI. Below is normal taus
It is the same as one process of memory. In Figure 5g6, 14 is the gate polysilicon layer 1.2 in the diagram showing the cross section of the final layer.
This is an insulating film between the capacitor and the polysilicon 7dlS for the load resistor. In this figure, the case where an 8@polysilicon structure is adopted for the load resistor is shown as an example in Bo 1. 16 is a P2O black interlayer insulating film, through which contact holes NO8° NO4, NO5 with a corner 116 are formed f'L.
The figure shows a state in which a metal wiring layer 17 made of aluminum or the like is formed after fc. Note that in the above example, if the overlapping parts of the gate electrodes are only on the field area,
8- is shown as an example, but this overlap may partially be on the active w4 area.

Of course, buried contact soil may also be used.

(5) Effects of the Invention According to the present invention, each gate electrode of a pair of cross-connected transistors constituting a static memory cell is arranged to partially overlap each other, thereby significantly reducing the cell area. It becomes possible to do this, and with great improvements, excellent practical effects can be obtained.

4. Brief Description of the Drawings 3. FIGS. 1 and 2 are circuit diagrams of a known Smenacki Solundum access memory cell, FIG. 8 is a plan view of a conventional memory cell, and FIG. 6 is a diagram of a conventional memory cell. Figure 5 is a cross-sectional view of the structure of the memory cell according to the embodiment of the present invention during the manufacturing process, and corresponds to the xx' cross section in Figure 4. Figure 6 is a structural cross-sectional view at the final stage of the manufacturing process of the memory cell shown in Figure g5.
, g......Gate electrode 8.4
・・・・・・・・・・・・Drain region 113.
14.16...Ryoukakuzetsu II & Membrane 15...
・・・・・・・・・・・・Polysilicon layer for load resistance Vss Figure 1 □ DD λ Figure n '3 Figure t Man 4F! 1

Claims (3)

[Claims] (1) In a random access memory cell having at least S field effect transistors whose drains and gates cross each other, the gate electrode of one transistor is placed on the gate electrode of the other transistor through an insulating film.
A semiconductor memory device characterized in that two electrodes are partially overlapped. (2) Gate electrode of one of the transistors? The gate electrode of the other transistor is connected to the drain region of the other transistor in a trench contact structure to the tunnel region of the other transistor.
A storage device for thieves in Paragraph 1 of the patent claims. (3) The two transistors are MI8m, and the gate insulation thickness of the one transistor and the gate I8 edge thickness of the other transistor are different, and the electrical placement of both transistors is balanced. A semiconductor memory device according to claim 1, wherein: ¥f value.