JPS5868284A - Integrated storage circuit - Google Patents

Abstract

PURPOSE:To perform high-speed successive reading and writing by arranging memory cells at intersections of word lines and bit lines, and providing a means of selecting the bit lines successively corresponding to the selection of the word lines. CONSTITUTION:In a memory array MA, memory cells MC are arranged at intersections of word lines WL and bit lines BL crossing at right angles. Successive specifying circuits SP1 and SP2 and a multiplexer circuit MUX are provided to select word lines successively, and bit lines are selected successively corresponding to said selection to connect memory cells to the outside in predetermined order. Consequently, input and output of information is speeded up and an input terminal for address specification is eliminated to obtain small-sized constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated memory circuit, and more particularly to an integrated memory circuit capable of high-speed sequential reading or sequential writing useful for information processing devices and image terminals.

As a conventional integrated memory circuit, a so-called random access type is known. FIG. 1 shows a conventional random access type integrated memory circuit. In FIG. 1, MA is a memory array, and a plurality of word lines WL are orthogonal to each other.
A memory cell MC is arranged at the intersection of and a plurality of pit lines BL. R■) is a row decoder that connects multiple word lines W
Select one of L. MUX is a multiplexer and connects one of the plurality of bit lines BL to the data bus line DB. C'D is a column decoder which selects the bit line BL to be connected to the data bus line DB in the multiplexer MUX.

Address signals applied from the outside are supplied to row decoder RD and column decoder CD.

The address signal supplied to the row decoders R and D is used to select one of the plurality of word lines WL,
Each memory cell MC connected to the selected word line WL
transfers data to each bit line BL (read) or enters a state in which data is transferred from bit line BI (write).

The address signal supplied to the column decoder CD connects one of the plurality of bit lines BL to the data bus line D B (-
Used for electrical connections. In this way, the address signal as a whole specifies one memory cell MC in the memory array MA, and connects this memory cell to the data bus line D.
B makes data transfer possible.

In this way, according to conventional integrated memory circuits, information can be read and written to any memory cell, but each time one piece of information is read or written, an address signal is input and decoded, so the read time and The drawback is that the writing time cannot be shortened.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated memory circuit that can input and output information at high speed.

Therefore, the present invention focuses on the fact that information is input and output in a predetermined order in many information processing devices, etc., and provides a means for soft selection of a plurality of word lines and bit lines, so that memory cells can be selected in a predetermined order. It is characterized by being connected to the outside in the following order.

Hereinafter, the contents of the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows a first embodiment of the invention. In FIG. 2, the memory array MA is similar to the integrated storage circuit in FIG.
Memory cells MC are arranged at the intersections of two orthogonal word lines WL and bit lines BL.SP, , 8P2 is a sequential designation circuit, and MUX is a multiplexer circuit.Here, the number of word lines WL is is N, and the number of bit lines is M.
Assume that a memory array M is provided with MN memory cells MC.

Sequential designation circuit SP1 has N output terminals TO11, TO]
2...TOIN and one clock input terminal T1
The output terminals 'ro11 to TOIN are each connected to the word line WLE, and each word line WL is sequentially selected in synchronization with the clock signal φ1 applied to the clock input terminal T11. Sequential designation circuit SP2
is M+1 output terminal 't' which is one more than bit line BL.
021, 'ro22...TO2(M+-1
) and one clock input terminal T2, the first output terminal T021 of which is connected to the input terminal T11 of SP1, and the clock signal φ1 is connected to the first output terminal TO21 of SP2. It is configured to be output from. Also second. Third. ...M+1st M output terminals T022. TO23...TO2CM+
1) is connected to a multiplexer circuit MUX. In the multiplexer circuit MUX, the M signals from the sequential designation circuit SP2 are in one-to-one correspondence with the bit lines BL, and the M signals are sequentially transmitted by the signals from the second to M+1 output terminals of the sequential designation circuit SP2. One of the bit lines BL is electrically connected to the data bus line DB.

Next, the operation shown in FIG. 2 will be explained by associating the electric signals to be handled with binary logic rlJ and rOJ. It is assumed that when the output signal of the output terminal TChi (i=1 to N) of the sequential designation circuit sp1 is "1", the word line WL connected to that terminal is selected. In addition, the output terminal TOzz of the sequential designation circuit SP2
When the output signal of (J=1 to M+1) is "1", the bit line BL corresponding to this terminal (2) is electrically connected to the data bus line DB.

Figure 3 is a time chart explaining Figure 2.
In Figure 3, T11+T1.2...TIM, Tl(
M+]), T21+T22...T2M+T2(
M+1) ...... are the periods of operation, and '
In I'll, φ1 becomes "1", the output terminal TO11 of the designation circuit SP1 becomes "1", and one word line (first word line and Tl) becomes "1", and the data stored in all memory cells connected to the first word line are taken out to the respective memory cells (bit lines tangential to each other).
Although φ1 becomes "0" at <T12 following l, the first word line is still kept at "1", and during this period, the second output terminal TO22 of the designation circuit SP2 is sequentially The bit line corresponding to DB is electrically connected to the data bus DB. At T13 following T12, T
”+2, the first word line is “1” and SF3
The bit line corresponding to the next third output terminal 't''023 is electrically connected to the data bus line DB.

Below T14 + 'ris I...T1(M+
In each period 1), each bit line is sequentially electrically connected to the data bus line DB. Following TI(M+1)<
At T21, φ1 becomes "1" again, and Toll of the designation circuit SP1 becomes roJ and TOl2 becomes "1", so the first word line becomes [Ol, TOlz, . "1", and the data stored in all the memory cells connected to the second word line are taken out to the pits m to which the memory cells are connected.

Following T21<T22 * T23+...T2(
M+1), each bit line is sequentially electrically connected to data bus line DB. The signals on the data bus line DB are configured to be able to be input/output to/from the outside of the integrated storage circuit.

As described above, by having a mechanism for sequentially selecting rows and columns of memory array MA, all memory cells can be selected sequentially, and there is no need to input or decode external signals for memory cell designation. This is necessary and enables data input/output in a short period of time.

The embodiment shown in FIG. 2 has a configuration in which after all memory cells connected to the same word line are selected, processing is transferred to the memory cell connected to the next word line, but the memory cells are dynamic type. In this case, depending on the relationship between the refresh time interval and clock signal φ2, T out of M memory cells connected to the same word line (L is Mat
(lower integer) (electrical connection of the data bus line and the bit line to which the memory cell is connected), and then when the word line is selected again (2) By processing one out of M unprocessed memory cells and processing all memory cells connected to the word line after L word line selections, the refresh time interval can be made appropriate. .

Further, in the embodiment shown in FIG. 2, all bit lines are MU
Although it was tangential to
The bit lines belonging to the same group are connected by a sense circuit, and the MUX
One of the two bit lines may be connected to the bit line.

In the embodiment shown in FIG. 2 above, the period T]1rT21+
. . . Like TN1, there is a drawback that there is a period in which no bit line is electrically connected to the data bus line. FIG. 4 shows a second embodiment that eliminates this drawback. The embodiment of FIG. 4 will be explained assuming that M is an even number. Two memory cell arrays MA1 and MA2 are formed by arranging memory cells at the intersections of N word lines and T bit lines.
Just like SP1 in the embodiment shown in FIG. 2, two Sequential designation circuits 5P11, 5P12 and M
A multiplexer circuit MtJX for electrically connecting one of the M bit lines to the data bus line DB, and a bit line BL to be electrically connected to the data bus line DB among the M bit lines in sequence. and a sequential designating circuit SP'2. Sequential designation circuit 8 pH, S P
, 2 are each N output terminals TOIIIT0112
+ “”” TOIIN r TOl21 + TO
l22 + """ TOl 2N and each one input terminal TI]1.T■12, sequentially specifying circuit SP
] Output terminal TO111+...TOIIN of memory array MA1 is sequentially connected to output terminals TO+21 and TO122 of designation circuit 5P12 to N words and IWL of memory array MA1.
°°°゛T012N is connected to N words (4wL) of memory array MN2, respectively. Sequential designation circuit S
P'2 is M output terminals TO'2.1 + TO'2.
2 +...TO'2! , M and input terminal TI
'2, and TO'2,1. TO'2,2...
TO2,M' is connected to the multiplexer circuit MUX, and M/2 output terminals TO+TO2,2,...
・To2. The signal output from M has a one-to-one correspondence with the seven pit lines of Mn2, and the signals output from the other τ output terminals TO
2, M/2+1. ...To2. The signal output from M has a one-to-one correspondence with the τ bits m of INl.

The configuration is such that when one of the output terminals of SP'2 has a logical value of "1", the corresponding bit line BL is electrically connected to the data bus line DB, and TO'2.1 is connected to the multiplexer. At the same time as the circuit MU father, input terminals sp and l are connected to input terminals TIII, and TO'2 and M/2+1 are connected to input terminals S
They are respectively connected to the input terminals T112 of P+2.

The signal input to the input terminal Tl11 of the sequential specification circuit 5P11 is input to φ11, and the signal input to the input terminal T11 of the sequential specification circuit 5P12 is input to the input terminal T11 of the sequential specification circuit 5P12.
The signal input to 2 is φ12, and 5P11, 5P1z
, Sy2's input terminal and output terminal are shown in FIG. 5. The period separated by clock signal φ2 is TN
, 1, T o12N is already “1”,
The Nth word line of memory array MA2 is in the selected state (= present, TO゛2,1 is also "1", and memory arrays 1 to 4
The bit line (first bit line) corresponding to o', 1 of A2 is electrically connected to the data bus, IIDB, and the Nth word line of MA2 and the first bit line are connected to each other. At the same time that a certain memory cell becomes ready for reading and writing through the data bus line DB, the signal of TO'2,1 becomes φ1.
It is also input to TIII as 1, and To of 5P11
Toll becomes "1", and the first word line of 1 to the memory array M connected to Toll] becomes selected.

TN, T'N following 1, TO'2.2 + at 2
TO111 and TO12N are "1", and the memory cell electrically connected to the data path line DB is the memory cell at the intersection of the Nth word line of MA2 and the bit line corresponding to TO'2.2. like this from TN, 1 to TN, M/2
The memory cells previously connected to the Nth word line of MA2 are sequentially electrically connected to the data bus line DB, and at the same time, the first word line of M1 is brought into a selected state. T'N, 4+1, MA, TO'2, 4
The bit line corresponding to TO'2.+1 is electrically connected to the data path line DB and the first word line of MAl is selected. The memory cell at the intersection of the bit line corresponding to child +1 and the first word line is electrically connected to data bus line DB. At this time, TO'2. The +1 signal is set to φ12 and is also input to -CT112, so TO
The signal of 12N becomes "0", the signal of T O] 21 becomes "1", the Nth word line of MN2 is unselected, the first
The word line becomes selected.

As explained above, in the embodiment shown in FIG.
Since word lines can be selected during sequential read/write operations of data in other memory arrays, data bus line DB is always electrically connected to some memory cell. When a one-transistor type memory cell is used, it is necessary to equip the memory arrays MA, MA2 with a sense amplifier circuit. This configuration is particularly effective because it can be performed during a write operation.

The embodiment of FIG. 4 includes two memory arrays MAI.

Although this is an example in which MN2 is provided, the same effect can be expected with three or more memory arrays.

FIG. 6 shows the configuration of a third embodiment of the present invention, which is an example of the configuration in which a second multiplexer circuit MUX' is added to the second embodiment of FIG. 4.

M U X' connects one of the two bits mBL to the memory arrays I't4A1 and
The bit line to be connected to the second data bus line DB' is sequentially determined by the output signal of the designation circuit SP'2. The multiplexer circuit MUX' has exactly the same configuration as the MUX, but the input of the output signal of SP'2 is different;
The signal from MA2's 1st. Second.・・・・・・Input corresponding to the first bit line, TO'2
．． 4+t+TO'2. +2.

...TO'2. The signal from M is the first .
Second. ...While inputs are made corresponding to the second bit lines, TO'2 is input to MUX'.
, 1 s TO'2 , 2...To'2.4
'The signal from MA2's 2nd. 3rd゜...Input corresponding to the second bit line, TO'2
M/2+, TO'2. M/2+1.・・・・・・TO'
2. The signal from M-1 is the first . Second.・・・・・・
...is input corresponding to the bit line of the real child, and T
O'2. The signal from M is input to M in correspondence with the two first bit lines. SP'2, 5P11, 5P12
In this embodiment as well, the signal at the output terminal of MUX
is electrically connected by, but at the same time, M U
DB' and the second bit line of MN2 are also electrically connected by X'. Also in other periods, the bit line to be electrically connected to DB in the next (- succeeding period) is M U
It is electrically connected to DB'i by X'. For example, connect a write circuit to DB, a read circuit to DB',
Only read through UX' and DB', MUX and D
If only writing is done through B, 1 of φ2
Data read out in a certain period defined by the cycle can be changed by an external information processing circuit or the like and written in a period following the above period, thereby speeding up and simplifying data processing.

In the embodiment of FIG. 6, the bit line to which D B' is connected is the bit line to which DB is connected next, and the connection of D B' precedes the connection of DB by one cycle of φ2. However, it may be preceded by one cycle or more.

Further, in the embodiment of FIG. 6, one sequential designation circuit SP'2
is used to control two multiplexers, MUX and MUX', but designation circuits may be sequentially provided corresponding to each multiplexer.

As described above, in the first, second, and third embodiments, the initial setting mechanism of the sequentially designated circuits is omitted, but it is effective if the state of the sequentially designated circuits can be controlled in whole or in part by external terminals. . FIG. 7 shows an example in which a reset circuit as an initial setting circuit is connected to 5P12. Further, it is also useful for controlling the integrated memory circuit to sequentially output a signal representing the state of the designation circuit, for example, the TOll signal in the first embodiment, to the outside.

As described above, according to the present invention, information can be input and output at high speed. Furthermore, an input terminal for specifying an address can be omitted, which is useful for downsizing the integrated memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a time chart for explaining FIG. 2, and FIG. 4 is another embodiment of the present invention. FIG. 5 is a time chart for explaining FIG. 4, and FIGS. 6 and 7 are diagrams showing still other embodiments of the present invention. MA, MA1, MA2...Memory array, MC...
Memory cell, WL...word line, BL...bit line, DB. DB'...Data bus line, SP1, SP2, SP11
, SP12, SP'2...Sequential designation circuit, MUX, M
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Ill, 1, 1

Claims (1)

[Claims] 1. By arranging memory cells at the intersections of a plurality of word lines and a plurality of pit lines, and selecting a portion of the word line, the memory cells connected to the word line and the pit line An integrated memory circuit capable of inputting and outputting data between memory cells, comprising means for sequentially selecting the plurality of word lines, and means for sequentially selecting bit lines in response to the selection of the word lines; An integrated memory circuit characterized in that it is connected to the outside in a predetermined order. 2. In the integrated memory circuit according to claim 1, during the period of selection of a part of the word line and the period of amplification of data taken out from the memory cell connected to the word line to the pit line, other than the above An integrated memory circuit characterized in that the memory cells connected to the word line (-) are connected to the outside. 3. In the integrated memory circuit according to claim 1, the memory in the integrated memory circuit An integrated memory circuit characterized in that a cell is connected to a data output mechanism, and after a certain period of time, the memory cell is connected to a data input mechanism. 4. The integrated memory circuit according to claim 3. An integrated memory circuit characterized in that one or both of the data input mechanism and the data output mechanism is replaced by a data input/output mechanism (two).