JPS5862970A - Picture transmission system - Google Patents

Abstract

PURPOSE:To transmit picture with high quality, by surely transmitting picture data read at a reading section to a recording section, and demodulating a signal independently of the fluctuation of intensity of the recevied signal level. CONSTITUTION:A count circuit 352 measures a time from the leading edge to the trailing edge of a pulse of modulation signal and a time from the trailing edge to the leading edge, at least one of them, and generates a counted output TC. The circuit 352 discriminates whether or not the count value is a prescribed value at a time discrimination circuit 354, and if the count value from the circuit 352 is discriminated as a prescribed interval, a timing control circuit controls the timing restoring the picture data from a modulation signal according to the count value. In response to the output timing of the timing control circuit, the picture data is demodulated from the modulation signal, a demodulation clock pulse CKD is picked up from an FF346 and a demodulation data DS is picked up from a latch 349.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image transmission system, and relates to an I! #5 is concerned with a preferred image transmission method in which image transmission is carried out by means of air communication.

High-speed communication is possible when the image reading section and the image recording section are separated and the image signal read by the reading section is supplied to the recording section via a predetermined transmission path for recording. , and a transmission method that reliably reproduces the image signal is desired.

As an example of such a transmission method, the present inventors generate a pulse frequency modulated signal by applying pulse frequency modulation using zt image data to a clock signal, and transmit the modulated signal through a predetermined transmission path. A system has been devised in which the image data and clock signal are decoded from the modulated signal to perform image arrangement.

In this method, the slice point moves depending on the strength of the received signal when reproducing signals on the receiving side, that is, the indulgence section. The effects are different, and therefore the pulse width of the reproduced waveform may differ from the pulse width of the original waveform.

The object of the present invention is to eliminate such drawbacks 1B and to improve the signal strength 1II1.
It is an object of the present invention to provide an image transmission device capable of performing high-quality image transmission by performing pulse frequency modulation without causing any adverse effects.

Hereinafter, the present invention will be described in detail with reference to the KFf4° plane.

Fig. 1 shows an example of an image transmission device to which the fJiJ of the present invention is applied, where tc and too are distributed reading units, which transmit images of sheet-like originals to a one-dimensional optical image element, such as a COD line image. It is read with Jinansa and converted into a chronologically arranged art relationship data VDM. This image data VDA
viIk child, this - image data 1 and record m5oo
'Mem work-1t't; 4ri l>II) Instruction 7'-fic
DIII! These signals (hereinafter referred to as data signals Da
4 (or MFM).

The output No. 4N of the pulse frequency ridge change circuit 11, that is, the pulse F'MM No. FMlil g is supplied to the transparent part 5001'c,
A built-in light emitting element 501, such as a light emitting diode or a laser diode, is driven.

The light emitted from the light emitting element 501 is transferred to the lens 50! The light is focused into a light beam Lt, and from this point the beam Lt t - ceiling fathom 4
c Supply to the attached light receiving unit Too ・Light receiving unit 700
A built-in light receiving element 701, such as an avalanche photodiode, converts the strength of this light (-^Lt) into a signal at once, and excludes the aforementioned 9-pulse FM signal FMS.

This signal FMSt is supplied via the coaxial cape A/1loo.

The recording section 300 extracts the image data VD% sorting control clock WCK and the command data CD from the supplied pulse FMg number N8, and the recording section 30o performs predetermined Idi recording performance based on these respective signals. .

FIG. 3 shows an example of the reading mechanism of the reading section 100, where 1'o1 is the sheet-like original %102, and 103 is the original 10.
A feeding roller that feeds the document 101 in the direction of arrow B, and a platen whose document feeding path is W6KW&V from 4o4i, and the image of the lower surface of the document 101 passing through the position of this platen 104 is read at once. 105 & processing The function of holding down the original 101χ and forming a well-focused image is the 9th original feeding function. 106 and 107 are document position detection means for detecting the paper edge of the document 101;
0 paper edge is from light emitting element 106 to light receiving element 10? Detects the point at which light is obstructed from progressing to the target.

This detection signal is used to control the recording section 300.

10B is a bar-shaped light source for document illumination, such as a halogen lamp, which illuminates the reading position of the platen 104 from below.
09 is a folding mirror, and the document 1 passing through the reading position
The image light Lr f reflected at 01 is turned back as shown in the diagram. 11G is an imaging lens, and the image ml light Lr 1k
The COD line image sensor 111 receives light and functions to create an upper KM image. This CCD line image sensor converts the imaged image light Lrv to VDAK time-series image data of a predetermined number of bits.

Figure 4 shows the recording mechanism of recording s3oo, where 30
1λ is the first recording mechanism, and sat ii is the second recording mechanism. In this example, these two recording mechanisms are used! Assuming that the four structures of 101A and 301B are exactly the same, the entire brass mechanism is
Regarding the II code f 8014, a code "mu" or rBJ is added to distinguish between the first recording mechanism and the second recording + S structure, and the code indicating the details of the recording mechanism is the same for both ML recording mechanisms. Attach.

gl&! Recording mechanism 301A and second recording mechanism 301B
each includes two recording heads, for example, inkjet heads 302o and 303v. Each inkjet head is a full-line 2-infusible inkjet head in which a plurality of recording elements are lined up in a straight line in a direction perpendicular to the drawing in FIG. Record 0
In this example, the inkjet head SO1 prints 16 dots/
It is assumed that the black normal mode recording of (3) is carried out, and the inkjet head 3o3 is used for the red normal mode recording of 8 dots per square.

Each recording mechanism! 01 A and! 101B are vertically stacked in two stages by a support (not shown).

-304 is a recording paper storage cassette) 305 is the recording paper stored in this cassette, 3o6 is a paper feed p-ra.

301 is the guide plate% 308 is the registration roller, 3θ9
31o is a platen with a large number of pores, 311 is a fan, 312 is a second conveyance roller,
sls+tM rack a-y, 314 G! W& delivery help)
, 315 C is a paper discharge tray, 31@ and 317 are ink tanks.

Next, the recording operation in the above mechanism will be explained. Except for the inkjet heads 302 and 303 being selectively used according to the signal sent from the reading unit 100, the two recording mechanisms 301A and 301B perform the same operation. Therefore, only the recording mechanism 301AK will be described here.

Paper cassette), 304K storage paper 305
By the rotation of the paper feeder 1 2306, the paper is fed along the 30 guide plates to the registration row 2308, which has stopped rotating, thereby forming the proper roof 1'. Next, as the registration roller 308 rotates, the recording paper is transferred to the registration roller 308.
The inkjet heads 302 and 303 are held by conveyor rollers 109 and transported toward the inkjet heads 302 and 303.At this time, on the opposite side of the inkjet heads 302 and 3G'l, there are platens 310 and 7A having small holes. 31
1 is placed in the box, and the rotation of the fan 311 blows air into the box in the r direction. Therefore, the first transport row 230
9, the recording paper 305 is pulled out from the fan 311K and placed on the platen 310? :Second feed roller 31
It is transported in two directions. In the process of this transfer, depending on the image data VD from the CCI) line image sensor 111, which is supplied to the inkjet and the RAD 302 or $03,
Recording is performed by the CC excitation circuit. Recording body, recording paper: a
When the leading edge of the OS is transferred to the second transport row 2312, the recording paper 305 is ejected to the paper ejection tray 31J by the second transport row 9312 and the transport bell 31'4.

FIG. 5 shows the control circuit of the reading section 1000 and the light transmitting section 500, where K111 is the above-mentioned COD line image sensor, and the drive circuit 113 is controlled by the tie-setting signal from the timing control circuit Jll12.
, and the time-series image data vDA' is generated. A quantization circuit 114 quantizes the image data. Transmission control circuit 11 for child-like image signal VD
Supply to 5. Reference numeral 116 is a central I&F device, which includes memory l consisting of random access memory, read-only memory, etc.
The operation of each part of the reading section 100 is controlled according to a control program written in the I-F. 11s is a reading mechanism control boat, which sends a blinking signal to the halogen lamp 10B, a drive signal to the brake and clutch for rotating or stopping the feed rows 102 and 103, and sends a drive signal to the document position detection devices 106 and 107. Receive a spider detection signal. A console input boat 119 receives recording unit control signals from a control console 121 placed on the cover 120 on the top surface of the reading unit 100. The control console 121 has four buttons 121a to 12111 for selecting the recording mechanism and recording color, a recording start button 121, and a cancel button 121f.
i have When the button 121a is pressed, the transmitted image data VD is supplied to the black inkjet head 302 of the #Il recording mechanism 301, and recording is performed using ink.

The following table shows the relationship between each button, recording mechanism, and recording color.

122 is an instruction data boat, and a recording mechanism 301A
and command data CD'? for controlling the recording operation of 301B. :Supplied to the acceptance control circuit 115.

Send 123! M#' is redundant and sends out a transmission control circuit for controlling its operation to the transmission control circuit 115. The transmission control @1!115 transmits image data or command data baud supplied from the quantization circuit 114 according to the transmission control signal and the tie-up signal.
Command data CDK supplied from K performs predetermined processing and its output signal (data signal) DSv frequency modulation circuit 12
Supply to 4.

In this embodiment, in order to distinguish between one image data ■ and command data CD, as shown in FIG. Command data header CM
't-add. Data signal D with these headers added
li k is supplied to the pulse frequency modulation circuit 124. This pulse FM circuit 124 receives the supplied data signal DBK.
Therefore, the four clock signal CKM supplied from the timing control circuit 112 is pulse frequency modulated.

The output FM8 of the modulation circuit 124 is sent to the fJD driving amplifier 1!
5 K is supplied, and the output light of the light emitting diode 501t'l[l1ll of the light transmitting section SOO is outputted from the light emitting diode 6 (tt/), and as mentioned above, the output light t of the light emitting diode 6 (tt/) is outputted by the lens 6G2.
is focused to form an original beam L1, and this beam Lt is supplied to the light receiving section yoo. - Figure 7 shows the control path for recording s3oo' and the light receiving section 70.
0'' and the light beam Lt from the aforementioned i-tip SO'O
is converted into an electrical signal, i.e., an iFM signal FMg, by an avalanche photodiode 701.
oz□yu. 4j*'FM&. , f□. , -1A9, and some output signals are supplied to the recording section SOO's 1132G * via the above-mentioned coaxial cable 900t. Bandwidth increase -1! The output signal of 32G is supplied to the V-circuit 321.

uI! The chest circuit 321 extracts the demodulated clock 1d signal CKD and the demodulated data signal D8 from the supplied signal FMS, and supplies the clock signal CKD to the timing signal generation circuit 322. This circuit 322 generates a write-out clock signal 0W. This signal 0W is the recording mechanism 30
It is used to control the timing of writing 1A or so't'a. The demodulated data signal DB' is supplied to the serial-parallel conversion circuit 323. This conversion circuit 323 is
- Demodulated data signal DB% which is a serial (time series) pulse signal: Parallel (parallel) pulse signal P8
K conversion is performed and this t is supplied to the image header turtle detection circuit 324, instruction header CH detection circuit 32S and latch circuit 326, and 1. Serial pulse signal D8t is delayed for a predetermined time and is supplied to the gate circuit 327. .

When the image header detection circuit 324 detects the image header vnt' shown in FIG. 6, ijigI! Header detection signal Vkl
B is supplied to the gate circuit 327K [this gate 327 is opened, and the image data vDv recording mechanism 301 or 30111K [at that time] is supplied directly or indirectly via the image memory soxMy that temporarily stores the image data. When the instruction header detection circuit 325 detects the instruction header CHt- shown in the sixth column, it generates an instruction header detection signal CHB. This signal cns is supplied to a circuit 328, delayed by a predetermined number of bits, and supplied to a latch circuit 326 as a latch signal.

As a result, the latch circuit 326 latches the command data signal CD when parallelization is completed. This command data signal CD specifies an interrupt request, start timing, recording mechanism 301 or 301B to be used, recording color, etc., and the recording mechanism is controlled according to this signal CD. 'The image header detection circuit 324 and the instruction header detection circuit 325 also supply the "detection JtK" signal via the OR circuit 329 to the dead time generation time *33G at the time of detecting each header.

Dead tie,, 1 kakaki. . Eh. Yukake 9, 1,
1 deck 4.2 im believe 4DTsy@live. This dead time i is applied to each header detection circuit 324 and 325.
1-1 to No. 1 DTSt. This dead time signal
I'll, the respective header detection circuits 324 and 326 cease operation. This results in
If the image data VD contains l1lii image header Vkl
Alternatively, even if there is a part with the same bit configuration as the instruction header OR, this is done so that it will not be detected as the header VH or CI.

Figure 8 shows an example of the circuit configuration of the pulse 1 circuit 124 in the reading 510G, where 13G is the positive edge detection
The etch signal CKM supplied from the timing control circuit is supplied to these etch detection circuits 13G and 131, and the latch circuit 132 is a latch circuit. The latch signal input terminal LK of the latch circuit 132 is supplied.Data No. 11 DS (see FIG. 6) supplied from the transmission control 1 path 116 is supplied to the data/hexagonal terminal DK of the latch circuit 132.

The latch circuit 132 latches the data signal DB4 in accordance with the positive edge of the clock signal CKM. AND circuit 13! to negative edge detection pulse NIP of negative edge detection circuit 131 and output signal LD1 of latch circuit 1m2. l
K, its output As and positive edge detection circuit 130
The positive edge detection pulse PICP is supplied to the Y-OR circuit 134. Output of OR circuit 134 TPt-2 Turtle counting circuit 1
35 as a toggle pulse. 2 overcount gang road 13
5 output, that is, pulse FM ij1 FM8 tt
, as mentioned above, LED drive lid) 14111m device 1
Supply 25K.

The operation of this love adjustment circuit 124 is as follows.

First, if the data signal D8 is in the state of "0", the output LD of the latch (b) path 132 also maintains the state of "0", and the output cam S of the AND circuit 133 also maintains the state of IOJ. Therefore, the output TP of the OR circuit !34 becomes rlJ only during the period when the positive edge detection circuit 130 detects the positive edge of the p-clock pulse CKM and sends out the positive edge detection pulse PEP. The level of the output FMS is inverted every time the pulse TP is output from this OR circuit 134.

That is, when the data signal DB is "O", the output FMS of the binary counting circuit 135 is equal to the time interval of the positive edge Pg of the clock pulse CKM (auxiliary 'r of the clock pulse CKM).
cicm time interval).

On the other hand, assume that the data signal D8 becomes IIJK at a certain point in time, as shown in FIG. In addition, "?" in the waveform diagram
" sign indicates that the contents of the subsequent data signal DB are unknown. The latch circuit wr132 latches this "1" signal in accordance with the positive edge PIi8 of the clock pulse 0α, and the output LD becomes "1". 11 mountains become pa. Next, when the negative edge of the clock signal CKM arrives, the negative edge detection circuit 131 generates a negative edge detection pulse NEP%. Therefore, this detection pulse NgP is rlJ''!: During a certain period, the output AS of the AND circuit 133 becomes "1", and this output signal 8 inverts the level of the output image of the binary counting circuit 135.

That is, when the data signal DS is "1", the output FM8 of the binary count @ is inverted not only to 5 when the positive edge PI of the clock pulse CKM arrives, but also to 1 when the negative edge PE arrives. The interval is half the period CKM of the clock pulse CKM.

Therefore, on the recording section 3oo side, this pulse FM if1
When detecting the difference in the time interval of level reversal of No. FM8,
Therefore, the data signal Ds can be reproduced.

FIG. 10 shows an example of the circuit configuration of the demodulation circuit 3210 of the recording section 3oo. In particular, 380 is an internal clock signal generation circuit, which generates an internal clock pulse CKI. In this embodiment, the period TCIC of this internal clock pulse CKI
I is set to 1/16 of the period 〒- of the clock signal port l that supplies the pulse FM circuit 124K of the reading section 1oo.

The positive edge detection circuit 33 detects the internal ripple signal CKI! .

Negative edge detection circuit 332. Counting 1 path 333 and Antoge) 334 K supply. Supplies positive and negative edge detection. These positive and negative edge detection circuits 331 and 3
32 generates positive-going and 1oJ edge exit pulses pgop and NIDP, respectively, in synchronization with the internal clock pulse CKIK when positive-going and negative-going edges between the signals arrive, respectively.

° Positive direction edge detection pulse PEDP 4t AND gate 335, OR gate 3!8, 7 lipf 4t 337
and is supplied to the timing coordination delay circuit 338.

Negative edge detection pulse NEDP v and gate 33
9, supplies the OR gate 336 and the flip 7p tube 337. The AND gates 33s and 339 have an edge selection output E8L from an edge selection circuit 350, which will be described later.
Q is also supplied. These AND gates 335 and 33
Shift register 3 as a delay a circuit with output t of 9
Supplies 4G and 341. The outputs of the shift registers 340 and 341 are respectively supplied to an OR gate 344 which determines the starting point of the bit 7 frame via a selection circuit 342; Aritsubu flop 345 to separate
The set input terminal 8 and the reset input terminal RK are supplied. When the OR output of the OR gate 344 is supplied to the reset input terminal R of the counting circuit 333 and the reset input terminal RK of the Aritz flop 346, the counting circuit s33 is reset by the output of the OR gate 344 which determines the starting point of the bit frame and starts counting. , whose counting output CT is converted into a timing occurrence j! in the form of a binary-32 overdecoder. ! 347 JC supplied. @l′ output, @o” output and ′″ during the output of decoder s47
8" output to the reset input terminal Rs of the 7-rip 7p knob 348, the 2-twin pulse input terminal of the 7-pin 349, and the set input terminal S of the flip 7p knob 346, respectively.
supply to. For example, @O" to @45" of the decoder 347
It is supplied to the output edge selection circuit j1350. For example, as shown in FIG. 11, this edge selection circuit SSO can be configured with 1-OR 16 selectors 401 and 402, 7-lip 70-tube 403, and read-only selector 404, and each enable input terminal E of selector 401# and 402 is supplied with the output from the Arriv flop 345, that is, the bit edge output indicating whether the bit boundary is a positive edge or a negative edge. As inputs to selectors 401 and 4020, @O"~015" in the output from decoder 347
The output is supplied, and as a selection input for each selector, the time from a positive edge to a negative edge, or conversely from a negative edge to a positive edge, of a b-bit configuration, from a latch 353 to be described later. The edge selection output ESL is taken out at the timing of the decode output that coincides with the number 4N read from the read-only memory 404 based on the latch output KEEb. When the ESL output is @1', it represents the selected output detection function state indicating the data period of the modulation signal FM8, and the ESL
When the output is @O''', the edge of the FMS signal data itself can be detected. 1':' Edge selection output EEL from edge selection circuit 350 and OR gate 351
supply to. The output of the inhibit gate 361 is supplied to the set input terminal SK of the arrest flop 348.

The output of the flip-flop 348 is supplied to a data input terminal D6C of a latch 349, and demodulated data DS is taken out from this latch 349.

The other input terminal button of AND gate 334 supplies the output of flip-flop 337. 7ritsugu 7 (ytsubu 3
The output of 37 generates a timing gate 46 TG8 that occurs on the negative edge of the data and is reset on the same positive edge, and determines the number of clock pulses CKI that pass through the AND gate 334 while the TGS output occurs. A clock circuit 352 counts and generates a clock output τCV. The reset input terminal R of the clock circuit 352 is supplied with the delayed output from the -M#L circuit 33B. Here, the output TC at 1F is the data FMS
represents the time from the negative edge to the positive edge of .

This total is 1! ) - provides the output TC to latch 353 and latches it during the occurrence of its latch enable input. Timing output TC'g.

The signal is also supplied to a time determination circuit 354, which determines whether the output TC at lrr has a period corresponding to one bit of the data FMS. Discrimination output of time discrimination circuit 3154 and delay circuit ss8
The delayed output of 2 and 353 is supplied to the AND gate 355, and the AND output is used as the latch enable signal of 2 to 353.

゛ With the above configuration, the 7 logic flop 346 extracts the demodulated clock pulse CKD 'g, and the latch 349
Demodulated data DS from Jul! ? ,put out.

Next, while referring to Figures 12 and 13,
The operation of the illustrated return circuit will be explained. In general, as shown in Figure 53, the received wave-signal FM for the original data Dm↑
S is the non-direction of the enclosure system depending on the received signal strength! The pulse edge shifts due to the I characteristics and the shift of the slice point. Moreover, the size of the edge shift in the positive direction and the negative direction τ, and T
, are different, so for the bit time width τ0 of the original data,
The pit time width t of the demodulated data Da is t=τ. -(T, -fp), and therefore the deviation Δt between τ and t is.

There are four relationships yx: n, p, 0. From this, for the positive direction edge, the time correction is performed as τb i =L + Δτ, and for the negative direction edge, the pulse width is set to the same value as τb1mm (1-11, is the specified pulse time width). During extraction, edge deviation in both the positive and negative directions is eliminated. More specifically, when Δτ〉O, when the 6-bit break of the data is a negative edge, K is the detection timing of the data edge when the next data edge appears early by tΔτ, and conversely, if the edge is in the positive direction. At the time of an edge, the next data edge appears with a delay, so the start of the data edge is delayed by ΔT.

Therefore, in the present invention, the reproduced metal 1114M4Irh
A clock circuit 35 measures the pulse time width of each data bit of IiB.
2''ell, and the time width, that is, the time from the negative edge to the positive edge tv time discrimination times τ,
/ Determine whether it is shorter. In reality, it is preferable to judge the length of the time t based on the 3/4 bit time, which is longer than the i-bit time, for example. The above-mentioned 374 guns is input as a reference value, and it is determined whether the time t as a time measurement output is longer than this reference value. Then, when the time t is longer than 374"o, 11" is obtained as the discrimination output. Here, in order to transfer and latch the clock output from the clock 1 circuit 352 to the latch 853, the AND gate 355 has a discrimination output, this delayed output, and a 0 discrimination. The output is a delayed output τ
At the timing d, the signal passes through the AND gate 3s5 and is supplied to the latch 353k, and the latch 353 is enabled to open twice, and the time measurement data tt' at this time is latched. The latch contents L8 are as shown in Figure 12. The memory 404K of the edge selection circuit 350 stores the data edge corresponding to the predetermined time interval Tp and τ7 in response to this latch output fall, and selects the data edge of the decoder 34γ or 6 according to the signal read in response to the latch output L8. c) I fwa. □,
]...4.1 ka, 2□401 ka, decide on the timing.

Therefore, an edge selection output 18L, which is detected according to the line time tK, is obtained from this edge selection circuit $10. This output EBL is an edge detection output indicating the data period,
and an edge O detection output indicating the data itself, the former enables AND GO (335%) and 339, and the latter enables AND GO (311).

In other words, when the EEL output is @l'', the AND gate 3
35 and 339 and edge detection pulse pmp and N)! :DP to each shift register $40 and 341
K transfer, and when EEL output is @O'', prohibit gate 1
51 t-open or goo) 33@Kamo edge detection pulse PEDP 51 is set to 7 lips 70 teeth 348 by hanging DP. As a result, the latch 341Kt
The clock signal is latched by the timing when the 10" signal is generated by the decoder 34γρ, and the latch output is taken out as the demodulated data DI. Regarding the clock signal, the positive direction of the FMs4M signal or OR gate 344 in response to any edge in the negative direction
After the 7-bit 170-1346 has been reset by the OR output of use

In addition, in the above, the frit 1 flotz 1331 is set at the negative edge and reset at the positive edge.
However, instead of setting it to 5, it is of course possible to set it at the square potter or the tree and reset it at the negative edge. The time discrimination circuit 35 is used for the seventh occasion.
4, the time width from the positive edge to the negative edge is compared with a reference value. Alternatively, it is also possible to measure the time from the negative edge to the positive edge and the time from the positive edge to the negative edge, and perform time discrimination based on both time data.

In the example shown in FIG. 12, the data signal D to be transmitted
8 is "1", the pulse FM signal FM8 changes from the "negative edge" to the "positive edge" and then to the "negative edge" at the level VIiL. Of course, there is a level inversion representing "l".

This demodulation circuit 3! l output, that is, demodulated data DB
As shown in No. 7, the demodulated black signal port (2) is supplied with the serial/parallel back circuit 323s and the timer signal generator H1 & 322flC, and the recording operation is performed based on these signals. In this case, the demodulation link signal CKD generated in the demodulation circuit N2 is completely synchronized with the transmitted pulse N signal FMgK.Therefore, distortion occurs in the edge-to-edge and O time intervals as described above. Even in this case, by operating the microprocessor, recording mechanism 301, etc. based on this demodulated clock pulse port (2), the data signal D8 can be correctly reproduced.

That’s all! As explained above, according to this IA, the image data etc. read by the facial recognition section are transmitted to the t1 generation section, and the signal is demodulated regardless of fluctuations in the received signal level. This enables high-quality image transmission.

[Brief explanation of drawings]

Figure 1 is a layout diagram showing an example of an image transmission device embodying the present invention, Figure 11 is a layout diagram showing an example of data transmission using spatial optical overconfidence, and Figure 3 is an internal diagram showing an example of the configuration of a reading section. The configuration diagram, No. 4g is an internal configuration diagram showing an example of the IIO configuration, No. Bg is a block diagram showing an example of the configuration of the control circuit of the reading section and the light transmitting section, and FIG. 69 is the bit configuration of the data signal. -Example Meeting Figure 7 shows an example of the configuration of some of the split circuits and the light receiving section. The diagram is llN3! l! Time chart of the circuit shown in cl, No. 10
The figure is a block diagram showing an example of a demodulation circuit, No. 1111 is a block diagram showing an example of the data edge detection path, No. 1
Figure 2 is a time chart of the circuit shown in I11G-, and Figures S and 13 are time charts explaining the time lag in data. Lt...Original beam, Lr...Reflected light from the original 1,,'. ■Mu・-Image data taken by COD, T...Blowing direction, ■...Quantized image data,
CD...Instruction data, D8...
・Data signal, (generic term for 1N image data and command data) ・Output of pulse frequency modulation circuit (pulse FM signal)
WCK--Folding control clock. 1 ・-Document feed direction, ・-m sideways view, (
10G--demodulation clock signal, CKW--write control clock, P8-z<9rel pulse signal, cni---modulation clock signal, tcnt--
・・Clock signal period, ■-#I image header, cn
-Instruction header, ■8-iii image header detection signal, CHB
...Instruction header detection signal, DTIi--dead time signal, NIP--member edge detection! (Russ, LD -...
Latch circuit output signal, M8...AND circuit output, Pli8F-...Positive edge detection pulse, TeP...OR circuit output, P8...Positive edge, Nl-*edge, CKI...Internal Clock pulse, IDP-・Edge detection pulse, ZS
- Edge selection signal, MU8C - ANDijI output pulse, 18F-7 lip reset pulse, LP - -
・Latch pulse, FFO・-BJi7 lip 70'
Tube output, CO...count value, ThK
w=period of internal clock pulse, 8P...and @step output pulse, 100-...reading section, 101...sheet-like original, 102, 103...feeding roller, 104...platen, 10 tons...
Original feed guide, toe...detection element, 10
? -... Light receiving element, 10g = - Rod-shaped source, 10
9--Folding mirror, 110--Imaging lens,
111・-CCD line image sensor,
112...Tinging control circuit, "113
・-CCD drive ll1i1 circuit, ti4... quantization circuit, 115... transmission control circuit, 1lli... CP
U. 117...Memory, 118-...Reading mechanism control port), 119...
・Console input port, 12
G...Reading section top cover, 121--Control console, 1'21a~1-Push gourd button, 122...
command data baud), 12S...transmission control port, 12
4... Frequency change iIi111gl path, 1.25...
・LED drive amplifier II & device, 130...Positive edge detection circuit, 1B1...Negative edge detection circuit, 132...
・Latch circuit, 133...AND circuit, 134...
OR times M, 135...Binary stitch number circuit, 30
0...Recording unit, IoT module-111g le recording mechanism, 3ulB-i
g 2 Brass Isokai, 301M--Image memory,
5O2-inkjet head (mushi), 30B...
Inkjet head (red), 504
-・Brass storage cassette, 5os-1 brass paper,
30@proboscis paper feeding rots, -107-...guide plate,
sos...sitast 0-2.309...j
ll14D transporting rollers, 310...gutten, 31 one fan, 31 second shaft conveying roller,
313... Track roller, 314... Conveyance belt. , 1111-1 paper output tray, 311! ,! 17.
- Ink tank, 3 snow - Narrowband amplifier, 321・
-Return IIl path, Sm1-・Making signal IA raw circuit,
323・-Serial parallel conversion circuit, 'A2fi--
-Image header detection circuit, 742m---Command header detection circuit, m2@-...Latch circuit; 1! ? -...Gate circuit, 3! lI--Delay circuit, 819--OR path, 311--Positive edge detection circuit, 312---Negative, edge detection tBa path, 3
31=number of stitches-tread, 1S4. Hi, 339.3SS-...
ANDGATE, S:I6,344...ORGATE,
317.34s, 346,348...7 rigs, 70 tubes, 338-...delay circuit, 340.341
-...Shift register, 342,343...Selection circuit, 347...Decoder, 349,353...
...Latch, 350...Data edge detection path, sbl...Inhibition gate 1, 35T...Clock circuit,
354...1g1j by time sequence'! , 38G...
Internal clock generation circuit, -401,40! -... Selector, 403... Relig frog, 404-... Read only memory, 500... Sending part, 601... Detection element, BO2-... Lens, 70G... Light receiving part, 701 ...Photodetector, 70 totes/preamplifier, 9 (1G...coaxial cable) Patent applicant: Yanon Co., Ltd.: '1: Figure 4

Claims (1)

[Claims] l) Adding pulse frequency modulation to the clock signal using binary image data; [generating a pulse frequency change signal, and supplying the change modulation signal to the repeater circuit via a transmission line; In the second image transmission method, the demodulation circuit demodulates the clock signal and the image data from the received modulation signal and records the image. Determine whether or not the time values from the clock circuit that measures the time to the edge and the time from the falling edge to the rising edge are within a predetermined time interval. When the time determination circuit and the armpit time determination circuit determine that the time value is within the predetermined time interval #C, control is performed to demodulate the image data from the modulation signal according to the time value. a timing control circuit for demodulating the image data from the modulation signal in response to the output timing of the timing control circuit; and data demodulation means for demodulating the image data from the modulation signal in response to the output timing of the timing control circuit; 2. The image transmission method according to claim 1, wherein the predetermined time interval is is the time interval corresponding to one of the logical values of the data.