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JPS5862766A - Projecting operation device - Google Patents

Projecting operation device

Info

Publication number
JPS5862766A
JPS5862766A JP56162431A JP16243181A JPS5862766A JP S5862766 A JPS5862766 A JP S5862766A JP 56162431 A JP56162431 A JP 56162431A JP 16243181 A JP16243181 A JP 16243181A JP S5862766 A JPS5862766 A JP S5862766A
Authority
JP
Japan
Prior art keywords
storage means
screen
video signal
main storage
transfer control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56162431A
Other languages
Japanese (ja)
Inventor
Daisuke Ogawara
大河原 大輔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56162431A priority Critical patent/JPS5862766A/en
Publication of JPS5862766A publication Critical patent/JPS5862766A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06VIMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00Arrangements for image or video recognition or understanding
    • G06V10/40Extraction of image or video features
    • G06V10/50Extraction of image or video features by performing operations within image blocks; by using histograms, e.g. histogram of oriented gradients [HoG]; by summing image-intensity values; Projection analysis
    • G06V10/507Summing image-intensity values; Histogram projection analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Abstract

PURPOSE:To perform high speed processing with a simple hardware, by binarizing a video signal, storing accumulated data in the longitudinal direction of screen, and transferring the content to a main storage means via a DMA transfer control means. CONSTITUTION:An input video signal is converted into a white or black binary coded video signal at an AD converter 1. This signal is given to a 8-bit counter 2 to count the number of white signals from the beginning of one horizontal scanning to the end. The number of white signals being the content of the counter 2 during the horizontal blanking period is transferred to a main storage means 4 via a DMA transfer control means 3. Through the sequential horizontal scanning for this operation, a projection data to the vertical axis of a screen is obtained at a main storage means 4. Further, a binarized video signal is inputted to a 8-bit adder 5, where the signal is summed with the projection data and the result is written in a shift register of a temporary storage means 6. The content of the means is transferred to the main storage means 4 via the DMA transfer control means 3 and the projecting operation for one screen's share is finished within the scanning time of one screen.

Description

【発明の詳細な説明】 本発明はTVカメラよりのビデオ信号を2値化した後の
データ処理に関するものである。第1図は2値化した画
面の白又は黒をX軸、Y軸に投影演算した様子を示して
いる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data processing after a video signal from a TV camera is binarized. FIG. 1 shows how white or black on a binarized screen is projected onto the X and Y axes.

従来投影演算は第2図に示すように、入力ビデオ信号を
、AD変換器1で白又は黒の2値化ディジタルビデオ信
号とし、この信号をバッファメモリ8に入力し、1ビツ
トの直列データを数ビツト保持し、並列データに変換し
た後、DMA転送制御手段3を介して計算機の主記憶手
段4に送る。
In the conventional projection calculation, as shown in Fig. 2, an input video signal is converted into a white or black binary digital video signal by an AD converter 1, and this signal is input to a buffer memory 8, and 1-bit serial data is converted into a digital video signal. After holding several bits and converting it into parallel data, it is sent to the main storage means 4 of the computer via the DMA transfer control means 3.

この主記憶手段4に格納された画面データに対してソフ
トプログラムにて投影演算を行っていた。
Projection calculations were performed on the screen data stored in the main storage means 4 using a software program.

その為に画面データを主記憶手段4へ転送するのに1画
面の走査時間が必要であシ、更にこれに加えてソフトプ
ログラムで9演算時間がかかり、処理速度がおそいとい
う欠点があった。本発明は上記従来の欠点を解消し、高
速な処理を簡単なハードウェアで行うものであり、以下
にその実施例を第3図〜6図に基づいて説明する。
Therefore, it takes time to scan one screen to transfer the screen data to the main storage means 4, and in addition to this, the software program requires 9 calculation hours, resulting in a slow processing speed. The present invention solves the above-mentioned conventional drawbacks and performs high-speed processing using simple hardware. Examples thereof will be described below with reference to FIGS. 3 to 6.

第3図において、1はAD変換器、2は8ビツトカウン
タ、3はDMA転送制御手段、4は計算機の主記憶手段
」6は8ビツト加算器、6は一時記憶手段の256 X
8ビツトシフトレジスタ、7は全体の動作制御となって
いる。上記構成において、第3図の投影動作を模擬的に
表わしたのが第4図で、画面の縦×横を266X256
分割し、その1列1行で動作を説明する。
In FIG. 3, 1 is an AD converter, 2 is an 8-bit counter, 3 is a DMA transfer control means, 4 is a main storage means of the computer, 6 is an 8-bit adder, and 6 is a temporary storage means 256X.
An 8-bit shift register 7 controls the overall operation. In the above configuration, Fig. 4 is a simulated representation of the projection operation shown in Fig. 3, and the length x width of the screen is 266 x 256.
The operation will be explained using each column and row.

第3図において、入力ビデオ信号をAD変換1で白又は
黒の2値化ビデオ信号に変換する。この信号を8ビツト
カウンタ2で、1水平走査の始まりから終りまでの白の
数を計数する。第4図の例では、j行i列までの白の数
は4となっている。これを最後の1=2664での1水
平走査の間、白の数を計数し、その後の水平帰線時間で
カウンター2の内容である1行の白の数を、DMA転送
制御手段3を介して主記憶手段4へ転送する。このカウ
ンター2の内容は1行の投影データであり、転送が終了
すればj+1行で同じようにカウントする。順次この動
作をj ==256まで繰返すことによ)、画面の垂直
軸への投影データが得られる。
In FIG. 3, an input video signal is converted into a white or black binary video signal by AD conversion 1. This signal is used by an 8-bit counter 2 to count the number of whites from the beginning to the end of one horizontal scan. In the example of FIG. 4, the number of whites in row j and column i is four. The number of whites is counted during the final horizontal scan at 1=2664, and the number of whites in one line, which is the content of the counter 2, is counted through the DMA transfer control means 3 during the subsequent horizontal retrace time. and transfers it to the main storage means 4. The contents of this counter 2 are one line of projection data, and when the transfer is completed, the counter 2 counts in the same way at line j+1. By sequentially repeating this operation until j ==256), projection data on the vertical axis of the screen is obtained.

一方第3図及び第4図において、前記2値化ビデオ信号
は8ビツト加算器6に入力している。第4図の場合この
加算器6の他方入力には一時記憶手段6のシフトレジス
タよりi列に相当する部分の今までの投影データ2が入
カニされている。すなわちこの直は1列のi−1までの
垂直方向投影データである。
On the other hand, in FIGS. 3 and 4, the binarized video signal is input to an 8-bit adder 6. In the case of FIG. 4, the other input of the adder 6 receives the previous projection data 2 of the portion corresponding to column i from the shift register of the temporary storage means 6. That is, this line is vertical projection data up to i-1 in one column.

の1を加算器5で加算し、その結果の3が再び一時記憶
手段6のシフトレジスタに書込まれ、i列の投影データ
が更新される。以上の垂直方向の投影操作は画面走査の
最小単位時間、す5なわち第6図において、”*]の時
間内に全て行なわれる。
1 is added by the adder 5, and the resultant 3 is again written into the shift register of the temporary storage means 6, and the projection data of column i is updated. All of the above projection operations in the vertical direction are performed within the minimum unit time of screen scanning, that is, the time indicated by "*" in FIG.

次にビデオ信号がP   ・になれば一時記憶手段i+
1.1 のシフトレジスタ6は1つシフトして次の8ピツトデー
タを読出し、同じ動作を繰返す一時記憶手段6のシフト
レジスタは画面の縦横の分割と対応し、256x8ビツ
トの構成でリング状に接続され、ビデオ信号2値化サン
プルパルスと同期してシフトを行う。このようにして最
後の1==256゜5=26eまで走査が終ると、一時
記憶6には画面の水平軸への投影データが保存されてい
る。この直後の垂直帰線時間を利用して、一時記憶手段
6の内容をDMA転送制御手段3を介して主記憶手段4
へ転送する。以上で1画面の走査時間内に1画面の投影
演算を終了する。
Next, when the video signal becomes P, the temporary storage means i+
1.1 The shift register 6 shifts one position and reads the next 8 pit data, and repeats the same operation.The shift registers of the temporary storage means 6 correspond to the vertical and horizontal divisions of the screen, and are connected in a ring shape in a 256 x 8 bit configuration. The shift is performed in synchronization with the video signal binarized sample pulse. When the scanning is completed in this way up to the last 1==256°5=26e, the projection data on the horizontal axis of the screen is stored in the temporary memory 6. Utilizing the vertical retrace time immediately after this, the contents of the temporary storage means 6 are transferred to the main storage means 4 via the DMA transfer control means 3.
Transfer to. With the above steps, the projection calculation for one screen is completed within the scanning time for one screen.

なお上記実施例において、一時記憶手段6をシフトレジ
スタとしているが、他のランダムアクセスメモリでもよ
く、要はスピードが速く、ノ・−ドウエア構成が簡単で
あればよい。又画面を256X2’66分割とし、カウ
ンター2、加算器6を8ビツトとしているが、画面分割
に応じて変えればよい。データを白として動作説明を行
なった75に逆に黒でも扱える。
In the above embodiment, the temporary storage means 6 is a shift register, but any other random access memory may be used as long as it is fast in speed and has a simple hardware configuration. Although the screen is divided into 256x2'66 sections and the counter 2 and adder 6 are 8 bits, they may be changed depending on the screen division. The operation of the 75 was explained assuming that the data is white, but it can also be handled in black.

このように本発明によれば、TV画面の1画面走査時間
で投影演算の結果が計算機の主言己憶手段に格納され、
簡単なノ飄−ドウェアで従゛来より高速で処理可能とな
る効果を奏する。
According to the present invention, the results of the projection calculation are stored in the main storage means of the computer within the scanning time of one screen of the TV screen,
The effect is that processing can be performed at a higher speed than before with simple hardware.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は投影演算例を示す説明図、第2図は従来の処理
の一例を示す説、明図、第3図は本発明の一実施例によ
る投影演算装置の全体構成図、第4図は動作説明の模擬
図、第6図は水平軸への投影動作のタイミング図である
。 1・・・・・・ADffi換器、2・・・・・・カウン
ター、3・・・・・・DMA転送制御手段、4・・・・
・・計算機主=己憶手段、6・・・・・・加算器、6・
・・・・・一時記憶手段7・・・・・・全体動作制御、
8・・・・・・直並列変換バッファメモリ。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第2
図 第3図 j
FIG. 1 is an explanatory diagram showing an example of projection calculation, FIG. 2 is an explanatory diagram showing an example of conventional processing, FIG. 3 is an overall configuration diagram of a projection calculation device according to an embodiment of the present invention, and FIG. 4 is a mock diagram for explaining the operation, and FIG. 6 is a timing diagram of the projection operation on the horizontal axis. 1... ADffi converter, 2... Counter, 3... DMA transfer control means, 4...
... Computer main = self-memory means, 6 ... Adder, 6.
... Temporary storage means 7 ... Overall operation control,
8... Serial/parallel conversion buffer memory. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3j

Claims (1)

【特許請求の範囲】[Claims] ビデオ信号を2値化するAD変換器と、2値化ビデオ信
号の1水平走査のデータをカウントするカウンタと、画
面縦方向の累積データを記憶する一時記憶手段と、この
一時記憶手段よりの読出しデータと現ビデオ信号を加え
る加算器と、前記カウンタ及び一時記憶手段の内容を主
記憶手段へ転送するDMA転送制御とで構成された投影
演算装置。
An AD converter that binarizes the video signal, a counter that counts the data of one horizontal scan of the binarized video signal, a temporary storage unit that stores cumulative data in the vertical direction of the screen, and reading from the temporary storage unit. A projection calculation device comprising an adder that adds data and a current video signal, and a DMA transfer control that transfers the contents of the counter and temporary storage means to main storage means.
JP56162431A 1981-10-12 1981-10-12 Projecting operation device Pending JPS5862766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56162431A JPS5862766A (en) 1981-10-12 1981-10-12 Projecting operation device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162431A JPS5862766A (en) 1981-10-12 1981-10-12 Projecting operation device

Publications (1)

Publication Number Publication Date
JPS5862766A true JPS5862766A (en) 1983-04-14

Family

ID=15754473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56162431A Pending JPS5862766A (en) 1981-10-12 1981-10-12 Projecting operation device

Country Status (1)

Country Link
JP (1) JPS5862766A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154654A (en) * 1979-05-21 1980-12-02 Hitachi Ltd Pattern inspection system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154654A (en) * 1979-05-21 1980-12-02 Hitachi Ltd Pattern inspection system

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