JPS5860819A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction by providing a circuit which inhibits the output of a multiplied signal or a circuit means of fixing the output to a specified value when an input signal frequency exceeds a prescribed frequency range wherein a circuit never malfunction. CONSTITUTION:A 1/n frequency dividing circuit 1 and a frequency divider 2 measure a period which is 1/n as long as one period of an input signal fin. The measured value is latched by a latch circuit 3. The 2nd frequency divider 4, on the other hand, divides the frquency of a basic signal CK. The value of the latch circuit 3 is compared with the value of the frequency divider 4 by a comparing circuit 5. A reset signal R1 for the frequency divider 2 and a latch signal L1 for the latch circuit 3 are generated by a control circuit 13. Then, an overflow detecting latch circuit 16 detects an overflow state of the frequency divider 2. A latch circuit 19 for inhibition signal output outputs a signal for inhibiting a multiplication output signal f0 when the frequency divider 2 is in an overflow state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplier circuit that obtains a predetermined multiplied output even for input signals outside a predetermined frequency range.

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 1 has been considered as a multiplier circuit that multiplies an input signal frequency with high precision and has good responsiveness. This circuit is for multiplying the frequency of the input signal f1 by n.
of! It is measured by converting the period of 1/n of the cycle into the basic signal CK.

Latch this. Basic signal C during the next cycle
K is primary turbid, and this chest output is compared with the above-mentioned two-dimensional value, and if they match, one pulse is output, and a period of 17n of one cycle is measured during this one cycle, This is repeated, and the 17f1 frequency dividing circuit I and the frequency divider 2 measure 1/n of one cycle of the input signal f, and the sub circuit 3 uses this measured value as 2. Then, another frequency divider 4 divides the basic signal CK, and a comparator circuit 5 compares the value of the latch circuit S and the value of the frequency divider a4. In this circuit, the pressure control circuit 1s is composed of three 1-pit shift registers 6 to 8, two inputs 9 and 10, and two NOR circuits 11 and 11.
The reset signal of the frequency division ft2 @R1 and 2. A latch signal L1 for the child circuit S is generated. First, by passing the reset signal R1 through the OR circuit 14, or by delaying the multiplied signal 7e by the 1-bit shift register 15 and passing it through the OR circuit #6J4, the reset signal R3 of the other branching unit 4 is generated. is making.

In the multiplier circuit as described above, when the input signal 'In is low, that is, when the frequency of the input signal 'it> is low and the divider 2 has an overflow of 74, a total of 11
111 value will no longer be accurate. That is, now the measured value of the divider 2 is Nl, the measured value of the frequency divider 4 is Nh, the incoming signal frequency is 'In', the period of the input signal is 'In', the % multiplier is n
1 reference signal is CJ[, measurement fig of frequency divider 2
'R1 is expressed by the following formula.

? :, for example, multiplier n=4, reference signal CK"
10 kHz, frequency divider 2 is composed of a 10-stage d-inary counter, and the measured value Nl = 1024 (Nl max), the period T of the input signal is given by the above equation (1), and from this input The frequency of the signal is f. In this way, when the frequency f1 of the input signal becomes 0.41 nm or less, the total 1ij tl N 1 of the frequency divider 2 becomes @0 again.
“Go back and continue cutting.

Figure 2 shows the measured value N1 and the period of the input signal “In”.
It shows the relationship between As long as the input frequency 'In is within the predetermined frequency fliB that does not cause circuit malfunction,
Measurement ri N s is m between @1024” and ``0''
b, but if the input frequency f is higher than the predetermined frequency range (if the period τ is short) or low (if the period Tin is long), the measurement fill N * is
It repeats between a value of 1024' or less and 10'''. Therefore, as shown in the third factor, the input/output characteristics of the multiplier circuit are as follows: Also, the multiplication output I・shows a high value, and the input signal /, n
The characteristics of the output signal f· with respect to K are very unfavorable.

Conversely, if the frequency of the input signal 'in is high, i.e. 2
．． If the value to be tuned is less than a certain value or 10'', there is a drawback that sufficient multiplication characteristics cannot be obtained.For example, if the multiplier number n=Ws, the 1711 frequency dividing circuit J
Measured value of input cycle measured by network device 2 Nx = 256
In the case of 2. in the latch circuit 3. The value N1 to be checked is Nx/n
=256/16=16, so every time the frequency divider 2 counts "16" from the basic signal CK, a multiplied output f.

That is, since one cycle is '256', it is output every '16' count (one cycle 16 [!!I), so it is multiplied by 16. Now, if the measured value of the input period measured by the 1/n frequency dividing circuit 1 and the frequency divider 1 is Nx = 255, then the value Nl to be obtained is N = 255/16 = 15. .93
= 15, a multiplied output f. is obtained every time the basic signal CK is counted by 15 by the frequency divider. What is this?

Since one period is 1256'', each count of 15 means -256/15=17.06, which means that the signal is multiplied by 17. tb, the input frequency f11m is the maximum frequency fw
If ax and sh are also high, the multiplication force f will change rapidly, as shown in the input/output characteristics diagram in FIG. 4, and the input/output characteristics will not be normal.

As mentioned above, in conventional nine-fold multiplier circuits, if the input signal frequency exceeds a certain range, the circuit malfunctions, the multiplied output signal is amplified to an inaccurate value, and the input/output characteristics become very poor. There were drawbacks.

The present invention has been made to solve the above-mentioned drawbacks.
By providing a circuit that prohibits the output of the multiplied signal or a circuit means that fixes the multiplied output to a constant value when the input signal frequency exceeds a predetermined frequency range in which the circuit does not malfunction, The purpose is to provide a reliable multiplier circuit that has input/output characteristics that do not cause any practical problems even for low frequency or high frequency input signals, and that can prevent circuit malfunctions. Refer to Part 1 of the present invention! An example will be explained.

In the multiplier circuit shown in FIG. 5, the same reference numerals as Fi are used for the same parts as in the above-mentioned ja1 diagram, and the explanation thereof will be omitted.

In the figure, reference numbers J to 1& are the same as in FIG. This circuit connects the top pit output of frequency divider 2 through input 4-11.
An inverted reset signal RESET is received at the middle terminal CP and passed through the input terminal 18, and the reset signal R of the control circuit 13 is reset.
2. Receive D from the data input terminal and output from the output terminal Q4.
This is a 1-bit shift register that sends the output signal. Further, 111 is a latch circuit for outputting a rounding prohibition signal which obtains a signal for inhibiting the multiplied output signal f when the frequency divider 2 is over-off o-1. An inverted reset signal RESET is received through the inverter J8, which receives L1 at the terminal cp.
The above is reset through the inverter JO,
Child circuit! This is a 1-bit, 7-ft register which receives the output Q4 of 6 at the data input terminal and outputs the inhibit signal 11 from the output terminal Qm. The output Q4 of the latch circuit 16 via the upper 8 pins/pins 20 and the TE signal L1 are ANDed by an AND circuit 21, and this AND output is converted into 2. To child circuit 82. It is supplied as a chill pulse.

Furthermore, the prohibition signal from the latch circuit 19! , 1, the output from the comparator circuit 5 is darted by the AND circuit 22 to control the sending of the multiplied output signal fo. Further, when the value of the contents of 2 and 2 in the child circuit S becomes small to some extent, it is fixed to a constant value.

-2, CH value fixing circuit, this fixing circuit 23 is shown as an AND circuit 24 which takes the AND of a predetermined high-order bit output,
An OR circuit 2 which takes an OR between the output of this AND circuit z4 and the pit output other than the predetermined high-order digits of the child circuit 3.
5 to 27. Further, 111 is an inverter that inverts the basic signal CK.The operation of the nine-multiplying circuit configured as described above is based on the above-mentioned rule.The circuit multiplies the frequency of the input signal 'In by n times. The period of 1/n of one cycle of in is the basic signal CK.
Then, it is measured by the frequency divider 2, which is then measured by the frequency divider 3. and then send the basic signal C to another branching unit 4.
KO frequency division is performed, and the frequency division output of this divider 4 and the above 2,
Te circuit 3-2. The comparison circuit 5 compares the specific forces of each other, and if the two match as a result of the comparison, one pulse is output. By repeating this operation, the input signal ftnt-
A multiplied output signal io multiplied by n is obtained.

In the above circuit, if the frequency of the input signal is low, the frequency divider 2 will overflow as described above, so the overflow detection circuit is used.

It is detected by the circuit 16. Furthermore, this circuit J6
The circuit 19 uses the detection output of 2 to output a prohibition signal. The inhibit signal 11 is obtained by inputting the inhibit signal It to the AND circuit 2.
In addition to J, the multiplied output f from the comparator circuit 5 is prohibited.

As shown in the input/output characteristic diagram in Figure 6, if the input frequency n is lower than the minimum frequency 'in- of the input signal f to prevent the circuit from malfunctioning, the multiplied output foB output Then it becomes zero. Conversely, the maximum frequency finv at which the circuit does not malfunction
When the input frequency becomes high for both nax and si, 2. The content is below a certain value or '''0#
On the other hand, as a desirable characteristic in practical use when a sufficient multiplication characteristic cannot be obtained, it is preferable to fix the multiplication output fo when the input signal f becomes high to a certain extent. Therefore, in the case of 2. The value fixing circuit 23 fixes the contents of the circuit S to a predetermined value and sends it to the comparator circuit 5, and the fixed value produces a multiplied output f as shown in the input/output characteristic diagram of FIG. fixed at a constant value. In this way, even if the input signal frequency is out of the frequency range in which malfunction does not occur, the input/output characteristics can have practically no problem.

FIG. 7 shows a multiplier circuit which is another embodiment of the present invention. In this circuit, the AND circuit 22 shown in FIG. 5 mentioned above is removed and a prohibition signal is output.

Inhibition signal I of Te circuit 19! 2. The signal is supplied to the C and G terminals S of the T circuit 3. By doing this, when the input frequency becomes lower than the minimum frequency fi□, the inhibit signal II causes the output of the frequency divider 2 to be output to the constant output of the frequency divider 2. 2) because it is in an overflow state. By this constant output, the multiplied output J
's. Therefore, as shown in the input/output characteristics of FIG. 8, the minimum frequency 11f1. - multiplied output f for a low input signal 'In below.

is constant. For fastening with high frequency, 2. Since the t value fixing circuit 23 fixes the υtput output to a constant value, the output signal fe remains constant for the input signal 'in having a maximum frequency f1nmax or higher, as shown in the characteristics of FIG. ing. This circuit also has the same effect as described above. If the present multiplier circuit is applied to, for example, a device for detecting the rotation speed of a vehicle engine, the rotation speed can be detected with high accuracy and the device can have good responsiveness.

As explained above, according to the present invention, when the input signal frequency exceeds a predetermined frequency range in which the circuit does not malfunction, a circuit that prohibits the output of the multiplied signal or a circuit means that fixes the multiplied output to a constant value is provided. Therefore, it is possible to provide a multiplier circuit that has input/output characteristics that do not cause any practical problems even for input signals of low or high frequencies outside the predetermined frequency range, and can prevent malfunction of the circuit.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional multiplier circuit, FIGS. 2 to 4 are diagrams for explaining the circuit operation of FIG. 1, and FIG. 5 is a configuration diagram of a multiplier circuit according to an embodiment of the present invention. , FIG. 6 is an input/output characteristic diagram of the circuit in FIG. 5, FIG. 7 is a block diagram of a multiplier circuit according to another embodiment of the present invention, and FIG. 8 is an input/output characteristic diagram of the circuit in FIG. be. 1...1/n frequency divider circuit, 2.4...frequency divider, 3
···cormorant. Child circuit, 5... Comparison circuit, 13... flllJ control circuit, 16... O/4 flow detection latch circuit, 19
...For prohibition signal output 2. Child circuit, 22...AND circuit, 23...2. chi value fixing circuit, CK...basic signal, f...input signal, f6...multiplying blade signal, Xt
...Kame n Prohibition signal.

Claims (4)

[Claims] (1) A 1/n frequency divider that divides the basic signal into 1/n, a first frequency divider that divides the output of this 1/n frequency divider into a predetermined value, and this first frequency divider 2. a latch circuit that receives the input signal and the basic signal and generates a reset signal for resetting the first frequency divider and a signal for the latch circuit; It is equipped with a second frequency divider that divides the frequency of the basic signal to a predetermined value, and a comparison circuit that compares the output of the second frequency divider and the output of the child circuit and outputs a multiplied output if they match. In a multiplier circuit that triples the input signal within a predetermined frequency range to obtain a ninefold output, means for inhibiting the multiplied output or setting it to a constant value when the target input signal is lower than the predetermined frequency range; A fixing means for fixing the multiplied output to a constant value when the input signal is higher than a predetermined frequency range is provided, and the multiplied output is controlled even for input signals outside the predetermined frequency range. Multiplier circuit to (2) The prohibition means includes an overflow detection latch circuit that detects the 0/4 flow of the first frequency divider and outputs a prohibition signal in response to the output of the child circuit used for this detection. Get the inhibit signal output for use. A patent characterized in that the device has a child circuit and an address that outputs the multiplied output by a prohibition signal from the latch circuit, and the prohibition signal prohibits sending out the multiplied output. A multiplier circuit according to claim 1. (3) The setting means detects an overflow of the first frequency divider, detects an overflow detection sub-circuit, and generates an inhibit signal upon receiving the output of the sub-circuit. Get the inhibit signal output for use. This output is used to transfer the contents of the #g1 frequency divider to the secondary circuit by an inhibit signal from the secondary circuit.
．． The multiplier circuit according to claim tA1, characterized in that the multiplier circuit is configured such that the multiplier output is set to a constant value. (4) The fixing means includes an AND circuit that ANDs a predetermined high-order bit output of the latch circuit, and a 9-OR between the output of this AND circuit and the low-order bit output of the child circuit. The above 2. The multiplication device according to claim 111, characterized in that when the content of the child circuit becomes smaller than a predetermined value, the output of the OR circuit is sent to the comparison circuit to fix the multiplication output tube constant value. circuit.