JPS586076A - Reducing method for switching loss of high frequency inverter - Google Patents

Abstract

PURPOSE:To reduce a switching loss of a high frequency inverter by selecting a rectangular switching frequency fr to the range of fs/fr=1.1-1.4 to a resonance frequency fs and displacing the period from the current stopping time of a switching element to the voltage generating time by the prescribed time. CONSTITUTION:A series resonance circuit of a resonance frequency Fs having a capacitor 3 and an inductance 4 is formed, a rectangular switching frequency fr to be applied to semiconductor switching elements 1, 2 is set to the range of fs/fr=1.1-1.4, and the period from the current stopping time to the voltage generating time of the elements 1, 2 is displaced by the prescribed time. In this manner, the charging current, discharging current and load current flowing through the capacitor 3 become I1, I2, IL, can be maintained at the prescribed value in the range of fs/fr=(tc+ts)/tc=1.1-1.4, and the switching loss at the switching closing time can be reduced to zero.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to low switching loss control in a high frequency inverter, that is, a method for reducing switching loss when converting direct current to high frequency using semiconductor elements.

For example, a high frequency power supply for high frequency induction heating requires 50 KH.
2 requires an output of 4KW to 150KW.

In modern times, it is customary to convert a DC power source into high-frequency high power and supply it to a load using a series inverter circuit and a semiconductor (thyristor, etc.) switching method. In conversion by switching, it is important to reduce the switching loss that occurs.In the present invention, we use a matching circuit between the load and the power supply ((inductance L) and eight capacitors C, and when the load current passes the zero point, The current flow time t for each switching element is to be set to reduce switching loss and improve circuit efficiency, and to set up an automatic tracking mechanism for load fluctuations.
. The feature is that power can be efficiently supplied to the load by always keeping the ratio of the pause time ts and the rest time ts constant.

Since the conventional switching type series inverter is well known, its explanation will be omitted, but Figures 1 and 2 are voltage and current waveform diagrams applied to the switching elements. In the conventional circuit, the current and voltage waveforms applied to the main switching elements are as shown in Figure 2 (B), and the disadvantage is that switching losses occur at two points a and b where the voltage waveform E and the current waveform overlap. be. In contrast, in the present invention, the current stop time is generated at point b when the switch is turned on, as in Figure 2, and the switching loss during this period is made zero to stabilize the switching operation. The present invention will be explained below with reference to examples.

Figure 1 is a circuit diagram of a high frequency inverter implementing the present invention (
A) and a waveform diagram of each part (B). In the figure, 15 is a DC power supply, 1 and 2 are switching semiconductor elements, 6 is a capacitor 0.4 is an inductance L, and 5 and 4 form a series resonant circuit (the series resonant frequency is f8). 5 is a capacitor, 6 is an inductance, 7 is a load resistance, 5, 6
, 7jy to form a matching circuit, the resonance frequency of which is set to 1. 8 is a high frequency bypass capacitor/su, 9, 10
is a damper diode, and 11.12 is a current detection section.

Note that d, , d2 are human power for driving the switching semiconductor elements 1 and 2, and the details thereof will be explained with reference to FIG.

E. In Figure 1, with the DC power supply 13 connected, the driving force d1. When the switching semiconductor elements 1 and 2 are operated alternately by d2 (pulse), the series capacitor 5 performs charging and discharging operations, and as a result, the series coil 4,
An alternating current flows through the matching circuits 5, 6.7. To explain in more detail, when element 1 is turned on by drive pulse d, series capacitor 3 is charged and 5, 4, 5, 6, 7
．． Current flows through the closed circuit B. In Figure 1 (B), mark 1 shows the waveform of this charging current, and mark 1 shows the waveform of this charging current.
When the potential becomes the same as the potential of the DC power supply 15, it stops.

Next, when the element 2 is turned on by the drive pulse d2, the charge stored in the capacitor 3 is discharged, and when the potential of the capacitor 3 becomes zero, the discharge current stops.

Said t. and t, 4 as shown in the figure. The construction of spear 1 (B).

shows the waveform of this discharge current. Spear 1 (B)
It is a composite of the waveforms of the load current, , and .In order to keep the distortion of this waveform small, it is necessary to combine the series resonant frequency f of the series circuit with 5 and 4 and the matching circuit with 5,6°7. What is necessary is to keep the ratio of the resonant frequency/r to a constant value of about 'e/'r-1, 1 to 1.5.

Figure 6 shows the pulses d, which drive the switching semiconductor elements 1 and 2, (LL generation circuit side diagram (A) and waveform example diagrams of each part (
B), drive pulse d4. The method of generating d2 will be explained next. In addition, 14 in Figure 5 (A)
is an integrator, 15 is a comparator, 16 is a set voltage (supply source),
17 is a V/F (voltage→frequency) converter, 18 is a pulse shaping circuit, and 19.20 is a drive circuit.

First, the detected current ■ of the current detection unit 11 (Figure 1).

(E) From (A) in Figure 6 (B), a rectangular wave (B) (designated as p) is created following 11 using the forming circuit (not shown) in 1-1.

In addition, a rectangular wave ((1) (represented as rp)) is transmitted from the detection current circuit '2 of the current detection unit 12 (to the inverted wave in Figure 5 (B)) to the forming circuit of the spear 2 following 12 ( (not shown).

The composite of ■, p, ■, and rp becomes the waveform shown in Figure 3 (to), which becomes the input G of the circuit in Figure 3.3 (Al). In Figure 5 (A), the input (to) A value integrated by an integrator 14 is compared with a set voltage 16 in a comparator circuit 15.

At this time, the output Δe of the comparison circuit becomes zero when f8/fr is a determined value, for example, 15. Δe 'i V/F
When converted into a frequency in the converter 17 and inputted to the pulse shaping circuit 1B, a rectangular wave pulse corresponding to the frequency is obtained, and this is passed through the drive circuit 19.20i to the gate of the switching semiconductor 1.2 as a drive pulse d1. d
Send as 2. Through these operations, automatic tracking is performed so that the switching operations of the switching semiconductors 1 and 2 always have a constant value, 1.5 in this case.

Now, in the present invention, when the above driving pulse is applied, if 78' is adjusted to a constant value within a range of approximately 1.1 to 1.4 times higher than /r, /8 becomes The series resonant frequency of the 3 and 4 series circuits in Figure 1, /r, is the resonant frequency of the load matching circuit, that is, the output frequency of the in-coupler, and its period is clearly t. Since it corresponds to +t8, (
to t8)/lc to a constant value between 1.1 and 1.4,
Therefore, te"cf- is kept constant, and by shifting the voltage generation timing by a certain period of time from the correct timing of one current stop during switching operation, the switching loss when the switching is closed is zeroed, and the switching operation is stabilized and the circuit efficiency is increased. At the same time, the purpose of reducing the waveform distortion of the load current is achieved and generated in the circuit, and there is also the effect of reducing the surge voltage.

The present invention has been applied to, for example, a high frequency induction heating oscillator with an output of 4 KW to 150 KW and a frequency of 50 KHz, and good results have been obtained.

[Brief explanation of the drawing]

Figure 1-1 is a waveform diagram (B) of the circuit of the high frequency inverter according to the present invention, and Figure 5 is a generation circuit diagram of the drive pulse for the switching element in Figure t1. 1.2...Semiconductor element for switching, 5,5.
...Capacitor, 4,6...Inductance, 7...
・Load resistance, 8...Capacitor, 9,10・
...damper diode, 11.12... current detection section, 13... DC power supply, 14... integrator,
15... Comparator, 16. ...Set voltage, 1
7...V/'F converter, 1B...pulse shaping circuit, 19.20...drive circuit. Patent applicant Kokusai Denki Co., Ltd. Agent Otsuka 1 external person Figure 1 + A) 2nd Figure 3! 9 +p

Claims (1)

[Claims] One or more pairs of semiconductor switching elements connected in series to a DC power supply, and a capacitor C and an inductance L between the connection point of the switching elements and the connection point of two series capacitors in parallel to the DC power supply. In a high frequency inverter equipped with a series resonant circuit having a resonant frequency f8, and a load coupled to the inductance L and serving as a matching circuit having a resonant frequency /r, a rectangular wave switching frequency fr'fr applied to a semiconductor switching element,
///Switching loss of a high frequency inverter characterized by reducing switching loss by selecting an appropriate value between r-1,1 and 1.4 and shifting the time from the time when the current in the switching element stops until the time when the voltage is generated by a certain period of time to reduce the switching loss. Reduction method.