JPS5859680A - Picture signal processing circuit - Google Patents

Abstract

PURPOSE:To facilitate reduction and expansion of a projected picture, by cutting the control loop of an oscillator forcibly by a mode signal, where subscreen information is projected on all of the surface of a display device, to set it to the free running oscillation and self-resetting a related counter. CONSTITUTION:An oscillator 2802 is controlled by a horizontal synchronizing signal HSSYNC and a horizontal fly-back signal and oscillates a clock signal having an integer-time frequency of the horizontal frequency, and the output is counted in 1 horizontal period (H) by a counter 2804. The output of the counter 2804 is inputted to a counter 2809 and is counted 1 vertical period by the counter 2809. A vertical synchronizing signal VSSYNC is detected by a vertical synchronizing signal detecting circuit 2811 and is sent to a phase comparing circuit 2812 and is compared with a reference phase. The control loop of the oscillator 2802 is cut forcibly by the mode signal to set the oscillator 2802 to the free running oscillation, and the counter 2809 is self-reset.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing circuit that performs image signal processing on a plurality of input video signals, and is particularly suitable for C1 that performs multi-functions such as enlarging and reducing a projected image. The present invention relates to an image signal processing circuit.

In general, typical examples of special processing for image signals include processing to enlarge or reduce the input image signal to an arbitrary size and display it, rotation of the projected image, and static processing. shows an example of image processing for displaying the projected image screen (-main screen 1 and the sub-screen 2 whose image data has been reduced by data compression and is displayed in synchronization with the main screen. In this case, the screen is displayed in sync with the main screen. In order to display the sub-screen, processing is required to reduce the image data density of the input video signal corresponding to the sub-screen.Furthermore, in order to enlarge and display the sub-screen 2, data interpolation processing is required.

FIG. 2 shows a conventional image signal processing circuit that generates a signal obtained by compressing input video signal data for a sub-screen. Second
Figure (=, sampling frequency 47so (/so
The sample plane digital signal 3 at a color subcarrier frequency of 3.58 MHz is guided to an input switching circuit 4 (= 3.58 MHz).

This input switching circuit 4 sends sub-screen digital signals for each field via signal paths 5 and 6 to one field memo! J
718. And these field memories 7
．． The data of 8 is supplied to the data processing circuit 11 via the signal path 9, 1, and the sub-screen display (= arithmetic processing of the necessary data is performed. A switching signal 12 is generated to switch each field, and when one field memory 7 is in the write mode, the other one field memory 8 is controlled to be in the read mode.Thereby, the data for each field is transferred to the one field memory 7. This data is used to obtain data 13 for sub-screen display.

In this way, an image signal processing circuit that uses a plurality of field memories is capable of storing two corresponding memories and can perform data correlation calculations between fields. When the address circuit has a plurality of circuit configurations (one arithmetic circuit becomes complicated), there is also a disadvantage that only a single correlation operation can be performed.

Figure 3 addresses the problem of having a plurality of 1-field memories in the circuit shown in Figure 2 (1).The analog video signal for displaying the sub-screen is the luminance signal Y2 color difference RY, B -Y, and the signal 14 of s is guided to the A/D converter 16 via the multiplexer 15. Here, the output of the multiplexer 15 is sent to the ψ converter 16 at approximately 2.4 MI (at the sampling frequency of Z). When sampled, a signal 17 quantized with 2 or 5 bits is obtained. From this signal 17, a signal corresponding to the reduction ratio (1) of the sub-picture heat is sampled and extracted by an arithmetic circuit 18 (2-5 bits). In this way, only the data necessary for the reduced display is supplied to the field memory 20 (-) via the signal path 19.
- and is read out at a predetermined timing, guided to a buffer circuit 22 via a signal path 21, and stored in memory. The data stored in this buffer circuit 22 is read out via the signal path 23 at a predetermined synchronized timing, and is converted into an analog signal by the D/A converter 24 (=displayed on the sub-screen as required). In this way, in the conventional image signal processing circuit shown in FIG. Therefore, the reduction ratio is restricted by the calculation function of the sampling calculation circuit 18. Therefore, the reduction ratio of the reduced screen that can be displayed on the sub screen is determined by the sampling calculation circuit, and the reduction ratio can be set freely. In addition, the circuit shown in FIG. 3 cannot function to enlarge and display the image on the sub-screen.

Further, a circuit similar to the image signal processing circuit shown in FIG. 3 is described in [IIJJ Vol CE-25+ Feb, '79
Michi.

Masuda etal “Fully Digital”
lized Picture 1nPicture T
Although it is written as "e1evision System" (=), it still has the above-mentioned problems.

The present invention has been made in view of the above points (--), and the present invention has been made in view of the above points (--).
It is an object of the present invention to provide an image signal processing circuit that can perform multi-mode image data processing such as image reduction, enlargement, and static image data processing.

(Summary of the Invention) The present invention samples an input video signal at predetermined horizontal and vertical cycles, performs a first correlation calculation on these water divisions, and stores the results in a field memory (
- One of the points is to control the size of the displayed image by performing a second correlation calculation that controls the data written and read from the field memory. That is,
By selectively controlling the combination of the first correlation calculation and the second correlation calculation, the size of the displayed image can be controlled, and the image can be reduced or enlarged using a small-capacity field memory.

Further, the present invention (second aspect) relates to video signals.

The above correlation calculation is performed between adjacent picture elements to enhance the correlation of data to be complemented by the correlation calculation (Embodiments of the Invention) Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

The image signal processing circuit according to the present invention can compress and expand sampled data by performing a first correlation calculation (=second correlation calculation) on an input image signal. This is one of its features.In this way, performing the correlation calculation for two input image signals multiple times via the field memory is possible by controlling the data compression ratio or data expansion ratio. This means that it is possible to reduce and enlarge the image.Furthermore, if you stop writing to the field memory and continue reading it, a still image is obtained, but in this case, the address access means for the field memory By using a novel circuit configuration, it is possible to obtain static images across multiple modes.

That is, the present invention can perform multi-mode image display by efficiently performing data rejection, interpolation, correlation calculation, and access to field memory for data sampled from an input video signal.

FIG. 4 shows the display positional relationship of images processed and displayed by the image signal processing circuit in this embodiment. Now, it is assumed that there are two types of signals to be displayed, a video signal as a main signal and a video signal as a sub signal. In the same figure, the main screen is normally a display device CRT.
A total of 111s+2 is displayed, and a sub-screen is inserted and displayed. This inserted sub-screen is usually P in the same figure,
The display is performed at the positions P4 to P4, and the display is performed at a size ranging from approximately 6-inch screen to full screen size. Further, the display position of the sub-screen may be set to a position other than the above (such as the center of one screen), and may be displayed in a reduced or enlarged manner.

Note that, as will be described later, the display image of the front thread image can be stopped on either the main screen or the sub-screen by stopping the writing of image data to the field memo and continuing reading it.

Such reduction and enlargement display of the input video signal is performed by first and second correlation calculations. In this case,
Performing the first correlation operation on the input side of the field memory and performing the second correlation operation on the output side has the effect of increasing the degree of freedom in reduction or expansion. In other words, the size of the display screen is determined by the calculation contents of the first correlation calculation and the calculation contents of the second correlation calculation, and the size of the display screen is controlled by controlling the calculation contents of both. The calculation means for the first correlation calculation and the second correlation calculation will be explained below.The first correlation calculation and the second correlation calculation are performed for both the luminance signal and the two color separation codes.

FIG. 5 is a circuit diagram showing a first luminance signal calculation circuit that performs the first correlation calculation performed on the luminance signal on the input side of the field memory. The first correlation calculation for the luminance signal performed on the input side of the field memory 134 is performed in the horizontal and vertical directions. This also applies to the second correlation calculation described later, but the correlation calculation circuit described in this embodiment is a linear circuit with a gain of 1, rather than being viewed as an instantaneous data companding circuit.
It is preferable to consider it as a representative value generation circuit. After interpolation of representative values by first correlation calculation and rejection of data, fifth
Explain using diagrams. In the figure, a portion surrounded by a broken line is a first luminance signal calculation circuit 1300 that performs a first correlation calculation on the luminance signal. This first luminance signal calculation circuit 13
00 is the analog luminance signal sampling pulse φ.

, (According to 1 ~ Perform Φ conversion digit ~ Φ converter 1000
The input is a signal quantized by . This sampling pulse is typically 3/so + 47so (/so
= 3.58 MIIz), but in this embodiment, 4407H (/u = 15.75 kHz) is used to simplify the configuration of control system circuits such as line memory and field memory.

The output of the ψ converter 1000 is transmitted through the latch I ["1 path 3701 and the latch circuit 371 to generate a 1/8 weight force "
After the addition, the signal is supplied to the adder ΣYi1. Also, above ~
The converter 1060 converts the data into one horizontal period (11
1), the first 111 memory 260 performs the delay operation, and the second
1. , l(- After passing through the memory 2B1, the latch circuit 380, and the latch circuit 381, the adder Σ
It is supplied to Yil. And the above IH memory 26
The output of 0 is % through the latch circuits 374, 376, 378.
is weighted by 4 and supplied to the adder ΣYi2, and is also weighted by 1/8 and supplied to the adder ΣYil. In addition, the output of the latch circuit 374 is weighted by 1/8,
and is supplied to the adder ΣYit with a weight of %. Further, the output of the latch circuit 376 is added to the adder ΣYi1. with a weight of %. ΣYi2,
and is supplied to the three-state circuit 405.

Furthermore, three-state circuits 406 and 407 take the outputs of adders ΣYis and ΣYi2 as their inputs, respectively. The outputs (2) of the three-state circuits 405, 406, and 407 provide the first correlation calculation result, and this result is written into the field memory 134.

Here, the first correlation calculation performed on the input side of the field memory will be described. The first correlation calculation is performed based on the data sampled by the A/D controller IS-1000, but which data is used to perform the correlation calculation depends on whether the image is enlarged or reduced. It depends on what ratio you use.

That is, in the correlation performance, the correlation calculation formula corresponds to each image processing mode, and the sampling data to be calculated is determined. The correlation calculation according to this mode (1) is specified by mode signals m3+rn, s mI, which are supplied to the high-restate circuits 405, 406 and 407.
-+-m2, +n,, +rn.

It is determined by ζ2. The first correlation calculation is performed according to the left mode determined in this way,
Since this correlation calculation is essentially a representative value setting, in the calculation process (second step), sampling data at different sampling times are used as calculation targets.

In FIG. 5, latch circuits 370.374.380 function as mere latch circuits for latching sampling data, but latch circuits 371.382.376.37
8 functions as a delay circuit that delays data by a time τ in the horizontal scanning direction. In addition, the first j II memory 26
0, the second 111 memory 261 has a period of one line 1//
It operates as a delay circuit that delays data by u7'ff. In Figure 5, the signal delayed by two lines with respect to the current line is T.
The signal delayed by 11 lines is indicated by M, and the current line signal B. In the horizontal direction, the signal is +1 relative to the current signal, and the signal delayed by time τ relative to the current signal (2 is 0, and the signal delayed by τ relative to the current signal ≦ 2. A subscript of -1 is attached to the signal.The first correlation calculation performed for each mode based on the signal defined in this way will be described next.The reduction coefficient by the first correlation calculation will be described below. It is assumed that the horizontal direction is Hdi and the vertical direction is Vdi.

[mo mode] First, there is mode m in which the main and sub-screens display moving images based on normal analog signals, and the sub-screens display images that have been reduced by digital processing. Let's talk about.

In this mode, Hd+ == %, Vd
I=l, and the reduction coefficient 11d i is the wing M. 10% (M-
, 10M+, )... It is obtained by the correlation calculation (1). That is, in this reduction mode, no reduction is performed in the vertical direction. In addition, in the horizontal direction, by controlling the latch circuit group and the first and second IH memories, only data corresponding to M is extracted as shown in FIG. The calculation of the formula is performed.By the calculation, the data M-1,
Each of M+1: 2! Without the weighting of 4, this data is obtained as interpolated data by adding a weight of % to the data itself. Note that the vertical reduction coefficient Vid =
1 corresponds to not discarding data 11 in the horizontal direction (in the two cases, data is discarded every time T, but in the vertical direction I/).

[mt mode] Next, try two modes in which the main screen is a moving image based on a normal analog signal, and the sub screen is a digitally processed zoom-up image whose size can be reduced. . In this m2 mode, ~Φconno(-ta(2) extracts the data M.
The output of 12 (1 is obtained. Then, this data is sent to field memo 17134 + varnish door without doing 1.

Therefore, in this mode, field memo IJ134σ)
The reduction factors on the input side are Hdi = 1, Vdi =
It becomes 1.

In the above two modes m6 and m2, 1 main picture 1
01 processes normal analog signals, but in the next mode (2), the main screen signal is switched to the sub screen and a digitally processed image signal is displayed.

[m, mode] In mode m, the main screen to be digitized is the data corresponding to the shaded area of all the signals on the display screen shown in FIG. In this case, the data corresponding to the shaded area on the display screen in FIG. 7 is set to M as in the m2 mode described above.

The signal is sampled as follows, extracted by adder ΣY12, and stored in field memory 134. Then, by this first correlation calculation and a second correlation calculation to be described later, data corresponding to the shaded area (2) in FIG. 7 is zoomed up and displayed on the entire screen. In this case, the data in the displayed part is not rejected, and the reduction coefficient is l1di-
1+Vd1=l. As will be described later, data interpolation is performed by a second correlation operation ( ) in order to zoom up the shaded area in FIG. 7 by a factor of 4.

[mr mode]

Next (2) mode mt is a mode in which the main screen that has been zoomed up in mode m Corresponding to MF mode, since the image signal is displayed in a reduced size, the first correlation calculation is performed to reject and reduce the data on the input side of the field memory.The data to be subjected to the first correlation calculation in this MF mode is , Figure 6 (b
) As shown in Converter 1000 to T, M,
Use data for 3 lines as &. A first correlation calculation is performed on these data to obtain a reduction coefficient Hdi=
1/8 is obtained, and the situation is shown in FIG. 6(b) (2). That is, T., M.

Based on five types of data corresponding to pigeon, M+, , Bo, C21/2 Mo+1/8 (To+Bo+M+1+
M-t) --(2) Data is reduced by discarding predetermined data among the data obtained by performing the correlation performance.

[m5 mode] Next, the main screen is based on digitally processed signals (mA mode in which a still image with the movement of the two images stopped is displayed on the entire screen; the size of the image displayed in this mode is as follows. is the same on the display screen as when displaying a normal analog signal.In this case, the reduction coefficient on the input side of the field memory 134 is set to Hdi=%Vdi ml.Such a reduction coefficient is used in the case of the above-mentioned mo mode. Therefore, the reduction calculation of the mode of ml is obtained by the first correlation calculation C2 according to the above equation (1) shown in FIG. 6(a).

(m, mode) The m3 mode is the above-mentioned ml mode, and is a mode in which a digitally reduced sub-screen is inserted into the static main screen.In this case, the sub-screen to be inserted is The reduction coefficients on the input side of the field memory 134 are set to Hd i-% and Vd1-i.This reduction operation is performed on the data shown in FIG.
It can be obtained by performing the same correlation calculation as the above-mentioned - mode of o10% (To+Bo+M+s+M-s).

The mode of correlation calculation on the input side of the field memory 134 according to this embodiment is as described above (2mg, m2゜m
, , m,', m,; , m, modes can be taken. Then, a first correlation calculation is performed by the first brightness signal calculation circuit 1300 shown in FIG. 5 corresponding to these modes (2).
If the correlation calculation is a data interpolation calculation, it functions equivalently as a bypass filter for the data of the ~Φ converter 1000. Further, when the phase-to-phase calculation is an calculation that discards data, the first luminance signal calculation circuit 1300 functions as a low-pass filter for the data of the 4-channel converter 1000. Note that switching of the first correlation calculation for each mode is performed by controlling the latch circuit group and the first and second IH memories in accordance with the type of mode signal supplied to the three-state circuit.

A first correlation calculation for the purpose of data interpolation or data rejection is performed on the luminance signal by the first luminance signal calculation circuit 1300 and stored in the field memory 134. The luminance signal data stored in the field memory is read out and subjected to correlation calculation processing by a second luminance signal calculation circuit, which will be described later. The second brightness signal calculation circuit, like the first brightness signal calculation circuit 1300, performs a second correlation calculation for data interpolation or data rejection on the read data of the field memory 134. This second correlation operation functions equivalently as a bypass filter or a low-pass filter for the data. Therefore, the output of the four-channel converter 1000 is the filtering effect of the first correlation operation and the second correlation function. To be subjected to a filtering effect by an operation (two. Like this (
2. The luminance signal data sampled and quantized by the converter 1000 is digitally processed by the first and second correlation calculations to obtain appropriate data according to the mode of reduction or enlargement of the projected image. .

Here, the second luminance signal calculation circuit that performs the second correlation calculation will be explained.

In FIG. 8, the broken line portion is the second luminance signal calculation circuit 1500.
shows. This second luminance signal calculation circuit 1500, like the first luminance signal calculation circuit 1300, in the vertical direction, correlates the current line signal B1 with a signal T delayed by 2 lines, and a signal M delayed by 1 line. Use as the operation target of the operation. In addition, the horizontal blade "t." (for one thing, when the data sampling period is τ (= current signal, current signal (2), three signals delayed by time τ and 2τ are subject to calculation in the horizontal direction. Here, , +1 for the current signal (2), and a signal delayed by time τ for the current signal (2) by 01 hours and a signal delayed by 2τ (= is given a -1 subscript.Due to the circuit configuration, the second luminance Since the mode of calculation carried out by the signal calculation circuit 1500 is more l/1 than that of the first luminance signal calculation circuit, the adder for adding the multiplied data has ΣYOI to Σyon and t
*The point where the number of circuits increases and the point where there are a large number of C-state circuits (switching and controlling the data of the bird adders ΣYol to Σ'Yoa, etc.) are defined as the first brightness. This is the main circuit difference from the signal calculation circuit. However, this difference is due to the fact that the second luminance signal calculation circuit has a large number of modes for the correlation calculation p.
, second lH memory 804>4.
o>Circuit configuration of the part that generates the calculation target data (with regard to 1, there is no fundamental difference between the two I, z. Also, the power It
The weighting coefficients for the data added by the input signals Σyot to Σyoa are shown in FIG.
02°804 is driven by the clock pulse of 4407H.The three-state circuits 840 and 842 are driven by the clock pulse of 4407H. The three-state circuit 8 is driven by the clock pulse of
40°842 is driven by a clock pulse of 2φos.

The second luminance signal calculation circuit 1500 performs a two-chain 2 correlation calculation based on data from the field memory 134 in which the correlation calculation results performed by the first brightness signal calculation circuit 1300 are stored. As a result, the reduction coefficient I(do, Vd
o is calculated. The reduction coefficients Ild i , I(do ) on the input/output side of the field memory 134 .

Once Vd i and Vdo are calculated, the screen size of the display screen is determined. The reduction coefficient by the second correlation calculation is performed in accordance with the mode of the first correlation calculation described above. Next, mode m on the input side of the field memory 134 described above. , m2. ml, m昌m,; , m
.

The output side mode for each mode will be explained, and the second correlation calculation in this case will be explained next.

(Mode for Mode 4) The mo mode is a mode that inserts a sub-screen that is digitally processed sub-screen signals for the main screen (2) that is displayed using normal analog signals.In this mode, the size of the sub-screen to be inserted is Depending on the screen size, three modes are set: m, which displays the sub-screen at a size of 116 screens; m, which displays 81% of the screen; and m, which displays the sub-screen on the entire screen.

mo, mode This mode is a mode in which a sub-screen is reduced to 1/16 screen and inserted into the main screen. Already on the input side, a reduction factor of 1 (d
Since i-% and Vd1==1 are determined, the reduction coefficients on the output side are set to lad o-% and Vdo-%, thereby reducing the display to 716 screens. In this case, the above reduction coefficient H
0-% is obtained by generating one interpolation data from two picture element data in the horizontal direction among the data read from the field memory 134. Similarly, the process obtained by generating interpolated data with one reduction factor is shown in FIG. 9(a). Note that the data to be subjected to the second correlation calculation to obtain this interpolated data are M-1, MO, M+
, , 4 pixel data of BO. For these four data, 3AMo10%B,) + 3A (M++ +
M-1)... Performing the calculation (3) (obtaining interpolated data of the adder Σyosi bimol mode from two).

Omo2 mode In the cono mode, the subscreen obtained by digitally processing the subscreen signal is inserted into the main screen as in the % screen (reduced by 2) and the above m mode.Reduction coefficient on the input side lid i, - station Vd1
=Hd is the reduction coefficient on the output side for l.

-1, Vdo -% and %(2) to obtain a reduced sub-screen.

The target data for the second correlation calculation is the three picture element data Mo, To, and Bo, as shown in FIG. 9(b).
The second correlation calculation at this time is % pigeon + % ('ro ten Bo
)...Indicated by (4).

omo3 mode The above two modes m. In 19mo2, a sub-screen was inserted into the main screen, but in this mode, the size of the sub-screen to be inserted is set to full-screen display. In other words, the sub-screen is displayed on the entire screen, and the reduction ratio of the sub-screen is 1. However, since the reduction coefficient on the input side is set to I (di = %, Vd1 = = 1), on the output side, in the horizontal direction, the reduction coefficient is H old =
It is necessary to perform an operation to make it 2. That is, on the input side, l
Since the pixel data density becomes 1 di-ht, the pixel data density becomes 2% (%), so it is necessary to interpolate the pixel data in the horizontal direction on the output side to make the resulting horizontal pixel data density 1.

In this way, a correlation calculation is performed in this mode to double the data density on the data read from the field memory 134 in this mode. This means that new data is generated from the data read from the field memory 134 in the horizontal direction. This shows how to generate new picture data represented by , doubling the pixel data density in the horizontal direction.As you can see from the figure, no interpolation of pixel data is performed in the vertical direction, so on the output side The reduction coefficient Vdo of is Vdo = l.Then, in order to double the picture data density in the horizontal direction mentioned above, the reduction coefficient on the output side is set to l1do = 2.The picture element data M.9M+1 is calculated. Obtained by calculating as an object.The calculation in this case is indicated by %(Mo+M++)・Mu・(5).Like this (2, in this mode,
The reduction coefficient on the output side is Hdo = 2, Vdo =
By setting it to 1, the sub-screen can be displayed on the entire display screen using data interpolated in the horizontal direction.

(Mode for mode m2) This mode m2 is a mode in which image data corresponding to the diagonally shaded portion shown in FIG. 7 of the sub-screen signal is reduced or enlarged and inserted and displayed on the main screen.

In mode m2, three modes are set depending on the size of the sub-screen to be inserted: mode mo for /16 screen display, mode mO for % screen display, and mode m and o for full screen display. In mode m2, the reduction factor on the input side is H
Since d i = l, , Vd i = 1, the size of the inserted screen is determined by the reduction coefficient (-) on the output side of the three modes of the above "ot #" 021m1o.

a m,, mode In this mode, the reduction coefficient 11do, Vd from the second luminance signal calculation C2 is applied to the data of % of the image data of the sub-screen.
This is a mode in which o is l1do = % + Vdo = 3A. Here, when extracting the sub-screen data, as shown by the diagonal lines in FIG. 7, the image data has a reduction coefficient of
=1. Note that even though Vdi = l, it is compressed isometrically to i.

This means that the reduction ratio of the screen is % on the input side, but the reduction ratio of the image data is l. Therefore, the reduction coefficient on the output side is lld.

=%, Vdo==%, so the display is on the entire surface m1.

A screen with the size of ('AX K X station) is displayed.

Also, the content of the displayed image is %(lx t x4ix
4i+). The calculation target of the '2nd correlation calculation in this mode is To + BO as shown in FIG. 9(d).
+M-,,Mo.

This is M+1 five picture element data. Then, a second luminance signal calculation circuit using this data...
6).

rno2 mode In this mode, the output side teno reduction coefficient HdO=1. This is the mode of setting vdO-1. As mentioned above, on the input side, the reduction coefficient is l1di = 1
, Vdi = 1, so the data surrounding the image data is not compressed. However, on the input side, only % of the total image data of the sub-screen is extracted, as shown by adding the diagonally shaded area ζ in FIG. Therefore, in this mode, as a result of the correlation calculation, the image extracted in FIG. 7 will be displayed on the % screen.

Therefore, the image data extracted by the ψ/parter 100 in FIG. 5 is used for image display without interpolating or rejecting the data.

m1o mode In this mode, the second correlation calculation reduces the reduction calculation coefficient on the output side to Hdo = 2. Let Vdo=2.

As a result, as shown in FIG. 9(e), the image can be enlarged by interpolating the data of the four circles extracted from the field memory 134 and the data of the five squares. In this case, the display image is displayed by expanding the image corresponding to % screen of the sub-screen shown in FIG. 7 to the full screen by 4 times (2 times). (Mo+
The data on which the calculation of M+t) was performed, and the same data B. , 11. .

Data on which %(Bo+B++) was calculated,
5A for data BO+ B+t l'r, l'r+ (B(1+ B+1 + 'ro+'r-H)
・・・・・・Data on which the calculation of (7) was performed, data T
. ,B.

Similarly, data Tit l B+1 is calculated as %(T+t
These are five pieces of data on which the calculation of +ll+-t) was performed.

And to this, the data “OI M+1 t BO+ B
A display image is obtained from 9 data including the 4 data of +1.

(Mode for mode m1) The reduction coefficient on the input side of E is Hdi = l, Vd1 =
For mode m, which is set to 1, the reduction coefficient is set to H on the output side.
The mode of m1o with do=2 and Vdo=2 is made to correspond.

In this case, a moving image that is four times larger than the main screen is displayed on the entire screen. Note that the reduction coefficient Hdo=2. Vd.

In order to obtain =2, as in the above mode m10, use FIG.
) Perform the data interpolation shown in .

(Mode for mode ml) Mode mr is a mode for inserting a sub-screen into the digitally processed main screen image. On the output side, modes m and o in which the reduction coefficient is Hdo22°Vdo=2 are made to correspond to this mode on the input side. The reduction coefficient on the input side is Hdi=%, Vd1-%, so 1/1 of the entire screen
A sub-screen with a size of 6 is inserted into the main screen displaying digitally processed signals. In this mode, the calculation for determining the reduction coefficient on the output side is the same calculation as in the mode m1o described above.

(Mode for mode m) In this mode, the main screen signal is digitally processed and displayed in a static state on the entire screen. This mode mJ(
For the second case, the calculation mode for calculating the reduction coefficient on the output side is
The reduction factor is Hdo=2. Mode m where Vdo=1
,. This corresponds to In this case, since the reduction coefficient on the input side is Hdi=% and Vd1=l, the main screen image is displayed on the entire screen. Note that data interpolation on the output side is performed in mode m described above. mode drink for.

It is obtained by a calculation similar to the second correlation calculation performed in .

(Mode for mode m) For mode m, where the input side reduction coefficient is Hdi = %, Vd1 =:% and a sub screen is inserted into a stationary main screen image, the output side reduction coefficient is Hdo = 2. p vdo
This corresponds to the mode m4o which is ``'-''. In the mode with such a correspondence relationship, the image of the sub-screen of the moving image is inserted and displayed in the still main screen image. The phase-to-phase calculation of is obtained by the same calculation as the calculation performed in the above-mentioned modes m and .

As described above, various modes of screen display are possible by combining the mode of the first calculation performed at the input end of the field memory 134 and the mode of calculation performed at the output side. In addition, the displayed screen itself may be a static image,
Any moving image can be stored by controlling the storage state of image data in the field memory 134.

The writing of the image data obtained by the above-mentioned image data to the field memory 134 is stopped, and the reading of the current image data is continued, and the second image data shown in FIG.
The brightness signal calculation circuit performs calculations to obtain a still image. The correspondence between the combinations of calculation modes on the input/output side of the field memory 134 described above is shown in the following table.

(F's 4E1) As described above, in this embodiment, image signals are processed in a wide variety of modes. The problem is how to perform multimode correlation calculations with a small memory capacity.

These problems are solved by means detailed below.

FIG. 10 shows a system block diagram of an embodiment of an image signal processing circuit according to the present invention that performs image signal processing according to the mode shown in the table above. Here, the digital processing of the main image signals is performed by the circuit within the broken line in the figure.

In the image signal processing circuit shown in FIG. 10, a remote control transmitter 50 selects the video signal to be displayed on the screen, and also selects the display mode signal, channel selection signal for the main screen and sub screen, and the strength of the audio to be described later. optically transmit signals that specify the The remote control receiving circuit 51 that receives the transmitted signal is composed of a photoelectric conversion circuit that receives the transmitted signal using a light receiving element, and a microcomputer is used in the decoder 53 to decode the input data 52 and decode the signal corresponding to the transmitted signal. Various switching control signals 54°55.5
6. Channel selection signal 57.58. Operation mode control signal 59. Outputs audio control signals, etc. to each predetermined circuit. In addition, the RF multiplied signal obtained from the antenna 60, the tuner A
, 61, and selects the channel determined by the channel selection signal 58 of the decoder circuit 53. The output 62 of this tuner 61 is guided to an IP detection circuit 63, which receives the audio IP multiplied signal 4. A video signal 65 is output. Here, the audio IF signal 64 is guided to the audio circuit 66, and the audio output 67 is guided to one input end of the audio switching old I path 68. The other input terminal of the audio switching circuit 68 is supplied with output 0 of the audio selection circuit 69 . Then, according to the audio switching signal 54 of the decoder circuit 53, an audio cuff of 1.72 is obtained. Audio switching circuit 68
The output cuff 1 is led to a main screen speaker 73, and the other output cuff 2 is led to an earphone 74.

A video signal 65 obtained by the IF detection circuit 63 is input to a video signal switching circuit 75, and a video signal from a video signal switching circuit 87 is also supplied to this video signal switching circuit 75. In response to the switching signal 55 of the decoder circuit 53, the video signal switching circuit 75 selectively outputs a main screen video signal 77 and a sub-screen video signal 78 to its output.

Further, from the RP signal obtained by the tuner B, 79, the channel selection signal 57 signal (-therefore, the corresponding channel is selected. The selected signal 80 is transmitted to the IP detection circuit 8.
1, and its detected output 82 is converted into an audio IP multiplied signal and supplied to an audio circuit 83.

The audio signal 84 is then guided to the audio switching circuit 74.

In the figure, the other input of the audio selection circuit 69 is an external audio input 85.
It is.

Here, the video 86 and the external video signal 88 guided to the video signal selection circuit 87 are selected according to the selection signal 56 by the decoder circuit 53 to obtain the video signal and the signal 76. In this way, in the system shown in the same figure, the Tuna people.

It is also possible to handle not only video signals obtained from 61 or tuners B and 79, but also input signals 85 and 88 from external inputs, such as VTRs and video discs.

Next, talking about video signal processing, the main screen video signal 77 is led to a main screen brightness signal processing circuit 89 and a main screen color signal processing circuit 90, and the main screen brightness signal 9 color difference signal is sent to each output terminal. The output B-Y96°rL-Y93 is obtained. The main screen control circuit 94 sends control signals 95 and 96 for controlling the display image mode to the main screen brightness signal processing circuit 89. The signal is supplied to the main screen color signal processing circuit 90 to perform control operations. In addition, regarding the synchronization system (in the case of X, the main screen synchronization signal extraction circuit 97
is the horizontal synchronization signal HM 5YNC from the input video signal 77
98, separate the vertical synchronization signal VM 5YNC99.

The sub-screen luminance signal 78 is then supplied to a sub-screen luminance signal processing circuit 1001, a sub-screen color signal processing circuit 101, and a synchronization signal extraction circuit 102.

The sub-screen video signal 78 is sent to the sub-screen luminance signal processing circuit 10.
0, sub-screen color signal processing circuit 101, synchronization signal extraction circuit 1
02, and the sub-screen circuit 103 generates signals 104 and 105 that control the luminance signal processing circuit 1009 and the color signal processing circuit 101. The luminance signal 106, which is the output of the sub-screen luminance signal processing circuit 100, is converted into a digital signal by a luminance signal to Φ converter 1000. On the other hand, the R-Y signal 107. which is the output of the sub-screen color signal processing circuit 101. The B-Y signal 108 is multiplexed at a predetermined timing by a multiplexer 1100, and the signal 109 is guided to the color signal A/D converter.
200 is the input signal sampling frequency φ5=880
/+-+s (/us: sub-screen input horizontal frequency range) = 6
Quantize to bits. The output 111 of the N-converter 1000 is subjected to a first correlation calculation by a first luminance signal calculation circuit 1300. The result of this first correlation calculation is stored in the luminance signal field memory 1400. The data in the field memory 1400 is controlled by the signal 113 of the address generation control circuit 3100.
The read data is recorded in field memo 1J1400.
A second correlation calculation is performed by a second luminance signal calculation circuit on the power side, and this calculation result 115 is stored in the buffer memory.
Guided to J1600.

In this way, on the input/output side of field memory 1400, two
By performing the correlation calculation step by step, it is possible to set the display state of multi-mode video as shown in the table above.

The buffer memory 1600 is read out at a predetermined main screen cycle, and the read buffer memory output 116 is
The signal is guided to an A converter 1700 and extracted as an analog signal 117. Furthermore, the luminance signal 117 converted into an analog signal is amplified by a buffer amplifier 1800 and output to a luminance signal switching circuit 1900. - On the other hand, the R-Y and B-Y digital signals of the color signals multiplexed by the multiplexer 1100 are converted into digital signals by the Nx converter 1200. converted to digital. Digitally converted signal 1
10, a first color signal calculation circuit 2400 performs a first correlation calculation, and the data is stored in a field memory 2500. A second correlation calculation is performed using the data read from the field memory 2500, and the calculation result is sent to the FL-Y for use via the buffer memory 2700.
The RY signal 118 is guided to the A converter 2000, and the BY signal 119 is guided to the BY/A converter 210. And the output 120.121 of each D/A converter
is guided to the output circuit 3100 via the buffer amplifiers 2100 and 2200 and the color signal switching circuit 2300.

Note that the sub-screen horizontal synchronization extraction signal 1 (5YNC122) and the vertical synchronization extraction signal V5YNC123 are the sub-screen timing generation circuit 28 that generates various timing signals for the sub-screen.
I am guided by 00. The various timing signal outputs 124 of this sub-side 1-timing generation circuit 2800 are respectively supplied to the luminance signal digital processing circuit section.

Further, a control signal for controlling the sub-screen display is sent to the mode signal generation circuit 2900 based on the output 59 of the decoder circuit 53.
Various mode signals 125 are generated.

On the other hand, the main screen horizontal synchronization signal 1 (M5YNC98 and vertical synchronization signal VM5YNC99) are sent to the main screen timing generation circuit 300, which generates various timing signals for the main screen.
It leads to 0. This main screen timing generation circuit 3000
The various timing signal outputs 126 generated in the above are respectively supplied to the digital processing circuit portion of the luminance signal and the nine color signals. The field memory address generation circuit 3100 controls the field memories 1400 and 2500 according to the output 113 thereof and the sub-screen timing signal 127 and the main-screen timing signal 128.

Main screen timing generation circuit 3000 output signal 1) G1
Reference numeral 29 denotes a switching signal for switching between the main screen signal and the sub-screen signal, each of which is connected to a luminance signal switching circuit 1900.

The signal is guided to a color signal switching 9 circuit 2300. Luminance signal output 1309 which is switched according to the above switching signal, R-Y signal output 131 which is color signal output, B-Y signal output 132
is supplied to the cathode ray tube 134 via the output circuit 3200. Also, the horizontal synchronization reproduction signal /unu 135 obtained from the main screen timing generation circuit 3000.

Both reproduction synchronization signals of the vertical synchronization reproduction signal /vieM are guided to a synchronization output circuit 3300, which outputs the horizontal deflection signal 137. A vertical deflection signal 138 is output to the deflection system circuit.

As described above, in the embodiment of the image signal processing circuit according to the present invention shown in FIG. 10, image data is processed. The image signal processing circuit according to the present invention processes image data according to modes corresponding to multi-mode image display formats. The processing of image data in this wide variety of modes is
This is possible by performing the first correlation calculation and the second correlation calculation on the input and output sides of the field memo IJ 1400 and 2500, respectively. As shown in the table above, multi-mode image display is performed by performing correlation calculations on image data a plurality of times.

This means that multi-mode screen display can be performed without increasing the memory capacity of the field memory 1400 or 2500, depending on the type of calculation by mode. In this case, in this embodiment, when data processing the luminance signal and the nine color signals, the control means for controlling the addresses for both signals are made similar, so that the circuit structure of the address generation circuit is not complicated. . In addition,
The above correlation calculation is performed on image data in both the horizontal and vertical directions, but in the horizontal direction, it is necessary to write and read data in one water period. This is necessary in order to extract the data to be subjected to the correlation calculation when performing the horizontal correlation calculation, but in this embodiment, two lines of data are read out in one horizontal period. Let's do it. Address generation control for data access to this horizontal image data also follows the multi-mode image display! The circuit configuration is as follows. These features will be made clear by explaining the 4-block circuitry corresponding to the blocks shown in FIG. 10, which shows an embodiment of the image signal processing circuit according to the present invention, and especially the circuit blocks within the broken line area. Dew.

FIG. 11 is a block diagram showing in detail the inside of the circuit blocks of the sub-screen timing signal generation circuit 2800 shown in FIG. The above sub-screen timing signal generation circuit 2800
are the sub-screen horizontal synchronization signal ll8SYNC123, vertical synchronization signal v8SYNC obtained by the sub-screen synchronization signal extraction circuit 102 in FIG. Various timing signals necessary for displaying the sub-screen are generated depending on the signal vs, which determines whether the sub-screen is present or not. The timing signals required for sub-screen display are timing signals for controlling a control circuit for generating address signals for field memories 1400, 2500, etc., and addresses for line memories that store horizontal image data. and a write control signal, a clock signal for processing data in the horizontal direction when processing image data between sub-planes, and a clock signal for processing data in the vertical direction.

First of all, if we look at the reference clock when processing horizontal image data, - horizontal synchronization signal 1 (s8Y
A synchronization signal HsSYNC, which is inputted to NC and supplied with a comparison signal to the other end and subjected to phase comparison, functions as a synchronization signal for the oscillator 2802. The oscillator 2802 generates a clock pulse φ5=88 that defines horizontal timing.
Generates 0/us. This signal φ8 is frequency-divided by two by a frequency divider 2803. Here, the output of the frequency divider 2803 is assumed to be an inverted signal φo8. This signal φos is applied to the counter CT
The output of the color/recTR(1) 2804 is applied to the horizontal timing signal generation circuit 28o5. The horizontal timing signal generation circuit 2805 generates a signal 1 (Rlr) that determines the horizontal phase of the sub-screen as one of its outputs, and this signal is applied to the phase comparator 28o1 as a phase comparison reference signal for the position comparison. Above counter CTR (1) 2
804 is composed of a nine-stage frequency dividing circuit, and the above signal φ
The frequency is divided by 440 in synchronization with the rising edge of so. Therefore,
The horizontal frequency /us is obtained at the final output stage of the counter CT)L (1), and the frequency 27H8 is obtained at the output of the eighth stage. The signal with the horizontal frequency fH8 is added to the counter CTI ((7) 2806, which functions as a vertical counter for determining the vertical phase of the sub-screen, and
The fIIs signal is applied to a counter CTR (61280
Added to 7. In addition to the above-mentioned horizontal phase determining signal l (Rml A signal HI that resets the counter CTR (2) that controls the address generation circuit 2808
L8 and line memory, and stores the sub-screen data in the field memory 140 according to the sub-screen mode.
The timing signal HT (I
I...

11T2).

Note that the line memory address generation circuit 2808 is
Counter CTII(]) depending on the supplied mode signal
2804 or a counter (counts the pulses of 212809 and generates an address signal ADo for the line memory.

ADo2. Generates ADo3. The signal llR8 generated by the horizontal timing signal generation circuit 2805
The line memory control signal generation circuit 2810 is composed of flip-flops that operate in response to vertical reference signals.
Generates signals W and R that control data writing and reading.

Next, in FIG. 11, regarding the vertical timing system, the vertical synchronization signals V and 8YNC of the sub-screen are supplied to the synchronization signal width detection circuit 2811. This synchronization signal width detection circuit 2811 counts the pulses from the counter CTR(1) 2804 during the pulse width period of the applied vertical synchronization signal V88YNC, and uses this count value to determine whether the signal can be regarded as a synchronization signal or not. However, as a result of the determination, only signals that can be regarded as synchronization signals are supplied to the phase comparator circuit 2812. This phase comparison circuit 2812 is connected to the counter CT
rt (Based on the output of 61, the comparison pulse generated by the phase comparison pulse generation circuit 2813 is input, and the phase is compared with the reference phase, and the above-mentioned counter CTR161
Generates a reset pulse for 2807. With this reset pulse, a pulse obtained by frequency-dividing the horizontal synchronizing signal 2/Hs by 525 is obtained as the output of the phase comparator circuit 2812.

In this case, the signal V applied to the phase comparison circuit 2812 and the phase comparison pulse generation circuit 2813 is the synchronization signal V, 5YNC applied to the synchronization signal width detection circuit 2811, which is divided by 525. This signal indicates whether or not the pulse generated by the phase comparison pulse generation circuit 2813 is within the capacitance error range.
1 resets the counter CTR1 (12807). In other words, Vs is the signal that defines the mode of whether or not the synchronization signal 1d is an unstable synchronization signal seen in video games, etc. , the obtained vertical reference signal is supplied to the vertical counter CTR (7) 2806 as a reset signal and is also supplied to the line memory control signal generation circuit 2810. The vertical timing signal generation circuit 2814 is supplied to the field memory 1400.2.
A reset signal V↑ for the write address generation counter of 500 and a signal vio used for presetting are generated. That is, the vertical timing signal generation circuit 2814 generates a pulse for capturing image data in the vertical direction of the sub-screen.

Sub-side timing signal generation circuit 2800 shown in FIG.
is the address signal ADO for the line memory mentioned above.
In addition to signals related to line memories such as I, kD62, ADo, etc., signals H!, φA, etc. that function as pulses for capturing vertical image data of the sub-screen, vT + ``rO, and horizontal data of the field memory. Also, a pulse signal for driving a control circuit for controlling the address of the field memory and an 8 for converting serial format sub-screen image data into parallel format data.
/P conversion signal is generated.

That is, a pulse of φ5o=4407Hs is obtained from the frequency divider 2803 based on the horizontal synchronizing signal ll8SYNC of the sub-screen, and a pulse of φ5o=4407Hs is obtained from the field memory 1400.
2500 field memories to the counter CTJ3) 2815. Counter (4) 2816
．． Field memory control signal generation circuit 2817.
It is generated by the % reduction timing generation circuit 2818.

Data 7 to the above field memory 1400.2500
The timing signal for transmitting and receiving data bit by bit in time division is the counter CT in the normal mode of the sub screen.
Occurs at R(3)2815. This signal is a signal that determines whether the column address callow address is (upper bit or lower bit), and the field memory 14
For the address 00.2500, there is a control signal, a driver enable signal WE', etc. On the other hand, counter CTFL
(4) 2816 is used to generate a timing control signal for the time division of image data with respect to the mode in which the sub-screen data capture mode is horizontal (= half of the normal mode). .Here, the data is expressed as % (=
A control signal for time-divisionally transmitting and receiving the image data of the sub-screen in the compression mode is supplied to the field memory control signal generating circuit 2818 via the data reduction timing generating circuit 2817. This field memory control signal generation circuit 2818 compresses the normal mode and image data by %(-) and compresses the field memory 1.
At 400.2500, a control signal is generated to time-divisionally transmit data into upper bits and lower bits.

Also, the above field memo, 14,00,2500
+- To store image data, it is necessary to convert it to serial data. In an image display mode in which the main screen is an analog signal display and a sub-screen is inserted, the control signal for converting this data format is the S/P conversion timing based on the output of the above-mentioned data type and small timing generation circuit 2817. This is obtained by the signal generating circuit 2819 I-. Here, in the mode table mentioned above, modes m, ', m, which insert a sub screen with a static image displayed on the main screen,
;, m3, it should be noted that the image data is compressed to 178 in the horizontal direction.

When compressing image data to 1/8 in the horizontal direction and converting the data from serial format to parallel format, the counter output of the counter 2820 that operates as a clock check signal layer O-440/US is input. A 1/8 data reduction timing signal generation circuit 2821 obtains a data conversion control signal. This control signal is supplied to the S/P conversion timing signal generation circuit 2819. As a result, the output of the 8/P conversion timing signal generation circuit 2819 is as follows in any of the modes listed in the table above.
A timing control signal is obtained for converting image data from serial form to parallel form. Note that the image signal includes both luminance 16 and 9 color chrominance signals; /P
The conversion timing signal YsS/P1 corresponding to the luminance signal (2'<-j) and the conversion timing signal C8S//P corresponding to the color signal (2') are output from the conversion timing signal generation circuit.

As described above, the MIIt+
An address signal AD0 for storing horizontal image data of the river surface in the line memory.

A Do2. At the same time as A Do3 is generated, various Q) frost control signals for generating addresses of field memo 'J 1400 and 2500 are generated.

The lK11 screen timing signal generation circuit 2800 shown in FIG. 11 generates sub-screen horizontal synchronization signals II, 8YNC,
The reference clock signal based on the vertical synchronization signal Vs 8YNc allows the line memory address (, generation of No. 4, field memo IJ 1400, 2500 +
Performs 1lill system and synchronous system control for the two systems. In this case, the counter CTIt (61280?.

Synchronization signal width detection circuit 2811. Phase comparison circuit 281
Details of the 2° phase comparison pulse generation circuit 2813 are shown in FIG. Here, the synchronization signal width detection circuit 2811
The counter C'rR(+) 2804 shown in FIG. occurs in its output. In addition, the phase comparison circuit 2812 and the phase comparison pulse generation circuit 2813 operate in response to the mode signal v8 depending on the stability of the vertical synchronization signal. This phase comparator circuit 2812 supplies the signal 2fus to a counter CTFL (61
Resetting 2807 simultaneously generates at its output the signals vav, p which are used as the two vertical synchronization signals.

Next, the line memory address generation circuit 2808 of the sub-screen timing signal generation circuit 2800 generates addresses ADo, , ADo2 . FIG. 13 shows the line/memory configuration included in the luminance signal calculation circuit 1300 of FIG. 10. In Figure 13,
The line memories L, , L, , L, , L, which store the luminance signal data of the sub-screen in the horizontal direction, each substantially function as a delay element for one water period. And the first
The address signal 4 A Dol , A I) generated by the line memory address generation circuit 2808 shown in FIG. ,
.

After ADo3, the address signal ADO1 addresses the line memory read, the address signal ADo2 addresses the line memory L, and the address signal ADo3 addresses the line memories L and L4. Each line memory 1~L4
C. RAM with a capacity of 44 words x 6 pits (
RandomAccess Memory) configuration. The common output terminal signal of the line memories LI and L2 is the same as that of the other line memories L3. This is the input signal for L. And write in memo') Ls + L4
A signal delayed by two horizontal periods with respect to the common input signal of the memories L, , and L is obtained at the common output terminal of the memory. These line memories L1 to L4 obtain calculation target data for the first correlation calculation for the image data of the luminance signal of the sub-screen, which is performed on the input side of the field 1400 for the luminance signal data. That is, data necessary for performing the first correlation calculation of the signal T delayed by 2 lines with respect to the current line, the signal M delayed by 1 line, and the current line signal B can be obtained. Note that each of the line memories Ll-L in FIG. 13 includes the line memory control signal generation circuit 281o in FIG.
A write control signal W and a read control signal R generated in the above are applied to control the transfer and reception of data. In this way, the address signal ADo for line memories L, ~L,
, , ADo, , AD, are obtained by the line memory address generation circuit 2808, and these address signals differ depending on the image mode shown in the table above.

This will be explained using FIG. 14. FIG. 14 shows the line memory address generation circuit 2808 in FIG.
Details of the line memory control signal generation circuit 281o are shown.

The line memory control signal generation circuit 281o is 7'J
Consisting of 7" 7o FF, line memory L, -
It generates signals W and I' that control the transfer of data to and from L. On the other hand, the line memory address generation circuit 2808 is a color/recTJ, It2804, which uses 440/H8 as a clock pulse and the output of the horizontal timing signal generation circuit 28o5 as a reset pulse, as shown in FIG.
, Karayata CTR (2) 2809 (7) Denia L! rThe above-mentioned J') m has a function of switching according to the mode of the mode table indicating the mode of image display. The line memory address generation circuit 2808 performs three tests on the count values of the counter CTR(1) 2804 and counter CTI't(2) 2809, which are supplied as a signal defined as an address signal, in accordance with the input mode signal. It is selectively outputted by circuits TS, ~TS. As a result, line memory address signals ADo, , ADo2 + ADos corresponding to the image display mode are obtained.

Address signal ADo+ + ADo according to this mode
The necessity of generating l + ADoB is due to the fact that the amount of image data written to the line memories L and -L differs depending on the screen display mode. That is, in the case of the normal screen display mode, image data corresponding to the entire screen is written to the line memories L, ~L, but in the zoom-up mode, as shown in FIG. Only image data (stroke 1 water data at the center of the screen indicated by diagonal lines) is taken into the line memories L1 to L4. In this way, the amount of image data written to the line memory differs between the normal image display mode and the zoom-up mode, and the data is written to the line memories L and -L, which function as delay lines for one horizontal period, between the two modes. The writing time is different. The problem caused by this difference in data writing time is
This problem can be solved by controlling the address ADOI HAD (H, ADo3) output to the line memory address generation circuit 2808 in both modes using the three-state circuits TS, TS4.

The value of the above address ADQI ADo, l ADO3 is the value of the counter CTR (1) shown in FIG.
2804, Color/ReCTR (2) 2809 The difference is that the count value is controlled by the three-state circuits 'rs, , 'rs4.

The above-mentioned line memories L1 to L4 are divided into writing and reading so that when "II" 3 is in the data writing mode, the line memories L2 + L4 are in the data reading mode. Now, when the line memory L1 is writing 1, the line memory L2 reads data from one horizontal period before, and after one horizontal period, the data in the line memory L is written into the line memory L. After one horizontal period, the data in the line memory L4 is read out to obtain calculation target data T, M, and B, which are the calculation targets of the second correlation calculation. In this case, the above address ADo+ + AI). , is the above color 7 Evening CTR (1
) 2804 and the counter CTR(2) 2809 have different preset values, so the line memory L,
, L, the image data write time and read time are different depending on the write mode and the read mode. However, a common address signal AD0.L is used for line memories L, L, which transmit and receive image data delayed by two horizontal periods with respect to the current data. Use. Here, line memory L3. The counter that defines the address for number L is the counter CTR (1) 2804, and the counter CTR (1) 2804 that functions as this address counter is a counter that defines the address for the normal screen display mode. This address counter CTR (1) 2804
The line memory L1. The three-state circuits T81 to TS operate to read L2 and specify the address. In this way, the read addresses of the line memories L1 to L4 are determined by the counter cT, which performs a 7-address counting operation corresponding to the normal image display mode, regardless of the write mode.
The address number is determined by R(1) 2804. The line memory control signal generation circuit 28
Since the flip-flop FF1 constituting 10 uses the pulse H-S every horizontal period as a clock signal, the line memories IJI, . . . -L4 continue writing and reading data every horizontal period. As a result, regardless of the image display mode, the line memories L1 to L4 operate as delay lines for one horizontal period, but in this case, the data read timing is determined by the counter CTFL(J).
It depends on the counter value of 2804.

Therefore, as shown in FIG. 7, even when the image display mode is the zoom-up mode and the image data for a % screen is written, the data is read out at the same timing as the data for the planned screen. Therefore, when writing to the line memories L, to L4 in the zoom up mode, the data density of the first correlation calculation target data of T, M, and B obtained by reading the data is % at the time of data writing.

In this way, the line memory functions as a data processing speed converter in which data is read out at a constant speed when data is read out, to compensate for differences in data writing due to differences in image display modes.

This is because the preset values of the counter c'rFL(t) 2804 and the counter CTR (212809) are different.

FIG. 15 is a time chart showing the horizontal direction timing signal generated by the sub-screen timing signal generation circuit 2800 shown in FIG. Horizontal timing system is 880/)
440, which is the output of the oscillator 2802 that oscillates at l, divided by 2.
10=Various timing signals are generated based on φso. The signal HR8 generated by the horizontal timing signal generation circuit 2805 is a pulse for each horizontal period, and the signal HR8 is generated by the counter CT.
R(1) 2804, counter, CTlt(2)2
It is used as a reset pulse for the line memory control signal generation circuit 2810+ki data reduction timing generation circuit 2817 and field memory control signal generation circuit 2818.5i data reduction timing signal generation circuit 2821. Further, signals HRBF, 2/H8, and /Ill are used for determining the vertical reference phase. The signal "Tl + 1 (? 2) is a pulse that determines the timing to take in image data in the horizontal direction, H and □ are used to write image data to line memories L1 to L4 in normal times, and HT2 is used in zoom up mode. This signal determines the timing for writing image data.

When writing image data to the line memory LI""L4, the flip controller 7 of the line memory control signal generation circuit 281o controls writing to the write memory.
'FP, is the output signal. And line) MoIJ
Counter CTR (L) 2804, which determines the address when writing L, ~L2 data
The count value of TR(2) 2809 is shown in the figure. As can be seen in the figure, the initial count value of counter CTR(2) 2809 is advanced by 115 with respect to the initial value of counter CTR(1) 28o4. Also counter CTR (2) 2
The clock frequency of 809 is counter CTR (1) 28
It is % compared to that of 04. Note that the above signal H7r
is used for normal image processing mode, and II is used for image signal processing in zoom-up mode. Here, the horizontal sub-screen image data acquisition pulse H, varies depending on the mode classified in the mode table described above.
, I.I.T.

(m0+mj+m, +m2) + HT, (m,'
+ ma) , ·, −(8).

Similarly, regarding the capture of image data in the vertical direction, the timing of writing vertical data differs between the normal image display mode and the zoom-up display mode, and this timing relationship is shown in FIG. In the figure, signal V indicates the timing of capturing image data in the vertical direction in the normal mode, and signal v2 indicates the timing in the zoom-up display mode. That is, at this time, the vertical image data capture timing pulses VT, , VT and the clock signal 10s
l Shows the relationship with the counter address of counter (7) 2806. In this case, the vertical data acquisition pulse VT is v, :vT'l(
mo+m,' + nu+m,) + VT, (m1
+m, ) , , , (9).

Even when the image display mode is the reduction mode, the timing of vertical data capture is defined. However, when in reduced mode, when capturing horizontal image data,
Image data in the horizontal direction is captured discretely according to the reduction ratio. In the % reduction mode represented by m in the mode table mentioned above, it is necessary to reduce the image data in the horizontal direction by %, and the timing pulse for capturing the image in the horizontal direction must also be set to the frequency % fHs of % in the normal mode. The data capture timing pulse for 〇 is %/, , ,
! :There is a need to. The horizontal image data capture timing pulse VTO corresponding to the reduction mode of these display images is expressed by the following equation using the reduction mode indicated in the mode table.

Vto=Vyt (347Ill ・ms+3A/us
@ m, ) ... (11 Figure 17 shows timing pulse 10ss for capturing horizontal image data in normal mode, timing pulse 3Af in reduction mode of 3A, timing pulse %/H 81% in reduction mode)
The relationship between H8 and the count value of the counter CTR (7) 2806 is shown.

In this way, the images are extracted according to the display image mode.
The converted data is input into field memories 1400 and 2500 at the timing described above.

The color signal of the image data of the sub screen is the color signal field memo I.
At the input side of the color signal calculation circuit 2400, which is a pre-processing of the J2500, it is necessary to multiplex the data of the two signals R-Y and B-Y in a time-sharing manner. In this case, the multiplexer 1100 multiplexes the color signals in a time-division manner to produce serial signals in the order of R-Y, B-Y, R-Y, B-Y, . . . . FIG. 18 shows the timing of converting the color signal to the serial form of the RY signal and the BY signal in relation to the luminance signal. In Figure 18,
φos is the horizontal timing signal generation circuit 2 of the sub-screen timing signal generation circuit 2800 that samples the luminance signal.
This is a signal generated at 805.

For the signal φas that samples this luminance signal,
The timing for multiplexing the color signals as described above is performed at the timing of adding two C in FIG.

(Field memory 1400.2500) Next, field memory 1400.2500 stores the first correlation calculation result.
Let's talk about 2500.

FIG. 19 shows a field memory 1400 that stores the correlation calculation results for the luminance signal (two luminance signals) and a field memory 2500 that stores the correlation calculation result for the color signal. Following the control signal generated by the circuit 2819, the image data is converted into a parallel form by the 8/P conversion circuit 1410 and stored in the luminance signal field memory 1420. At this time, the address of the memory is determined by the field memory control circuit. 1430
Field memory address generation circuit 1 controlled by
Occurs at 440. and luminance field memory 142
When reading 0 data, the P/S timing generation circuit '1450 converts the data in order to perform the second correlation calculation.
This is performed by the φ conversion circuit 1460 in response to a timing signal by the φ conversion circuit 1460. Further, the field memory 2500 shown in FIG. 19 that stores the color signals that have been subjected to the correlation calculation stores the data that has been S/1) converted by the S/P conversion circuit 2510 in the color signal field memory 2520. The read data is then converted into serial data by a P/S conversion circuit 2530.

For field memories 1400 and 1500, l
In addition to the timing signal for converting data from parallel format to serial format as described in 2 above, there are also control signals that control the upper address and lower address, and control signals that control the field memory itself according to this address control signal. , a write enable signal WIi is required.

FIG. 20 shows the 11th section which controls the field memory.
Field memory control signal generation circuit 2818 shown in the figure
and % data reduction timing generation circuit 2817 are shown in detail. In FIG. 20, the counter CTR (4) 2816 is reset by the output signal IIR of the 2805, and the timing pulse for converting the image data for the luminance signal in the normal image display mode from the serial format to the parallel format. Synchronized to HRs. This counter CTR(4) 2816 converts data from serial form to parallel form by a group of pulses SPo, S.
P, , SP2. SP, .

Get SP. In addition, the % reduction timing generation circuit 2 with
Counter CT I'L(4) 817 2816 generates the above-mentioned S/P conversion timing pulse that reduces the luminance signal to the horizontal data to the moon in the normal image display mode. The above field memory control signal generation circuit 2
818 receives the signals 880/)Ill and 440firs and generates a signal for controlling the field memory from the output of counter CTR(3) 2815. In this embodiment, a DRAM is used as the field memory, and these signals are necessary for controlling the field memory. Column address strobe signal CAG to control the address, row address strobe signal RAS, column address gate signal CAG to control the address signal, row address gate signal RA
G and write enable signals are obtained by field memory control signal generation circuit 2818.

The counter CT IN (3) 281 mentioned above in FIG.
The timing relationship between the pulses of the 5° counter (4) 2816 and the data sampling control signal system for the luminance signal field memory 1420 is shown. In this figure, the sampling interval of data shown in 5Po-8P4 is one item, and sampling of period data of lφso is stopped between sampling one data and sampling the next data. The signal φso 1 is used to convert the data into P/S and to output/bring the data.
Setting the periodic time interval can be said to have a buffer effect on the processing speed of the field memory. In addition, WS in the figure
T is a timing pulse that reduces the horizontal image data to a square in normal display mode.

Having looked at the S/4) conversion of data to the feed memory in the normal image display mode, next we will discuss the SA) conversion of data when the image display is in the reduction mode.

In the normal image display mode, in order to effectively use the storage capacity of the field memory, the image data is reduced to symbols in the horizontal direction. In the present invention, the display screen can be reduced in multiple modes, as shown in the table above. To reduce the size of the display screen, save the image data to the above field memory by %
(mode m;, m, in the table above). The timing signal for SAP conversion of data in this case is obtained by the circuit shown in FIG. Figure 22 shows the % data reduction timing generation circuit js2x, 8/P.
Circuit portion related to the display screen reduction mode of the timing signal generation circuit 2819, counter CT R (5) 282
Indicates 0. In Fig. 22, the force fy :, y ta CT R(
5) 2820 is a 〇〇 counter, uses φas as a clock pulse, and extracts 5 pieces of data during this time, so the data is reduced to %. Then, the horizontal frequency of the sub-screen is set to t=-qIIR, ka+J, and the output of this counter CT R (5) 2820 is gated by the % reduction timing generation circuit 2821, and the display mode is set as shown in the table above. Mr.

Generates an 8/P conversion timing control signal for image data in m3 mode. That is, as shown in the figure, the data percentage reduction timing signals sp, ;, sp;, sp菖S
p;, 8 P; WST' is generated in the % data reduction timing signal>colored soil circuit 2821. A time chart of these timing signals is shown in FIG. In addition, in FIG. 23, among the above timing signals, SP
; and 8P: are omitted.

- Timing signal S P,; , S P,' generated by the % data reduction timing signal generation circuit 2821
sr:, wsT' is the SAP timing signal generation circuit 2
819 three-state circuit TS, and is controlled by mode signals m,'+m3. Here, the three-state circuit TS receives a timing signal SP when the above-mentioned display image mode is the normal mode. , SP, , SP
,, SP3. SP, , WST are guided,
S/P conversion timing signal generation circuit 2 according to the image mode applied to the three-state circuits ST, ST2.
At the output of 819, h reduction, reduction SA) conversion timing signals are obtained. In this way, an 8741 conversion signal of image data for a luminance signal is obtained.

On the other hand, the S/P conversion timing SPs for color signal data
,SP, ,SP,' and the output Q of flip-flop FFo.

It is made by Q. The above flip-flop FF.

inputs an inverted signal of the writing enable signal WST of the image data of the luminance signal to the field memory 142o, and is reset by the signal HR. The output of this FFo is the three-state circuit T8.・T8. It is a control signal for The color signal is sent to the multiplexer 11 mentioned above.
00, the R-Y and B-Y signals are alternately in real form, so the timing of S/P conversion is as follows.
8. At the timing of adjacent data as in the case of luminance signals. /P conversion is not possible. That is, the color signals are serially 几-Y and B-Y.

From the data group R-Y, . Whether one of the RY signal and the BY signal is extracted and the data is reduced by a month or a percentage depending on the mode depends on the mode signal S in FIG. 22.

This mode signal is used for mode classification of displayed images.
In this case, the color signal data is reduced by 3A42, and a timing chart in this case is shown in FIG. In Figure 24,
The R-Y and B-Y signal data come every cycle of the signal φas, but reducing the data to H requires the signal φos 10 clocks as can be seen from the timing chart of the luminance signal data shown in FIG. Data SP during the period, ~SP
This corresponds to sampling each piece of data corresponding to , one by one. Even when the color signal data shown in FIG. 24 is reduced to a signal, it is reduced to a color signal data signal by extracting one R-Y signal and one B-Y signal from the signal φoslO clock.

Taking the color signal data corresponding to 5pOc' as an example in the figure, since the RY signal data is sampled at time A of the 10 clock period of the clock φos, the data is reduced to %.

Similarly, 5PIC', SP, C'...S
The color signal data corresponding to P and C' are each reduced to %. In this case, the timing signal 8 PoC'~SP,C'
The data are [(RY), (B-Y), (R
-Y), (B-Y), (几-Y)J in the order of parallel data (2 S/P converted. Then, the next set of parallel-converted data is reversed from the previous one [( R-Y), (B
-Y) l (RY) , (B-Y) , (B-Y)
). S/P converted (RY) and (B-Y
) The signal data sets alternate. In addition, in Fig. 24, the R-Y signal is sampled at time A, and the B-Y is sampled at time B after the ILs clock, so the phase error between R-Y and B-Y can be suppressed. .

The time difference between the sampling times of the R-Y signal and the B-Y signal is at most time E,! :P is 2φos clock period. In this way, in the Sβ conversion timing signal generation circuit shown in FIG. 22, although the data is reduced and the data is extracted at discrete times, the difference between the sampling times of the color signals B-Y and R-Y is kept small, and the B -Y and I'L-Y signal phase errors are suppressed. Fig. 25 shows a timing chart when the display screen mode is mr or m3, the mode signals applied in Fig. 22 are m, '+m, and the color signal data is reduced to 5≦. be.

(First Correlation Calculation) The correlation behavior regarding the horizontal and vertical data on the input side of the feed memory 1400 for the luminance signal has already been explained using FIGS. 5 and 8. In FIG. 26, the first correlation calculation for both the luminance signal and the color signal will be comprehensively explained.

In FIG. 26, the latch circuits Latl-12 of the luminance signal calculation circuit 1300 and the color signal calculation circuit 2400 each have a latch function to latch data. However, the latch circuits Lat20 to Lat31 function as geometrical delay elements having a delay time τ corresponding to 10 clocks of the clock signal φso applied as the clock φ.

First, to describe the first correlation calculation for the luminance signal, each of the latch circuits Lat 1 to 3 has (n-1
) Line diagram image data 'J'l'y, n line diagram data My, and (n+1) line diagram data BY are derived, respectively. Here, if the output of the latch circuit Lat21 is taken as the reference time, the input data of the latch circuit Lat21 is at the time τ
time advances by 2τ, and the output data of the latch circuit Lat22 is delayed by 2τ. Here, for a delay of time τ −
1. If we define a subscript of +1 for the advance of τ from 09 hours to the current time, the object of the first correlation calculation is BOYtM+l
It is expressed by five pieces of data: Y, MoY, M-, y, 'ro. The relationship between these five pieces of data is made to correspond to the image data on the display screen, and the sample positional relationship of the data is shown in FIG. In the luminance signal calculation circuit 1300 in FIG. 26, K1- is a multiplication circuit having a function of weighting data with the coefficients shown in the figure.

Further, 5I-8 is an adder that adds data that has been given a predetermined weight. The output of adder S4 is sent to latch circuit La.
t8, the output of the adder S is connected to the latch circuit Lat.
Guided by 9. And latch circuit Lat7
contains image data M. Y is being guided. The latch circuits Lat7 to Lat9 form a three-state circuit.

In this case, the three-state state of the latch circuits Lat7 to Lat9 is stagnated by the mode signal, the clock signal φθ8, and the like. A signal obtained by wire-ORing the outputs of these latch circuits Lat7 to Lat9 is data YMI of the first correlation calculation result for the luminance signal. This calculation result data YMI can be expressed by the following logical equation according to the mode classification according to the mode table described above.

YMI-(Ml+M2)MO+4)([0,25(M
+ty + M-IY)+0.5 N[ov)+(
M, +M3) (o, 12 (M+IY +M-IY
+t30Y +TOY) +0.5M0Y)...
...0υ On the other hand, regarding the color signal calculation list 1400, it is necessary to extract and perform calculations on the I'L-Y signal and the B-Y signal for the color signal. In the color signal calculation, a time-divisional calculation is performed on either the R-Y signal or the B-Y signal, which are transmitted every time τ.

Therefore, regarding horizontal data, data at the reference time (Moo) and a signal delayed by 2τ from this (M-to) -
The signal (M+, o) advanced by 2τ is used as the calculation target. Then, the first correlation calculation result Cold for the color signal obtains the output of the latch circuit LatlO~12 as a wired oasis.

The first correlation calculation result CMf for this color signal is expressed by the following equation.

CMI= (Mt+Mz)May + (Mo+Piq
)(0,25(M+lY +M-IY)+0.5M0
Y ) +(Ml +Ms) (0,125(M+IY
+M-&Y+ B6y + TOY) + 0.5
MOY) ---(tlIn addition, in FIG. 26, the weighting coefficient for the data applied to the multiplication circuit is 0.
．． 5.0.25 and 0.125, but in order to configure this, C2 may have a circuit configuration in which a predetermined coefficient is determined by an adder using a bit shift method. Further, the data as the calculation result is rounded to 6 bits, and the final output data YM) + CMI is 6 bit data.

In this way, the first correlation calculation of the image data shown in creations (8) and (9) does not have a filter effect on the image data having the well-known comb filter characteristic isometrically.

(S/P, generation of timing signal during S/P data conversion) As described above, the result of the first correlation calculation obtained by data processing is that the luminance signal data is stored in the field memory 1400. , color signal data is stored in field memory 2.
500 and then stored. and,
Furthermore, in order to perform a second correlation calculation, the data stored in these field memories 1400 and 2500 is read out and then subjected to P/S conversion. This has already been explained using Fig. 19, but Fig. 28 shows the SA of data.
P, 0th 28th showing details of the circuit that performs P/S conversion
In the figure, luminance signal data to be subjected to SAP conversion is guided to latch circuits Lat1411 to Lat1415 having a 6-bit configuration.

Each of these latch circuits receives a conversion timing pulse 8P generated by the S/P conversion timing signal generation circuit 2819.
latch circuit LatL11 where o and SP are guided.
The output of 1 to 1415 is a latch circuit L consisting of 30 bits.
At 1416. This latch circuit 14
The signal WS_TY generated by the Sβ conversion timing generation circuit 2819 is given as the clock signal No. 16. Image data converted into 87P is obtained as a 30-bit output of the latch circuit Lat1416. This S/P
Compared to the data rate before S/P conversion, the converted signal data rate is 2 degrees when the image display mode is the mode indicated by mo+m, ;, and is 'Ao in the m;+llll5 mode. . This means that in the mode table mentioned above, when the display mode power is ml, m, 11di=% for horizontal data, and the display mode is m.
, ', m, then l1di=%.

Looking at it, it has a circuit configuration similar to that of a P/8 conversion circuit for luminance signals. The 8/P conversion timing signal of the color signal data is controlled by the three-state circuit T8 depending on the image display mode.

That is, when the image display mode is m, + m2, SP
. y ~ 5P4Y is used as the S/P conversion timing pulse, and when the mode is (m, 10 m2) (the display mode is m
l, In.

For other cases), s poc '~SP, C' is S/P
This is used as a timing signal for conversion. In other words, the image display mode of the Sβ conversion timing pulse for the luminance signal data is m, +m! In this case, the φ conversion timing signal is also used for binding the color signal data. Originally, the signal data density of the chrominance signal is % compared to the luminance signal, and the timing of ′ψ conversion is different, but the 8/P conversion timing signal for the luminance signal is used as the timing signal for converting the chrominance signal data to SAP, and the number of circuit elements can be adjusted. In order to reduce this, this embodiment uses a circuit configuration in which the SAP timing generation circuits for the luminance signal system and the color signal system are not separated. In this way, the luminance signal
Timing of conversion (S/1 for system and color signal system) Being able to share the f encoding circuit depending on the display mode can reduce the number of circuit elements (:, the data reduction factor required for the luminance signal) Combinations of color signal reduction coefficients that require 8/P conversion can be easily combined without complicating the circuit configuration. In this embodiment, the field memories 1420 and 2520 are 211 and 211, respectively.
The same configuration of bits is also used for υ).

This field memory 1420.25201:
The above-mentioned 1st and 2nd data sampling circuits perform correlation calculations on image data and S/P conversion.
Read the stored data to perform the correlation calculation of P
/8 conversion (two cases will be described next).

The data stored in the human yield memories 1420 and 2520 is converted into a P/S converter circuit 1460 for luminance signal data and a P/S converter circuit 2530 for color signal data in order to perform the second correlation calculation. A conversion takes place. Timing signals for P/S conversion of data in the P/S conversion circuits 1460 and 2530 are output to a P/S timing source regeneration circuit 1450.

FIG. 29 shows the details of the P-time signal generation circuit 1450. The P/S timing pulse generation circuit 1450 essentially consists of a shift register, and as explained in FIG. Input signal φ.8, output data S1.S2...81G
occurs. FIG. 30 shows the timing chart.

(Generation of control signals for field memory and address control for field memory "M address generation") So far, we have talked about S/P conversion and S/P conversion of data when sending and receiving image data to and from field memory. Next, regarding the circuits that control the address of the field memory and generate the C near address signal, the field memory control circuit 1430 and the field memory address generation circuit 1440 in FIG. How the address is controlled will be explained with reference to FIG. 31 showing details of the field memory control circuit 1430 and field memory address generation circuit 1440.

The shift register SR of the field memory control circuit 1430 in FIG. 31 uses the output φt of the horizontal counter CT R (1) 2804 shown in FIG. VT is input.

The output of this shift register SR (C, D.

E) and the mode signal (m: + m, ) for selecting the mode in which Hdi=% in the mode table described above, a preset data import signal P+G and a data preset signal PG are obtained. In addition, 1. The signal vT, which is a signal that specifies the timing of line data extraction and is expressed by equation 10.
0 is operated by two people in the shift register SR,l. A preset signal PG' for the write address counter CTR(W) of the field memory is obtained from the outputs B and E of the shift register SR. In addition, FIG. 32 shows the signals φt, V
T, PTG, RG, VTo, PG' Indicates the timing chart.

Factors for determining an address when loading data stored in the field memory include whether or not the displayed image is in zoom-up mode, and whether the displayed image is held still.

FIG. 33 is a diagram showing the address area of the field memory in relation to the display drawing, and FIG. 33(a) shows the entire address area when the image display mode is m, for example, 220H (H: (indicates one line). In this case, the reduced data of the sub-screen is stored in the address area of the shaded area. Also, Fig. 33 (
b) shows the address area of the field memory when the display mode is mr; in this case, the reduced data of the sub-screen is stored at the bottom of the shaded area. As can be seen by comparing (a) and (b) in FIG. 33, the area shown in (b) is smaller than the area of 11011 minutes.

This is because in the m1' mode, the amount of image data is small because the image data is captured for the cropped portion of the entire screen as shown in FIG. In this case, to obtain a zoomed-in image, data is interpolated on the output side of the field memory. The reason why the capacity of the field memory may be small even though the image is zoomed up in this way is that the correlation calculation is performed twice on the input and output sides of the field memory.

Image data on the sub-screen as shown by the slopes in FIGS. 33(a) and 33(b) is written by skipping the address areas other than the slope portions after writing the image data on the main screen. In this way,
In addition to the main screen image data written to Jt, further data is written to the field memory (-).

By reading the data written to Fiebelt memory in this way using normal mode addressing,
Obtain an image with a subscreen inserted into the main screen.

To clarify the address skip mentioned above, the signals shown in FIG. 3.21 are related to the address control of the F sub-screen.

In the field memory control circuit 1, 130° field memory address generation circuit 1440 of FIG.
G is led to a reset terminal of a field memory write address generation counter CTR (W) consisting of a 13-stage frequency dividing circuit. 'Also, the preset data acquisition signal P+
G is led to the control terminal of the buffer TS1441 (G) 1442, 1443 and the latch circuit Lat14
44 reset terminal.

The output of 1442 is led to the control terminal of buffer 1445, which leads preset data PR8 to address counter Dw. This preset data determines the start address at which the image data of the sub-screen is stored, and in this embodiment, it is address +2356. Further, the output of the gate 1443 is sent to the buffer TS144.
6 and leads the start address (+4692) to the address line ADw. Signal PT shown in Figure 32
In the area where G is "0", address line ADw2 is connected to address line ADw. address line AD,
, are led to an adder 81447. , start address data +24 for skipping addresses as shown in FIG. 33 to write image data for the sub-screen is led to a latch circuit 1444 for skipping addresses +24. The output of this latch circuit Lat 1444 is led to an adder S 1447, and the output of this adder is led to a preset terminal of a counter CT)t(W). The preset gate signal of this counter CTR (W) is the signal PG' shown in FIG. 32 and the PG logical sum PG'+
Obtained by PG. In addition, the address counter CTR (
The input signal of W) is (VT(m;+m,) +v'I'
. ))('I' - W8TY is applied from the output of the gate circuit 1431.

On the other hand, the read address ADR of the field memory is selectively outputted by the signal wg' via the buffer T8144B. From this switching 1:, within the 111 period (-1II
It becomes possible to write data for I minutes and read data for 20 minutes. The reason why 20 minutes of data is read out in addition to storing 1 ti of data within the 111 period is when performing the second correlation calculation described later, 3 lines worth of data (T).

M, B). In other words, 1
20 while writing apparently 1H worth of data within the tt period.
By controlling the address from which data is read,
The input and output terminals of the field memory can be set in a wide variety of ways.

Note that the address of the field memory is buffer ST (
L) and ST (H). In this case, the address of the upper bit is outputted via 8T(H) and the address of the lower bit is outputted via 5T(L), but this switching control is performed by the S/1) conversion timer control signal shown in FIG. It is controlled by signals CAG and RAG of generation circuit 2818.

-Also, when a control signal for a mode for freezing the image is input to the input of the shift register SR in FIG. 31, the gate circuit 1432 is closed. As a result, the signal WE, which is a write permission signal for the field memory, is cut off. As a result, writing of image data to the field memory is stopped.

In this case, the signal VItS, which is a reference signal for the vertical period, is used to reset the data so as not to stop writing data in the middle of image data for l vertical screens. In this way, by continuing to read image data while stopping writing new image data, a still image is displayed.

(Generation of Timing Signals for Main Screen) Next, details of the main screen timing generation circuit 3000 that generates various timing signals related to the display ζ2 of the 1'-1 main screen will be described with reference to FIG.

In FIG. 34, the main screen horizontal synchronization signal HMSYNC
is led to a phase comparator 3001, and a horizontal flyback signal HF B is applied to this phase comparator 3001. The output of the phase comparator 3001 is the oscillator 3002
The phase comparator 3001 performs control such that the phase difference between the horizontal synchronizing signal 11.5YNc and the horizontal flyback signal HFB becomes zero.

The oscillation frequency φm of the oscillator 3002 is φm=880/
At i+M (/, , main screen horizontal frequency), this signal is led to a frequency divider circuit 3003. The output φm of this frequency dividing circuit 3003 (1 is guided to the main screen horizontal counter CT RQ13004 consisting of 9 frequency dividing stages, and the output of this counter CTRQI) is guided to the main screen horizontal timing circuit 3005. There is. In addition, the above counter CTR
(lQ is led to the output of the vertical counter CT Rc!l3006 for each of the signals fHM and 2fHM, and for synchronous reproduction (D vertical fy counter pcTn (7) 3007. Also, the above-mentioned color CTRα0) 3004 The output of the counter CTR (2013006) is a counter consisting of nine frequency division stages, and the output of a predetermined stage is led to the main screen timing generation circuit 3008. ing.

The vertical synchronization signal VM8YNC is subjected to vertical synchronization detection in the vertical synchronization signal detection circuit 3008 to obtain a detection signal VPM.

The output of the counter CT RQ13007 is led to the f self-reset pulse generation circuit 3009, which is controlled by the mode signal v8 and outputs the self-reset signal, comparison ζ pulse, to the vertical synchronization pull-in circuit 3010. do. The vertical synchronization pull-in circuit 3010 is controlled by the mode signal vM to generate a vertical reset signal VRM, and also supplies the synchronization output circuit 3300i with a vertical drive signal /VDM.

Also, the counter main screen horizontal counter CTR.

The output of Q13004 is the horizontal drive signal generation circuit 30.
111-, which generates a horizontal drive signal /IIDM, which is supplied to the synchronization output circuit 3300.

The outputs of the main screen horizontal timing circuit 3005 and the vertical screen timing 3012 are outputted to an output stage of a cover sofa address generation circuit 3013, a display effect signal generation circuit 3015 that gives a special effect to the display of the sub-screen, and an output stage that generates an analog signal switching signal DG. Analog switching control circuit 3014
is supplied to.

In the main screen timing generation circuit 3000 shown in FIG. 34, when the display mode supplied to the vertical synchronization detection circuit 3008 is rrlos + mIo,
The phase comparator circuit 3011 is rendered inactive. In this display mode, the oscillator 3002 freely oscillates at a center frequency of one wave number. As a result, when a display image is displayed in a stationary state, the oscillator 3002 is caused to freely oscillate and a synchronization signal is generated in the internal circuit.

That is, when the screen is displayed in a stationary state, even if the output signal of the oscillator 2000 is continuously changed in one free run state, the displayed image is prevented from being affected.

Furthermore, the mode RvM applied to the vertical synchronization pull-in circuit 3010 is a signal that determines whether the handled synchronization signal is within the pull-in range of the vertical synchronization pull-in circuit 3010, and VM=O
When , counter CTR (to) 3007°, vertical synchronization pull-in circuit 3010, self-reset pulse generation circuit 30
A synchronous signal is generated by the so-called countdown operation performed at 09. The mode signal vM has priority over the mode signals y, +m, and o, and sets the synchronization system to external synchronization. In other words, in the display image stop mode and when the applied synchronization signal is outside the pull-in range of the vertical synchronization pull-in circuit, the synchronization signal is internally generated by a countdown operation. Fig. 35 shows a timing chart of signals related to the internal synchronization of the main 1 screen synchronization signal. Vertical drive signal/V
D- driver pulse width is 11.5 THM (TII
M: horizontal period of the main screen).

The main screen synchronization signal system signal is determined as described above, and the horizontal drive pulse/HDM and the counter Ci' R(10) 30 are determined in accordance with the horizontal output circuit of the display device.
The phase difference Tx with the output/HM of 04, the pulse width TW + the vertical synchronization pull-in circuit 3010, and the horizontal drive signal generation circuit can be made variable by configuring them as shown in FIG. 35. Monostable multipipulator MM of horizontal drive signal generation circuit 3011 having the circuit configuration shown in FIG.
The phase difference TX+pulse width Tw is controlled by controlling the capacitance values of the capacitors CX, C, which determine the time constant of . The phase difference Tx between this signal /IIM and the horizontal drive signal /IIDM, the signal whose pulse width is controlled /) IDM
The relationship between the two is shown in Figure 37.

(Horizontal and Vertical Display Position Definition of Display Screen) Next, the main screen timing generation circuit 3000 generates a signal for defining the position of the display screen in the horizontal and vertical directions, and this will be explained.

As previously described with reference to FIG. 4, the display position of the sub-screen is set at the positions indicated by p and -mp in the same figure. Now, for example, P1 = 1 to display the screen at the right corner position.
The other positions P2 to P4 are defined in the same way. The main screen horizontal timing circuit 3005 in FIG. 34 adjusts the horizontal display according to the display position shown in FIG. 4 based on the horizontal reset signal HM It, as shown in FIG. Based on the signals Tll1M to TH4M that define the position and follow the timing chart of FIG. 38, a signal GMH' that defines the horizontal display expressed by the following logical equation is generated.

GMH'=TIIIM CPs + P4) mol
+TH2u (PI +P2)mot +TH! +
11 (Ps+P4)m02+To4M(P1+Pt)
mo2+Tnau (mto 10 log)・・・・・・
...(L row) On the other hand, regarding the vertical position regulation, the vertical screen timing circuit 3012 is based on the signals TVIM+ to TV4M according to the timing chart of FIG. Signal G that specifies the vertical position of
Generate yy.

GMV=TV+M (Ps+P4)mo1+TV
! v (P, +P, )mat + Ty3(1'3
+Pn)mo2+To+(Pt+Pt)mo2+ TV
4M (m1G + n1os)...I The signal GMH' that defines the horizontal direction of the display screen and the number 1 Gy that defines the vertical direction are expressed by the above logical formula.
The display area is determined by ANDing both signals.

(Display effect, switching with analog signal) FIG. 40 shows the output buffer address generation circuit 3013, the analog switching signal generation circuit 3015. and details of the display effect signal generation circuit 3015. The gate circuit AND of the output buffer address generation circuit 3013 performs a logical AND operation of the signals GM, , / for specifying the display position in the horizontal direction and the signal G%JV for specifying the display position in the vertical direction. , outputs a signal GMH that defines the display position on the display screen. This signal GMH is input to a shift register 5R31, and the output of this shift register 5rt31 is applied to a counter CTR3υ. Counter CTR (l
υ is a counter consisting of nine stages, and generates a read address signal for the memory as a result of the A-B output logic operation of the shift register.

Further, the output buffer address generation circuit 3013 of the output buffer address generation circuit 3013 performs screen display of the signals generated in the mode signal generation circuit 2900 in FIG. 7 by analog display or by digitally processing the image data. The gate circuit AND is closed in response to a selection signal ME indicating whether to perform the operation. A control signal D determines whether or not the logic value of this gate circuit AND controls the period in which one analog signal is displayed and the period in which a digital signal is displayed in one horizontal period.
'Used as G. Furthermore, a signal avv' whose phase is delayed by one horizontal period with respect to the signal GMv is generated at the output of the shift register 5a32. This signal GMy' is used as a control signal to delay the actual image display by 2 H since it takes time to calculate data during approximately the IH period when displaying the screen.

(Display Effect) As for the display effect, in this embodiment, the display on the sub-screen is not displayed instantly, but a display method is used in which a door gradually opens.

In the display effect signal generation circuit 3015, a signal vrtNt having a pulse width of one vertical period on the main screen is used as a time reference signal for performing display effects. 2 of counter CT R3QQ to which this signal VRM is input
The output for the third stage and the output for the third stage are selectively switched by an external control signal by the switch SW. Now, if the switch SW is connected to the power supply side (= connected), the gate circuit 0
The output signal CPNV of 1'L becomes a 5 second clock signal. Also, when the switch SW is set to the ground side, an instantaneous clock pulse is obtained. The above signal CPNv is a command signal MDo for performing a display effect, which is a shift register 8R.
This becomes a clock pulse for the shift register 8R300 when performing the display effect added to 300. When the above command signal becomes "1", the output A of the shift register 8R300,
A signal Prd obtained by performing operations A and B on B is obtained as the output of the gate circuit AND2. This signal P r d is 7
Dow/count counter D C1' IL consisting of stages
1.

Up-count counter UCT, R1 as DATAI,
2 (in this embodiment, it is 40). The preset data at this time defines the position on the screen from which the door effect on the displayed image is started. Above counter 1) CTf'L1・UCTC2O4
The lock signal is the above signal CPNv.

A signal CP obtained by ANDing the output indicated by C of the shift register 5R300 and the output of the gate circuit NANDI.
Use NVO. The up counter UCTR1 counts up the clock signal, and the down counter DCTRI counts down the clock signal.

Then, the up counter UCTJ is 8 o (qs-Q
7=1), the clock signal is blocked by the output of the gate circuit NANDI (CPNVG=1).

Further, the 7-bit output of down counter DCTRI is supplied to converter CPAI. Similarly, up counter U
The 7-bit output of CTJ is also supplied to comparator CPA2. On the other hand, the output I of the shift register 5R31
is reset by the inverted signal, and the above output I and signal φr
The 7-bit output of the counter c'raaot, whose clock signal is the AND with no (440/u), is supplied to the comparator CPAI,2. Comparator CP
AI coincidence output ""Pr + comparator CPA2
The coincidence output CMP of is led to gate circuits NAND2 and NAND3, respectively. The output of the gate circuit NAND2.3 is applied to the set terminal S and reset terminal R of the flip-flop FF3Q, respectively, and the display screen generates a signal indicating that the door is full due to the door effect here at the output of this FF30. . In order to perform this door effect in which the display screen gradually opens without disturbing the image in the initial stage, the display effect operation is performed after the counters UCTRI and DCTRI are preset. FIG. 41 is a timing chart showing that the display effect is performed after the counter is preset. As shown in the figure, after the signal MDoP for effecting the display effect is generated, preset data is generated for the counters UCTRI and DCTRI, and then the clock signal CPNVO for these counters is generated.

In addition, FIG. 42 shows CPNV for explaining the display effect.
Q+ shows the relationship between the counter address of the down counter, the counter address of the up counter, and the matching outputs of the comparators CPAI and 2, respectively. As can be seen from the figure, the counter addresses are all based on 40 and count up and count down. This means that counter address 4
This means that the image display corresponding to 0 is expanded horizontally. The display screen is enlarged as the pulse width of the output signal of the solid flop FF3Q is enlarged as shown in FIG. 42, and the display image surface of the sub-screen is enlarged. Note that the display effect is performed according to the size of the sub-screen determined for each display mode by performing an OR operation between the display mode signal and the output of the flip-flop FF3Q.

(Control of reading data from field memory) It is necessary to read the image data stored in the field memory in order to perform the second correlation operation. In this case, the image data of the sub-screen stored in the field memory at the timing of the sub-screen must be read out at the timing of the main screen. A control circuit for this purpose is a field memory read address generation circuit 3100 shown in FIG. The block circuit configuration of this field memory read address generation circuit 3100 is as follows.
Shown in Figure 3. In FIG. 43, the field memory read address generation circuit 3100 receives the main screen timing signal G generated by the main screen horizontal timing circuit 3005.
A field memory read timing circuit 3020 receives input signals Mv, GMv', GM) and generates various field memory read timing signals.

This field memory read timing generation circuit 30
In response to the timing signal 671 generated at 20, the display image determines whether data for one line period (l Tus ) of the sub screen is read out from the field memory during one line period (ITHM) of the main screen, or data of two lines is read out. It is determined by the field memory data read monitor circuit 3o21 depending on the mode. One output of the field memory data read monitor circuit 3021 controls the line memory address generation circuit 3022 and sends the line memory address 6 to the line memory address generation circuit 3022.
97 is generated.

Further, the other output 677' of the field memory read monitor circuit 3021 and the sub-screen timing signal 672 are led to a field memory read clock generation circuit 3o23 that generates a field memory read clock. This field memory read clock generation circuit 30
The output 682 of the field memory read address generation counter 3o23 is used as a clock signal for the field memory read address generation counter 3o24. Further, the skip timing generation circuit 3025 generates a timing signal for skipping the read address of the field memory in accordance with the number of lines in which data is discarded when data is discarded when performing the second correlation calculation.

The skip data generation circuit 3026 is a circuit that generates a timing signal for skipping the read address of the field memory according to the image display mode.

The skip data indicating how many lines of read addresses are to be skipped by the skip data generation circuit 3026 and the field memory read address generation counter 3
An adder 3027 adds the count value of o24.

The output of the adder 3027 is immediately preset to the counter 3024 by the output 680 of the skip timing generation circuit 3025. As a result, the value of the field memory read address generation counter is skipped, and the read address of the field memory is skipped. By skipping the addresses in the field memory in this way, the required number of lines of data of the image data in the field memory is read out.

Further, the buffer memory write clock control circuit 3028 in FIG. 43 is the same as the brightness signal cover sofa circuit 1600 shown in FIG. A write clock for the buffer memory of the color signal output buffer circuit 2700 is generated according to the image display mode. The clock signal generated by the buffer memory write clock control circuit 3028 is guided to the buffer memory write address generation circuit 3029, which generates the buffer memory address 694 according to the image display mode signal 690.

In this way, the field memory read address generation circuit 3100 has a function of skipping the read address of the field memory in order to extract only the image data corresponding to the line necessary for performing the second correlation calculation from the field memory. Figure 44 shows the circuit blocks 3020, 3021, 3023, 30 shown in Figure 43.
25 details are shown.

In FIG. 44, the main screen timing signal GMv 605
.

GMV' 618 and Gun 607 are guided to shift registers 5R700°8R701 and 1704, respectively. The clock signal φ of these shift registers SR is 4
A timing signal SP2 for S/P conversion of the sub-screen data shown in FIG. 21 is used.

The output of the shift register 8rL700 and the timing signal SP when converting the data of the sub-screen into 87P, the output 674 of the 8R7oo (8R7oo, sp, ) logic operation 703 is the field memory read address counter 3024. Reset. On the other hand, the output of shift register 8R704 (Srt7
The output cuff 45 of the AND gate circuit 706 of 04A-SR704B・5p4) is a one-stage R111 counter 7.
It is used as a reset signal of 33 and a line memory address signal 711 which will be described later.

Here, the output B of shift register 8R704, 7
32 is defined as Gll.

FIG. 45 shows the S//P conversion timing signals 5P2321 and 82 of the sub-screen data 323, the main screen timing signal Guv605, and the output 674 of the gate 703. Signal Gu
n607, a time chart of the output cuff 45 of the gate 706 and the output signal α1732 of the shift register Sit 704. To explain FIG. 44 with reference to FIG. 45, the output signal (ill 732) of the shift register 704 synchronized with the clock signal CP, 321 is used as the clock signal When the signal GII732 drops to ~γ, the above RIIIFF
The output Q734 rises. At this time, the gate circuit 725
The output of the OR gate 705 (SP2+SP,
) obtain signal 726. Further, the signal 726 is added to the clock of the 1.data current monitor counter 727, and the clock represented by (SP2+SP,) is counted. Counter 727 address 32 Q6 output cuff 2
8 becomes "1" and the signal 5Po319 is input, the AND logic of the gate circuit 729 is completed and the gate circuit 73
1 resets all (FF 733. In other words, the output 1tllI signal 734 of RIIIF'F 733 resets the data (
The signal is "1" during the readout period (period of 32 clocks with the clocks of SP2 + SP4). The above RI
The H signal 734 is guided to the shift register 5It746, and in synchronization with the falling edge of the signal all (8R746A-
8R746B-8'P4) The AND operation result obtains the reset signal 71 of the line memory address counter. Furthermore, the output of the gate circuit 707 is a mode signal (mto)
741 and an output Q739 of FF3, which will be described later, are ANDed to obtain a field memory preset signal 680. The output B of the shift register 5R746 is inverted by the inverter 715 and becomes the clock for the counter 718 (a2itpp (!: when). The counter 718 receives the mode signal (m
o3+m+o) 7]2 * When m2 and ma2713 are each rOJ, the operation is performed so that the l II data read period is "1", similarly to the above R111FF. Now, when the image display mode signal 738 is "1", R2HFF
718117) Q output R21 (720 is 5) 173
o guided by 6 (mo ・mot)・5R736A
-5R7361'3-8P, generates field memory preset signal 743. Note that the gate circuit 702 generates a signal that defines the field memory refresh period of the DIIAM configuration, and the result of the AND operation of this signal with (S l', -1-sp4) is added to the OR gate 710.

FIG. 46 shows a time chart of the main signals among the signals treated in FIG. 44 above.

In FIG. 46, the signal Itll1 is generated within the period of GH732.
734°1 (211?20) occurs. That is, the figure shows that data for 2H of the sub-screen can be read from the field memory during the ITHM period of the main screen.

Note that within the signal G II period, l 1 is transferred from the field memory.
Deciding whether to read 1 minute's worth of data or 2I minutes' worth of data is determined by the reduction or enlargement operation when performing the second correlation operation on the field memory output side according to the mode in the image display mode table mentioned above. It depends on how you do it.

(Address assignment when reading field memory data) Memory read address generation, arithmetic control circuit 3] 0
0 field memory read address generation counter 3
024, adder 3027, skip data generation circuit 3026, line memory address generation circuit 302
2. Buffer memory write clock control circuit 3028.
This circuit shows details of the buffer memory write address generation circuit 3o29. The output 682 of the field memory read clock generation circuit 3023 is a field memory read address counter 75 consisting of 13 stages of counters.
It leads to 0. The reset signal for this counter 750 is a reset pulse 674.

In the image display mode table, the field memory preset signal 680 generated by the skip timing generation circuit 3o25 in the m, o, rrlo/mo modes is connected to the preset terminal of the counter 750, and is output at the rising timing of the signal 680. Preset the counter to a preset value of 689. Further, the output 684 of the counter 750 is led to one input terminal of the thoracic device 751, and the other input terminal of the adder 751 (2 is the skip data 687 determined by the skip data generation circuit 3026. Two types of data are prepared: ``64 address (advance the field memory address by 64) 752 and -32 address (delay the field memory address by 32) 753.This skip data is used in the image display mode n% 'rnH. Controlled by signal 685, when in mo-mo mode, data 752 with a value of +64 is m.When in -r110I mode, data 753 with a value of -32 is used as skip data. Adder 3027 (Line memory address specification) Line memory added to the address generation circuit 3022 (
111H+R2H) signal 723 is the shift register 811
P/8 timing guided by 758 (see Figure 29) (
1) Synchronized with St signal 757. The A output cuff 59 of the shift register S It758 also receives the clock signal.
A logical AND operation is performed with (760 ) and becomes the clock input of the line memory address counter 762 .

Further, the line memory address counter 762 generates a line memory address for storing data read from the field memory in the line memory.

The reset signal of the counter 762 is the line memory address generation counter reset signal 711.
Q, LmRFF3Q, and LmW are line memory write and read signals.

One side signal (Rllll) 734. (R211) 72
0 are led to shift registers SR766 and 5R765, respectively, and are synchronized with the signal 52757 mentioned above. In addition, the shift registers 5R766 output cuff 67o and 5R765 output cuff 68c are guided to each h 5R769 and 5R789,
It is delayed by two clocks of clock signal φs6. Here, the B output of the shift register 8R767 is ItIH'
, the B output of 8R789 will be referred to as 211'. The OR gate circuit 770 includes the signal 11' and the signal 7.
67 is input, and its output is from the output cuff 72 of the NOR gate circuit 771 to the buffer memory write address counter 7.
Reset 74. Further, the signal R2H' is guided to the NOR gate 771 via the OR gate circuit 773.

That is, a reset signal is obtained for the counter 774 before the rise of the signals t'tlit' and +t2u'. Gate circuits 778, 779, and 780 provide clock signals to this counter 774. Further, the clock rate of the clock signal of the counter 774 differs depending on the horizontal data reduction/enlargement coefficient on the field memory output side in each display image mode. When the clock signal of the counter 774 is written as a logical expression, it is as follows.

mol-R2H'-CTR8QI-...11! The 9-bit output 694-1 of J counter 774 is directed to a buffer memory.

(Buffer memory write and read timing)
A flip-flop (FF4) 693 controls reading and writing of data to and from the buffer memory, and is a one-stage counter that operates depending on the rise and fall of the signal GMII 607 described above. This reset of (FF4) 639 is performed at the field memory read address generation time in the image signal processing circuit shown in FIG.
00, field memory read address (43rd
Signal 684 in the figure).

The line memory address of the arithmetic circuits 1500 and 2600 (signal 697 in FIG. 43), and the write address (the fourth
A signal 694 in Fig. 3) is obtained.

(Data complementation and rejection during second correlation calculation) The data reduction and expansion calculation circuits 1500 and 2600 according to each mode signal in the display mode table mentioned above will be described. To understand, please refer to Figure 48 (
a) to (e) will be explained using time charts. Note that the main timing in the figure is the read timing of the field memory RIH734, R211720.

and field memory read address counter preset signal 680. Operation period R] H'790 or R
2H' 791 and an analog switching signal DG indicating the period in which digitally processed signals are displayed within one horizontal scanning period.
167 is shown.

FIG. 48(a) shows a time chart when the image display mode is indicated by -.moI. According to this figure, 2n worth of digitally processed image data is read from the field memory during one period of 0M11607, which is one horizontal scanning period of the main screen. The reduction calculation in this mode is performed in the R2H'791 period, and the calculation results in this period are read into a buffer memory to be described later. The data read into the buffer memory will be read and displayed during the txi357 period. Further, at the rising edge of the preset signal 680, the field memory read address is skipped by 2 o of sub-screens in this mode. As a result, data for two lines required for performing the second correlation calculation in this mode is read out in a period corresponding to one line of the main screen.

Figure 48(b) shows m6-mo: mode and m, -
The time chart in nNo, mode is shown. In this mode as well, as shown in the mode table, two lines, T and B, are subject to calculation, so it is necessary to read data over two lines.

FIG. 48(C) is m. R in the time chart when 3 modes are used
The data written to the buffer memory during the IH' period is
An interpolation operation is performed to double the data density in the horizontal direction,
It will be displayed in the next DG period.

FIG. 48(d) shows a time chart of m2/mo2 mode, and since l1do = l and Vdo = l, it is only necessary to process the data of the same line in code (7)-F--, and the field memory data is , l in one GMH period
Only data II is read from the field memory and displayed.

FIG. 48(e) is a time chart for the m1o mode, in which a preset signal for the field memory read address counter is generated from the output of flip-flop FF3 of the field memory address generation circuit 322 shown in FIG. This preset signal causes the field memory address to be returned by 32 addresses. Therefore, 11 minutes of data in the field memory will be read out twice.

As shown in FIGS. 48(a) to (e), the data in the field memory in each mode is read out, and the read data is compressed between IR)I' or 21'uI' The data is subjected to arithmetic operations such as magnification and expansion, and is stored in a buffer memory.

(Second Correlation Calculation) The second correlation calculation has already been described using FIG. 9, but the interpolation and rejection of data when performing reduction and enlargement operations will be further described using FIG. 49. .

FIG. 49 shows the interpolation and rejection of data concerning only the modes in which characteristic calculations are performed among the modes in this embodiment.

Figure 49(a) is m. -Horizontal reduction coefficient Hdo = X lVertical reduction coefficient Vd in mo1 mode
It is an explanatory diagram when performing an operation of o.-%. In the same figure, 0
The marks indicate data line by line read from the field memory. The following explanation (the same applies to -).

m shown in FIG. - In the mo1 mode, as shown in the figure, for example, n line data and n+1 line data are read out from the field memory, and using the data indicated by arrow C and the own data, the reduction is performed one after another on the m lines displayed on the main screen. will be displayed. In this case, data obtained from two lines of data n+4° and n+5 is displayed on the m+1 line of the main screen. That is, data for three lines of the sub-screen is discarded in the vertical direction.

Figure Φ) is m. Three modes of calculation will be shown. That is, li
In the figure, Δ
Interpolate new data into the marked area. This interpolated data is created from only one line.

FIG. 2C shows calculations in m and o modes.

That is, the case of calculation of Hdo=2 and Vdo=2 is shown. In line m in the figure, interpolation calculations are performed using data on both sides. For the m+1 line, data is interpolated by performing upper and lower interpolation and interpolation calculations using four points on the diagonal. In this case, to generate one line of interpolated data, T(n), M(n+1), B(
3 lines of data (m+2) are required.

The arithmetic circuit that performs the above-mentioned arithmetic operations is shown in the block diagram of FIG. 10. circuit 15
00. Field memory output side color h S calculation circuit 260
It is 0. Both arithmetic circuits 1500 and 2600 have the same circuit configuration except for a part.

FIG. 50 shows details of the luminance signal calculation circuit 1500.

The luminance signal calculation circuit 1500 is a line memo IJ802.
, 803, 804, and 805, and an arithmetic circuit 801 that performs reduction or enlargement operations according to each mode.
It consists of P/8 conversion output data Y of field memory. 135 is led to line memories 802 and 803. The address of the line memory is supplied from the output 697 of the line memory address generation circuit 3022.

Further, the write/read control signal for each line memory is supplied to flip-flops FF3Q and Fl''3Q of the line memory address generation circuit 3022 shown in FIG. 47.

The above luminance signal Yo135, 1) 1 play signal 80
The 6.2H play signals 807 are supplied to launch circuits each consisting of 6 bits. Each latch circuit output follows the definition in diagram M27, and the signal to be calculated is n+t yo, BOYO.
IM+t yOI M,, yOI M-I Y6 +
T+t Yo + ToY6 + T-@Y(1+
It is shown in FIG. 50 using the symbols T6 Y6. In the figure, each signal 801, 808, 809, 810, 8
11, 812, and 813 are led to an arithmetic circuit consisting of a multiplication circuit and an adder similar to the first correlation arithmetic circuit shown in FIG. The operation will be explained below with reference to the drawings and the calculation formulas for each mode.

Figure 50: The output of the latch circuit is mo/mo, and in mode 0.5MoYo+0.25BoYo+0.125 (
The calculation result for the luminance signal is obtained as M-tYo+M++Yo). The clock of the latch circuit 815 is φL (described later using FIG. 45), and the T terminal has m. -rr1o+ signal 817 is added. Also,
The calculation of mo-mo2 mode is O5Mo"o + 0.
25 (BoYo+ToYo), the calculation result is sent to the latch circuit 818. The clock of the latch circuit 818 is φ8o, and the signal - is applied to the T terminal. Also,
m, which performs an enlargement calculation of 11do=2 in the horizontal direction. ＋fu
In the ns mode calculation, as shown in FIGS. 49(b) and 49(c), the rllo3 mode m line calculation and m.

It is understood that the operation q of the m+(m+2) lines of modes is common. That is, the line in mlol- mode, m+
The signal that determines the second line, etc. is the signal of FF4784 in FIG. The logical operation results in mode 3 are the same.

In the arithmetic circuit shown in FIG. 50, the latch circuit 834 is still led to the N(OYo signal, and the latch circuit 834 is led to the arithmetic result of 0.5 (Mo"o+M+I Y6). 834. The clock φ of 831 becomes the φso signal. On the other hand, the T of the latch circuit 831
φ8o is connected to the terminal, iso is applied to the T terminal of the latch circuit 831, and the output of the latch circuit 831.83-1 is wired ORed and applied to the latch circuit 843. The clock of the latch circuit 843 is φ8-2φ8o, and the T terminal has m03+m1O-FF4Q 844
is added. M because no calculation is performed when the image display mode is m2/mo. The Y0 signal is directly led to latch circuit 837. The clock of the latch circuit 837 is φ8
°, and the T terminal is m26 m02838. Then, the operation in “2” 1n01 mode is o, 5Moy0+
0.125 (M+, Y0+M-, Yo+ IIoY
.

+ToYo), the calculation result 820 is led to the latch circuit 821. The clock φ of the latch circuit 821 is φ,
m2・m(1, signal is applied to the T terminal. Also, m
, In the calculation corresponding to the m4-1 line shown in FIG. 49(C) in the o mode, the calculation result is obtained by two types of calculations. In this case, the latch circuit 824 in FIG.
' is an interpolation calculation 05 (Bo
Y.

+ToYo) calculation result 820 is derived. On the other hand, the calculation result 828 of 025 (BoYo+ToYo+B+IYo+T+1Yo) is led to the latch circuit 827.
The clock and T terminals of the latch circuits 824 and 827 are similar to the latch circuits 831 and 834 described above. That is, a φ8o force is introduced to the clock terminal of the latch circuit 824, the T terminal 825, and the glue terminal of the latch circuit 827. An 18° signal is applied to the T terminal 829 of the latch circuit 827. And the final stage latch circuit 84
The clock of 0 becomes φ8, and the T terminal 841 has m, δ・
The FF4Q signal is added. Data 137 obtained by wire-ORing the outputs of each of the latch circuits described above is written to the buffer memory.

(Correlation Calculation for Color Signals) The second correlation calculation for luminance signals has been described using FIG. 50. Next, the second correlation calculation for color signals is m.

It is equivalent to the luminance signal calculation except for the reduction calculation in I mode. m in Figure 51. , shows a reduction arithmetic circuit in mode. Eight·
Calculation result of color signal in rr1oI mode, (o, 5
MoCo 10 (125”o Co + o, 125
(M+ 1Co+ Nl -tCo)) 890 is led to a latch circuit 891. Note: Moco, BoCo
Symbols such as . . . are given in accordance with the symbols in FIG. 50.

Output L of latch circuit 891 using φ8° as a clock signal
B 893 and L^890 are guided to a 6-pit data selector 894. This data selector 894 has a control X terminal 895, and operates to lead the signal LA 890 to the output 896 when the X terminal is "1", and to lead the signal LB 893 to the output 896 when the X terminal is [Ol]. .

Now, the CTR8IQ signal is led to the X terminal, and φL (φL-CTR8IQ1・φ8
Q) and a mo-mo1 signal to the T terminal 899, a reduced signal in mo-mol mode is obtained at the latch circuit output. FIG. 52 (2) shows a time chart of data during correlation calculation for the color signals shown in FIG. 51.

In this FIG. 52, the performance results synchronized with the clock φ8o, that is, the data of 890 points are, for example, R-Y, B-Y, I
't-Y, . . . are flowing in this order. This data flow is controlled by the multiplex signal CTR8IQ2, and by latching the φ and double signals, the latch circuit 8
97 output 126 has R-Y', B-Y', R-Y'
, . . . reduce the color signal data to the stations indicated by .

In Fig. 51 showing the correlation calculation circuit for color signals, m2・m
m also in oI mode. -H reduction calculation is performed with the same circuit configuration as in the mol mode. The color calculation output 126 obtained according to each mode is written to the buffer memory.

(Writing data to output buffer memory) FIG. 53 shows a specific circuit diagram of the luminance signal output buffer 1600 and the color signal output buffer 2700.

In FIG. 53, buffer memory write address 694-1.
Write/read control signal (Fig. 47 PF4 output) 694
-2, 694-3 and buffer memory read address 566 are switching buffer circuits 856, 857,
It leads to 858°859. The switching buffer circuit supplies write and read addresses 860, 861 to data buffer line memories 850, 851, 853, 854 according to control signals 694-2, 694-3.

Now, when the control signal 694-3 is "L", the line memories 851 and 854 are in the write mode, the write address 694-1 is led to the address 861, and data is written. At this time, the control signal 694-2
becomes "0", and the line memories 850 and 85
3 reads data according to read address 860. The buffer line memory luminance signal output 852 is routed to a latch 862 for phasing with the chrominance signal. In addition, the latch 862 outputs, and the force is further applied to two stages of latches 863 and 864.
A 6-bit luminance signal output Yout 139 is output. The color signal buffer memory output 855 has different R-Y and I(-Y signal sequences) depending on the mode.

FIG. 54 shows a signal train in the m, o+ m03 mode.

FIG. 55 shows an m, o+ mo3o- mode time sequence.

To explain the circuit of FIG. 53 with reference to FIGS. 54 and 55, the latch circuit 865 in FIG. It is a latch circuit.In each latch circuit, B-Y,
Detection of the RY signal is performed by controlling each latch circuit. In addition, the input of the counter FF5870 is 61
The inverse φmoa 867 of 4 (see FIG. 40) is input. The input of the counter FP5871 is FF5'8
70 Q1 outputs are led. Also counter 870.
871 reset terminal (the second is the buffer memory read address counter reset signal 616 (see Figure 40)
is guided. As a result, the latch clock φa-y 8
81 and φIL-Y 822 are obtained by the following logical formula.

φ, -Y: (mo3+m, o) @φmosc・FF6Q
, 10m, , +m, 6@(6mOR・FF5Q4-(IQ
φB-y: (lηo3+m.,)-φmou-FF6Q
2+mo3+mo+ ・φmoa −FF5Qr=(1
7) Gate circuits 874, 875, 876, 877
and 879 and 880 are the iwl paths that implement the logic of the above two equations. Figures 54 and 55 are mo,
+ m. , mode and mo, + m. , these timing charts in the mode are shown.

As you can see from the timing chart, φa-y881
By providing φa-v882, the latch 86
The output of latch 866 provides the B-Yout 129 signal, and the output of latch 866 provides the R-Yout 128 signal. Also, in Figure 53, Yout 139, B-Yo
ut 129, R-Yout 128 and φmo
a 867 inverted signal D/A converter clock φl
lA383 are each led to a D/A converter circuit.

In the block diagram of FIG. 10 described above, YOLIt13
9 is led to the D/A converter 1700 and Y-DAC 140 and is converted into an analog signal. Similarly, R-Yout
128 is led to R-YDAC2000 and converted to an analog signal, B-Yout129 is led to B-YDAC210
0 ni led 7 s 0 g signal 1:.

converted. The converted analog signal is led to buffer amplifier circuits 1800, 2100, and 2200, where it is subjected to DC level adjustment and gain adjustment, and the analog-converted luminance signal is exclusively used for luminance signal output times 1900.

The color signal is guided to a color signal switching circuit 2300.

The analog switching signal DG mentioned above is a double switching circuit 1900.

2300, and the signal DG is the cut plane of rlJ (
2) Lead the digitally processed image signal to the output circuit 3200, 1) (When 1167 is "0", the main screen signal Y, R-Y
, B-Y are switching circuit outputs (two leads 130, 131
, 132 are led to the output circuit 3220, and the output circuit output 1
33 drives a CRT 134.

(Effects of the Present Invention) As is clear from the above description, according to the present invention, when inserting a sub screen into the main screen and projecting it, the first screen is inserted through the input yield memory. In order to perform the second correlation calculation, many types of correlation calculations can be set for the image data, and the image display form can be set in many ways across multiple modes. The degree of freedom in selecting this image mode is not limited to the size of the display screen, but also the selection of whether to display a moving image or a still image, and the mode selection of whether or not to display a zoomed-in image. I can say it.

Also, the image data when inserting a subscreen on the main screen is
1 digitally processed sub screen within 1 horizontal period of the main screen
Image data corresponding to a horizontal period is written to the field memory, and multiple horizontal periods of the sub-screen (in this example, 2
Since the image data of the horizontal period) is read out, the correlation calculation of the line correlation can be performed on data of multiple lines. This means that even when performing correlation calculations in the horizontal direction, image data of not only the current line but also other lines are subject to the correlation calculations, so an image with good resolution can be obtained.

Also, regarding the synchronization system, when inserting a sub-screen into the main screen, synchronization of the sub-screen is performed using the synchronization thread of the main screen (image processing is performed in turn), so no disturbance in the synchronization of the inserted image occurs. Furthermore, regarding the synchronization of the main screen or the sub-screen itself, it is determined whether the supplied synchronization signal is within the internal synchronization pull-in range.

Within the pull-in range (= If there is, synchronize by internal synchronization,
As for the case outside the pull-in range, the circuit configuration is such that the internal synchronization system is reset by the supplied synchronization signal and then shifts to the internal synchronization system, so that the synchronization system can be kept in a stable state.

Furthermore, the first correlation calculation is performed. Since the correlation operation is performed separately into the second correlation operation, the capacity of the field memory is inevitably large when performing the correlation operation with a single operation, but in the present invention, the capacity of the field memory is required The field memory capacity is relatively small, only 8%. This means that if the display ratio 1 product of the sub-screen to be inserted is reduced, image data will be rejected, but this data rejection will be performed multiple times on the input/output side of the field memory, so the field memory capacity will increase. This is understandable because it requires less. Furthermore, since the circuit configurations of the field memories for luminance signals and color signals are approximately the same, the address circuits can also be configured approximately the same, so that the image signal processing circuit according to the present invention is easy to integrate. It also has suitable effects.

[Brief explanation of drawings]

FIG. 1 is a general explanatory diagram showing the insertion of a sub-screen into the main screen, FIGS. 2 and 3 are block circuit diagrams showing conventional image signal processing circuits, and FIG. 4 is an image according to the present invention. An explanatory diagram for explaining the image display position displayed by the signal processing circuit, FIG. 5 is a circuit diagram showing the i-th correlation calculation circuit of the image signal processing circuit according to the present invention, and FIGS. FIG. 8 is a circuit diagram showing the second correlation calculation circuit of the image signal processing circuit according to the present invention, FIG. 9 is an explanatory diagram of its operation, and FIG. A circuit block diagram showing the entire image signal processing circuit, FIG. 11 is a circuit block diagram of the sub-screen timing signal generation circuit in FIG. 10,
12 is a circuit diagram showing the vertical synchronization detection circuit in FIG. 1O, FIG. 13 is a circuit block diagram showing the field memory input line memory, FIG. 14 is a circuit block diagram showing the line memory address generation circuit, and FIG. The figure is a timing chart of the circuit in Figure 14, Figures 16 and 17 are timing charts that explain the vertical timing of the sub-screen, Figure 18 is a timing chart that explains color signal multiplex timing, and Figure 19. 20 is a circuit block diagram showing the luminance signal and color value field memory in FIG. 10; FIG. 22 is a detailed circuit diagram of the circuit in FIG. 11, FIGS. 21, 23, 24, and 25 are timing charts for explaining the same, and FIG. 26 is a first correlation calculation circuit diagram, Second
Figure 7 is an explanatory diagram, M2S diagram is the S/P of image data,
Circuit diagram for explaining the circuit that performs P/8 conversion, Part 2
Figure 9 is a circuit diagram showing a circuit that generates a timing signal for P/8 conversion, Figure 30 is its timing chart, and Figure 31 is a circuit diagram showing a circuit that generates a timing signal for P/8 conversion.
FIG. 32 is a circuit diagram showing a two-yield memory address generation circuit, FIG. 32 is a timing chart for explaining the same, FIG. 33 is an explanatory diagram for explaining address skipping,
FIG. 34 is a circuit diagram showing the main screen timing generation circuit, FIG. 35 is a timing chart for explaining vertical synchronized playback, FIG. 36 is a circuit diagram for explaining the horizontal and vertical drive signal generation circuit, and FIG. 37 is a circuit diagram for explaining the horizontal and vertical drive signal generation circuit. FIG. 38 is a timing chart for explaining the same. Figure 39 is a timing chart for explaining the vertical timing of the main screen, Figure 40 is a circuit that performs a door display effect,
41 and 42 are timing charts for explaining this, FIG. 43 is a circuit diagram showing a field memory read address generation circuit, FIG. 44 is a detailed circuit diagram of FIG. 43, and FIG. 45. Figure 46 is a timing chart for explanation.
Fig. 7 is a detailed circuit diagram of Fig. 38, Fig. 48 is a time chart explaining address skip when reading from the field memory, Fig. 4'1 is an explanatory diagram of correlation calculation, Fig. 50
The figure is a circuit diagram for performing the second correlation calculation, Figure 51 is a diagram showing a circuit for performing the correlation calculation for color signals, Figure 52 is a timing chart for explaining it, and Figure 53 is the speed of data readout. Circuit diagram showing a circuit that performs conversion, No. 54
FIG. 55 is a timing chart for explaining this. 1420... Luminance signal field memory 1430...
Field memory control circuit 1440... Field memory address generation circuit 1600... Luminance signal output buffer circuit 2700... Color signal output buffer circuit 252
0...Color signal field memory 2806...Horizontal timing generation circuit 2808...Line memory address generation circuit 2800
...Sub-screen timing generation circuit 2811...Synchronization signal width detection circuit 2812...Phase comparison circuit 2813...Phase comparison pulse generation circuit 2814...Vertical timing signal generation circuit 2817...% data reduction timing generation circuit 2818... - Field memory control signal generation circuit 2821... 3 data saving reduction timing signal generation circuit 2900... Mode signal generation circuit 3000... Main screen timing generation circuit 3025...
・Skip timing generation circuit 3026...Skip data generation circuit 3028...Buffer memory write clock control circuit 3100...Field memory address generation circuit (7317) Agent Patent attorney Noriyuki Chika (and 1 other person) ooooooooooo o
ooooooooo. Figure 9 (Q) ooooooooooooo. ooooooooooooo. ooooooooooooo. ooooooooooooo. (C) ・■・−・■・ ・■・−・■・ , cd) Cabinet・ −・ ■・ −・ Figure 48 (a) Figure 48 (b) MO-MO2u-do s4 Hdo-1, Vdo-172
M2・M%+ (-do chair Hdo -1/2. Vd
o -172 Fig. 48 (C) Fig. 48 (d) M2 ・Mo2 i-F vs. Hdo-1, Vc$o= 1
Fig. 48(e) Mlo(-do df Hdo-2, Vdowa2MS4
Figure 9 (a) Mo-Mo1t-h- n 9Ishite'ri0 Δ ()→-do\-()
−11−−−−−−9, m9(shin+19ii−9o Δ 0 Δ 0 −1u−m++
U4n (c) M + Teito 1 Father Figure 51 Figure m2 ``01 Figure 52 Figure 531'!'1 Figure 54 φt Y Figure 55 φt v Procedure Amendment (Method) 1. Indication of the case Patent application 1983 - IJliS! No. 34 2. Name of the invention i1m Ishin -! Il & Dan circuit 3. Person making the amendment Relationship with the case Mr. Yuan Applicant (307) Tokyo Shibaura Electric Co., Ltd. 4. Agent Address: 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100 March 23, 1933 (Shipping date) 6. Subject of amendment 7. Contents of amendment (1) Attached specification of the present application (Fuji 3N+ to An engraving of 133 drawings of the pot. (No changes in the contents) [An engraving of the drawings with the original stm. (No changes in the contents.)
ni (knee)

Claims (1)

[Claims] According to the synchronization system of the main screen, the width of the main tooth or the entire surface is
In the 1-false signal processing circuit that inserts the image of the I & 11 screen, at least the main screen's water-'F is controlled by the PI period iI1 and the horizontal flyback IH and is n times the horizontal frequency (n is an integer of ). σ] an oscillator that oscillates a clock signal, and the oscillator output '4! : a copper lσ) counter that counts the number of stitches in one horizontal period; a #20 counter that can count one vertical period by inputting a predetermined ratio of the first counter; and a step synchronization detection circuit that detects the incoming main screen synchronization zero. Then, when the predetermined output of the third counter is asked, the comparison result with respect to the narrow detection inertia is determined. , a vertical synchronization pull-in circuit that detects the phase difference between the comparison pulse and the vertical detection signal and generates a No. 1 or self-reset signal to the second counter under predetermined conditions; a horizontal drive signal generating path for synchronizing with the horizontal drive signal 'lt of a predetermined width; means for obtaining a vertical drive signal of a predetermined width in synchronization with the output of the second counter; means for obtaining a mode signal that is projected on the entire surface, and the forced VC #
A video signal processing circuit that cuts the control loop of the oscillator to provide a running oscillation, and causes the second counter to perform a self-resetting operation. (Left below) Engraving of detailed shop (no change to independence)