JPS5858666A - Data processor - Google Patents

Abstract

PURPOSE:To shorten an effective memory access time, by possessing one of plural processors with a cache memory accessed by an imaginary address, and holding an address converting device in common by all processors. CONSTITUTION:In case when an I unit 43 accesses an instruction word to be executed, if its instruction word exists on an instruction cache 41, it is sent to the I unit 43 through a bus 45. Unless it exists, an imaginary address of the instruction word is sent out to a memory controller 12 through a common bus 50, the imaginary address is converted to a physical address, and a main memmory 10 is accessed through a memory bus 11. An obtained data (instruction) is sent to the instruction cache 41 and the I unit 43, and to an E unit 44, ''what to do'' is instructed. Subsequently, a necessary data is collected from a data cache 42, operate-processed, and stored in the main memory 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device in which a plurality of processors all share one main memory (hereinafter abbreviated as main memory).

At least one of the plurality of processors is a processor that accesses memory using a virtual address in order to execute instructions, and this processor is herein referred to as a job processor.

In addition, at least one is a processor that performs memory access using a virtual address in order to perform input/output with an external storage device (hereinafter referred to as external memory), which is also called an auxiliary storage device. The processor is called a file processor.

The job processor is also equipped with character memory that is accessed using virtual addresses.

Further, the data processing device according to the present invention includes an address translation device that is commonly used by each processor and converts a virtual address into a physical address.

The present invention addresses problems that occur when the file processor updates the address translation table when rewriting the contents of the main memory (page roll-in, page roll-out) in such a data processing device. The present invention relates to a data processing device that solves problems caused by the collapse of the conventional concept that memory is a copy of main memory.

First, the background of the present invention will be explained in detail.

A data processing device in which one main memory is shared by multiple processors is generally referred to as a multiprocessor system.

Conventional multiprocessor systems generally allow multisystem configuration without imposing the cost/half-over-maximum cost of a single computer. Therefore, when the number of processors is about two, it is an optimal configuration, but as the number of processors increases further, there is a problem that mutual interference increases and the hardware configuration becomes too large.

One of the problems that must be solved in multiprocessor systems is the virtual memory system.

The well-known virtual memory system assumes that main memory and external memory are apparently one unit, and that the information requested by the processor is not located in main memory but in external memory. In some cases, the system automatically transfers information from relatively unused portions of main memory to external memory and transfers requested information from external memory to main memory. - Transferring information from main memory to external memory is called rollout, and conversely, transferring information from external memory to main memory is called rollin.

Such roll-in and roll-out controls are used by being divided into units called pages.

For each page, information about whether the page is currently in main memory and, if so, what the corresponding physical address (also known as the real address) in main memory is. , placed on the conversion table.

The address when the processor accesses the memory is given as a virtual address, and the upper address part of the address is looked up in a translation table to be translated into a physical address.

Such a translation table is required for the number of virtual address pages and requires a large amount of memory. Therefore, in an attempt to reduce the capacity, the translation table is divided into a segment table and a page table. Many of them perform two-level address translation.

As mentioned above, the conversion table requires a large memory capacity, so it is generally placed on the main memory. Therefore, if the main memory conversion table is checked every time there is a memory access from the processor, one memory access request will always result in three or more memory accesses, and the overhead cannot be ignored. .

Therefore, many processors that use a virtual memory system are equipped with a high-speed buffer called TLB, and this high-speed buffer stores a physical address corresponding to a recently used virtual address.

According to this, when a memory access occurs from a processor, it is first checked whether there is a corresponding address in the TLB, and if there is, a translation table is created for address translation. No memory access is required, and the overhead of address translation is small, allowing access.

Conventionally, such an address translation device including a TLB was placed in each processor, and a virtual control method was realized with the help of a control device within the processor.

On the other hand, in order to improve performance, it has become common to provide each processor with a high-speed memory called memory. This cache memory is a copy of a portion of main memory and is typically designed to be 5 to 10 times faster than main memory.

When accessing memory from the processor, it is first checked to see if there is a corresponding item in the cache, and if there is,
The contents will be sent back, and if not, the main memory will be accessed.

By the way, when using a virtual memory system and having a cache memory, conventionally, the TLB, the memory, and the main memory are connected in this order from the perspective of the processor. This is based on the idea that the cache memory is a copy of the main memory, which is real memory, and the cache memory had to be accessed after being converted to a physical address.

Such conventional methods have the following problems.

The first problem is that the effective memory access time becomes longer.

The reason for this is that when accessing the cache memory from the processor, the access must always go through the TLB. In other words, the virtual address from the processor is
This is because the cache memory is accessed after converting it into a physical address using 'f'LB.

The second problem is that TLB is required for all processors.
When the number of processors increases, not only does the amount of hardware increase accordingly, but it is also necessary to correct TLB deviations, which increases complexity.

To correct TLB misalignment, when a processor swaps a page, it updates the translation table and TLB entry, but it must notify not only that processor but also other processors and clear the corresponding part. Must.

This is generally 'I' L, 13 purge ('
l'ranslation Lookaside f3u
-r purge), and is one of the important points when configuring the -r A/f processor.

The third problem arises from the fact that general job processors use virtual addresses when accessing memory, but input/output processors do not have a TLB and therefore access using physical addresses. The disadvantage of this is that conversion is required when passing, which increases overhead.

The fourth problem is similar to the second problem, but even if it is not a multiprocessor, in a processor that uses advanced pipeline control, the unit that accesses instructions and the unit that accesses operands are separate. Each unit has a cache memory to increase speed, but in this case too, in the conventional system, each unit must have a TLB, which increases the amount of hardware.

In order to solve this problem, Japanese Patent Laid-Open No. 49-53339 discloses a method in which the cache memory is accessed using a virtual address and address translation is performed only when there is no hit. Although this method eliminates the need to perform address translation every time the cache memory is accessed and is fast, the publication points out that this method cannot be adopted because it has the following drawbacks. There is. It does not work if: (1) two different virtual addresses refer to the same physical address; This is because when the contents of a certain virtual address are rewritten, the contents of the cache memory specified by another virtual address indicating the same physical address must also be rewritten.

(2) When rewriting the contents of a page nickname or segment table, a special scan is required to invalidate the cache.

(3) Since the strain key corresponds to a physical address, protection checks are impossible.

There are three points.

Japanese Unexamined Patent Publication No. 56-38649 similarly discloses a method of accessing a cache memory using a virtual address, but does not mention a solution to the above problem.

Next, Japanese Patent Laid-Open No. 55-142476 discloses a system in which an address translation device is shared by a plurality of processors. According to this document, the cache memory is not shown to be economical in a multiprocessor configuration because it is shared by a plurality of processors.

The present invention is applied to a configuration in which there are multiple processors, at least one of which has a cache memory that is accessed using a virtual address, and the Natres conversion device is shared by all processors.

The purpose of such a configuration is to
.

The purpose is to reduce the amount of hardware required and to shorten the time required for effective memory access.

The other purpose is -T! The object of the present invention is to provide a method that does not require complicated processing such as matching control between 3Ls.

Another purpose is to provide a method that allows input/output processors to access memory using virtual addresses, and to centralize address management.

Another purpose is to realize a fast and economical memory control method in a computer consisting of multiple units that perform pipeline control.

However, the biggest problem with this method is that
The problem pointed out in 53339 is that when a main memory page or segment key or pull is rewritten, this is not transmitted to the cache memory, and the contents of the cache memory no longer correctly reflect the state of the main memory. be.

An object of the present invention is to provide a data processing device that solves this problem.

Next, the concept of how the present invention solves the problems pointed out in the above-mentioned Japanese Patent Laid-Open No. 49-'533'39 will be explained.

The first problem is that two virtual addresses cannot indicate the same physical address, which is necessary in this case, but multiple virtual memory is required. This was necessary when the length was small, about 24 bits, and the virtual space was insufficient, at about 2" = 16 Mega, so 2" = 4 Giga.
If a virtual space as large as 248==256 tera can be supported, there is little need for multiple virtual memories. Furthermore, coplanar subroutines or accessing data using different virtual addresses is not a good method because it complicates real estate management. Therefore, all programs.

In the case of a single virtual memory where data is assigned a unique address, this is not a problem.

Next, the second problem, which is essential when accessing a cache using a virtual address, will be explained in some detail. To update the address translation table, (i
) If a missing page fault occurs during the execution of a program and you roll in the necessary page, or if you roll out a page to create an empty area, (11) Generate program 1 and If the virtual address is too small, the cache memory may contain data that has already been rolled out and is not in main memory, or the previous program may remain in the cache memory even though a new program has been generated. The fact that information that has already been rolled out remains in the cache means that the cache memory is a space including the external 4 memory, and can be thought of as a cache, and information that has already been rolled out can be read. There will be no inconvenience.

Conversely, the main memory size increases by the number of characters, which can be said to be an advantage of this method. When an attempt is made to write to main memory, the store memory passes through an address translation device each time the page is in main memory in order to update both the cache and main memory for each write. It is checked whether or not. Therefore, a program running using rolled out pages will continue as long as the cache is flush on a read, and will either miss or cause a page fault when a main memory write occurs. will occur. Here, the check in the address translation device means that the state of the page is (a) existing in main memory, (b) during paging, (
C) There are three states: not present in main memory.A general processor can access the file only in (a), and a file processor that transfers to external memory cannot access it even in (b). This is a check to see if it is possible and meets this rule.

When a page fault occurs, the corresponding block in the cache memory is invalidated, so it will no longer be hit in the cache. Note that if a page fault occurs during read access, the block is controlled not to be written to the cache.

Next, the program you have been running will complete.
・When a new program is generated at the same virtual address, it is normally transferred from external memory, but in this case, during transfer from external memory,
The problem is solved by providing a means to invalidate the cache. Specifically, transfers from external memory to main memory are performed using virtual addresses, and this address is monitored by the cache memory, and if there is a corresponding block in the cache memory, it is invalidated. be.

Next is the third issue of protection.
Virtual addresses are considered to be a better method than physical addresses because they allow a unique storage key to be assigned to each program. However, since writing always passes through an address translation device, write protection is always checked. When a write protection error is detected, the corresponding block in the cache memory is invalidated to prevent the data written to the cache memory from being used. Execution protection needs to be devised so that if there is a corresponding item in the cache, it is returned here and does not go through the address translation device for reading the memory. In the present invention, an example is shown in which the cache memory is separated into an instruction cache and a data cache, but in this example, if an execution protection error occurs, the cache memory is controlled so as not to be intruded.

From the above, it is believed that the method of solving the problems of the present invention in the past has been understood, but the present invention also solves the problems in multiprocessors in a similar manner. In a conventional multiprocessor configuration, when the address translation table is rearranged, a command is sent to other processors to invalidate TLBs owned by other processors.
LB purge). This allows the TLB to be updated even if the previous program remains in cache memory.
By invalidating the cache memory, the corresponding cache memory can be prevented from being used. In a multiprocessor to which the present invention is applied, the problem is that when one processor rewrites the address translation table, the cache memory of another processor no longer matches the main memory. The solution is to transfer from the external memory using a virtual address, monitor this virtual address in the cache memory, and invalidate the corresponding block if it is in the cache memory.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an example of the overall configuration of a data processing apparatus to which the present invention is applied.

In FIG. 1, 10 is a main memory for storing programs and data, and a memory bus 11. It is connected to a common node 50 via a memory controller (MCU) 12.

几 is an external memory that stores programs and data to be stored in the main memory 10, and is connected to an external memory bus 21.
It is connected to a common bus 50 via a file processor (FCP) 22.

30 is an input/output processor (IOP), which controls data transfer with various input/output devices (not shown); 40 is a job processor (JOBP), only one of which is shown here; The life job processor 40 is composed of an instruction character 7-'41 degree data cache 42, an I unit 43, and an H E unit. The units 44 are connected by a bus 46, and ■Units°)[3 and E unit 44
are connected by bus 47.

In this way, file processor 22. The input/output processor 30 and the job processor 40 are both connected to a common bus 50 and can access the main memory 10 via the memory controller 12.

The job processor 4 includes ■ unit 43 and E unit 4
4 performs pipeline processing, and as mentioned above, each unit has an instruction cache 41 and a data cache 44.

The data handled by the program (instruction) is an operan.
This data cache is also called an operand cache.

When the emunit 43 accesses the instruction word to be executed next, it is first checked whether the instruction word exists on the instruction cache 41, and if it exists, ``the data is transferred to the bus as an instruction word. -5 via unit 43
sent to. If it does not exist, the virtual address of the command is sent to the memory controller 12 via the common bus 50.

The memory controller 12 converts the virtual address into a physical address and accesses the main memory 10 via the memory bus 11. The obtained data (commands) are transferred to the common bus 5.
0. It is sent to the instruction cache 41 via the bus 45t, and is further sent to the e-unit 43 via the bus 45t, where it is processed by the unit 43 and at the same time stored in the instruction cache 41 for viewing.

(2) The unit 43 decodes the obtained command and instructs the E unit 44 "what to do." E
Based on this command, the unit 44 collects necessary data from the internal registers and data cache 42 (if it is not on the data cache 42, from the main memory 10 as well as the instruction cache), performs arithmetic processing, and outputs the results. When storing the result in the internal register 10, the data at the corresponding position has already been taken into the data cache 42. Next, an example of the configuration of the common bus 50 will be described.

The common bus 50, as shown in FIG. 2, is an activation bus 55. which is used to actually transfer information. A data bus 56'l response bus 57, and an activation bus occupancy request line 51. which is necessary to determine which processor or memory controller will use each of these buses 55-57. The data bus occupancy request line 52, which includes a response bus occupancy request line 53 and an interlock signal line 54, is used in a time-sharing manner.

The contents of the information on each bus 55 to 57 are as follows.

(1) Start-up bus 55 (a) Address (b) Type of access (for example, read access/write access, and number of access keys (C)) Access key (used for protection and check performed by the MCU 12). ) (2) Data bus 56 (a) Write data (b) Read data (3) Response bus 57 (a) End signal, (b)
These include return code (information about errors and page faults that occurred during access), etc.

FIG. 3 shows how these buses 55-57 are used.

As shown in this figure, 1 (i) a's read request and b's read response (ii)
It is possible to simultaneously transfer three combinations of a read request for a and a write response for d, OiD, a write request for c, and a write response for d in the same time slot.

Next, FIG. 4 shows how the buses 55 to 57 are used. In this figure, JOBP40 is set to MCU12 in time slot 0.
Memory read activation is applied to time slot N, !, and the read data for it is time slot N,! :N+1 was returned and 9,
In the completed time slot 1, the l0P30 activates the memory write to the MCU 12, and a response - is returned in the time slot N+2. In this manner, the common bus 50 performs so-called split transfer in which activation and response are separated. Furthermore, the main memory 10 is configured to be able to process multiple memory accesses.

Before performing the transfer of the buses 55 to 57 described above, it is necessary to perform occupancy control.

This is a method in which the processor or memory controller that wishes to transfer issues occupancy requests 51 to 53 for the bus to be used for transfer one time slot before the transfer, gives priority to these requests, and permits the transfer. is possible, but we will omit the details here. However, a response request for occupancy has a higher priority level than an activation request. This is because if a response cannot be returned due to an occupancy request due to activation, the activation process becomes stuck on the memory controller, resulting in a deadlock state. For example, in the case of this embodiment, if there is a conflict between the data read response b shown in FIG. 3 and the occupancy request caused by the data write activation of C, the former is given priority.

The above occupancy control is shown in a simplified manner in FIG. In time slot O, JOBP40 and l0P30 attempt to perform read activation, and each requests activation bus occupancy request 51.
is being issued. Among these, JOBP40 is l0P3
Assuming that the priority level is higher than 0, JOBP 40 uses the activation bus 55 to activate the read in time slot 1, and at the same time stops the occupancy request. On the other hand, l0P
30 was not allowed to be occupied, so time slot 1
However, the startup bus occupancy request 51 continues to be issued. In slot 1, there is no occupancy request from JOBP 40, so in time slot 2, l0P30 can start reading.

When accessing the main memory 10 by excluding access from another processor, that is, by also interlocking, the startup bus 55 is prevented from being used by other processors.

This is because by occupying the activation bus 55, future activations from other processors are excluded, and for memory activations that are already being processed in the main memory 10, the data bus 56. This is to enable the response bus 57 to be used to return a response. If these responses cannot be returned, the startup process will get stuck on the memory controller 12, resulting in a deadlock situation. circle. z
<, (55°, .7..-3,6 Explanation.A processor that attempts to interlock and access the memory controller 12 receives a startup bus occupancy request 51 as shown in FIG. 6, and starts up. In the time slot for transferring information to the bus 55, an interlock signal 54t' indicating that the startup bus 55 is occupied is generated.This signal prevents startup bus occupancy requests 51 from being accepted from other processors. This is realized, for example, by the circuit shown in FIG. First, if the interlock signal 54 is not output, each of the occupancy requests 51 to 53 is checked by the priority determination circuit 61, and the activation bus occupancy request 51 issued by itself has the highest priority. In this case, the activation bus 5'5 occupancy permission signal 64 is output through the AND gate 62 and the OR gate 63.Therefore, this processor is activated at the next time.
．． Engineering information for 5. Transfer is possible. At this time, if the interlock request signal 65 is output from the processor, the AND gate 68 is raised, the flip-flop 66 is set to J-, and the interlock signal 54 is output. This interlock signal 54 is output until the interlock release signal 67 is issued, and during this time, this processor continues to occupy the startup bus 55. Next, when the interlock signal 54 is issued from another processor, the output of the priority determination circuit 61 is prohibited by the AND gate 62, and the activation bus occupancy permission signal 64 is not output, so that the activation bus 55 cannot be used, and therefore memory cannot be started.

Next, MC0 and MC12 will be explained.

In addition to normal memory access processing, the MCU 12 performs address translation from virtual addresses to physical addresses and checks for growth.

In addition, since they are commonly used between processors and require high throughput, read processing and write processing are performed as shown in FIG.
The process is divided into several stages (1) to (2) or (2) to (2), and multiple accesses can be processed in an overlapping manner as shown in FIG. 8(C).

Figure 9 shows an example of the configuration of ¥CUI 2.
However, in each processing stage shown in FIGS. 8(A) and 8(CB), the following operations are performed.

(A): Operation of the read processing stage ■ The virtual address (VA), access type (FUN), and access key' (AKEY) on the read activation reception activation bus 55 are transferred from the common bus 50 to the common bus reception register 71. It's crowded.

■ Address translation and protection check The address translation device 75 determines whether the page indicated by the virtual address (VA') exists in the main memory 10, and if so, converts it to the physical address (PA). Convert to If there is no such page, it will be a so-called page fault.

Also, at this time there is a grote protection check circuit.

At 76, a determination is made whether the access is authorized.

The address translation device 75 and the programming check circuit 76 will be described in detail later.

The results of these gross protection checks and page fault information are the same as other error information (FUNC'j
and the physical address (PA) in the access register 72.

■ If no error or page fold occurs in the access to the memory read start access register 72, the memory controller 77 writes the memory start 151 to the main memory 10 at the physical address (PA) on the access register 72. Apply
When the main memory 10 receives the activation, it transfers the access type (FUNC) and return code (几C) to the temporary storage register 3.

Also, the access in the access register 72 has already been -
If it indicates the occurrence of ra or hegefut,
Move the previous information to the temporary storage register 3 without activating the memory. ′■ Read data reception and data,
Response bus occupancy request Main memory 10i4 receives read data 154 via memory bus 11, and also receives access type (FUNC)
and return code (几C) to common bus sending register 7.
Move to 4.

On the other hand, a data bus occupancy request 52 is issued to the common bus 50.
and outputs a response bus occupancy request 53.

■ Read data, response bus transfer ■ When the occupation request 52.53 of ■ is accepted, the read data (154) is transferred to the data bus 56 via the bus 155, and the end signal and return = I-)'' (RC ) are transferred to the response bus 57 via the bus 156 and returned to the accessing processor.

(B) Operation of the second write processing stage■'The virtual address (VA) on the write activation reception activation bus 55 from the common bus 50, the access [
Q' (FUNC), access key (AKEY), and write data (WD) on the data bus 56 are taken into the common bus reception register 71.

(2) The same operation as (2) in the read processing stage (A) is performed except for address conversion and setting protection check write data (WD) in the access register 72.

(2) The process is the same as (2) in the read processing stage (4,) except that the memory write activation write data (WD) 153 is transferred to the main memory 10.

■'Response bus occupancy request access type (FUNC) and return code (几C)
is transferred to the common bus sending register 74.

On the other hand, for the common bus 50, the response bus occupancy request 53
Output.

■'Response bus transfer■'When the occupation request 53 is accepted, the end signal and return code (RC) are sent to the response bus 57 via the bus 156.
and return it to the processor from which it was accessed.

As mentioned above, read and write processing is divided into each stage, and different access processing is performed.
The stages numbered □ can be processed in parallel as shown in Figure 8 ('C).
The e-write activation and (c)16 BYte')-de activation are received and processed in time slots 0 and 1.2, respectively.

Looking at the case of time slot 2, (a) memory read activation ■, (b) address translation and protection check ■', and read activation reception from C common buses ■ are performed in parallel. There is. Here, (c) 16
Compared to the 4 BYte read in (a), the Byte read repeats the stages (■) to (■) four times, and this is because memory interleaps are performed in units of 4 B)'te. This will be explained below.

FIG. 10 is a diagram showing an example of the configuration of the main memory 10. The memory boards (MB) 14 (14a to 14d) are configured with a data width of 4 BYte, and each memory board 1
4a, 14b, 14C, 14d, the lower 2 bits of the address added in 4-byte units are 00.01, 10.
I have data that is 11. and 16 BYte
The data is 4 bytes each for the memory boards 14a, 14b, and 14C.

14d, when reading 16 Bytes, there is no conflict on the memory board 14, and the memory board can be activated and the read data can be read out in succession as shown in FIG. 8(C).

Such 16 Bytes + busy data is mainly used for block transfer to send data to the cache memory in the event of a cache miss.

■Unit 43 and E unit 44 are instruction cache 41
or when accessing the data cache 42. is 16
] Unit smaller than 3 byte (in this example, 4 BY
Let it be te. ), so when reading this 16 Byte, the 4 required by E unit 43 and E unit 44 is
By controlling the BYte data to be delivered earlier than the rest of the data, the access time can be changed as shown in FIG. 10 (B). The order of the memory boards 14 to be activated from the MCU 12 can be changed depending on the throat address.

Next, address translation and protection checking will be explained in detail.

FIG. 11 is a block diagram mainly showing the address translation device 75 of FIG. 9 in more detail, and FIG. 12 shows the operation flow of address translation.

Virtual address to physical address translation table 130
is placed in a part of the main memory 10 because of its large memory capacity. But every time a memory access occurs, to convert the virtual address to a physical address,
Since accessing the main memory 10 causes a large overhead, the MCU 12 is provided with a TLBIIO that stores recently accessed address translation information.

TLBIIO includes the address translation table 130,
The contents of recently used pages are stored, allowing high-speed address translation. TLBII
The contents of each page in O are valid pits (V) 111
．． Connect (C) pit 112, the second part of the virtual address (
VPA)113. Part of physical address (PPA) 114
．． (BP) 115 and storage key (8, EY) 116. The v hit 111 and the C pit 112 indicate the current state of the corresponding page, and if the v bit 111 is "0", the T
The content of the corresponding page in LBllo is not valid data (
invalid) and.

When both the v bit 111 and the C pit 112 are "1", this indicates that the corresponding page is currently being transferred between the main memory 10 and the external memory 20, that is, it is being paged; When the v bit 111 is "1" and the C bit 112 is "0", this indicates that the corresponding page is in the main memory 10 and memory access is possible.

The reason why the paging-in-progress state is added in this way is to prevent accesses other than paging access from the FCP 22 to the area where paging is being performed.

In this system, address conversion from virtual address to physical address is performed in 1. In MCU1'2, each process -□
Since this is common to all processors, even accesses that are being paged by the FCP 22 will go through the same address translation device 75, allowing other processors to access the area that is being paged. This will lead to data corruption or loss. Therefore, as mentioned above, both the v bit 111 and the C pit 112 are "
1", the above-mentioned inconvenience is solved by allowing only paging access from the FcP 22.

Next, part of the virtual address (VPA) 113 is the TLBI
When performing address translation in IO, this is to check whether the translation pair of the corresponding virtual address (VA) is registered in TLBIIO. This is for creating a physical address (P A , >) when there is a translation pair in TLBIIO.

Virtual address (VA) is segment address (8A)
121. Page address (PA) 122. It consists of an intra-page address (DISP>123), and the above physical address part (PPA) 114 is an intra-page address CDl5.
Physical address execution protection pit 115 (EP) connected to P) 123 is to prevent erroneous instruction reading and execution for data. If an instruction is read from the area, an execution protection error will occur.

Therefore, as in this configuration example, when the instruction cache 41 and data cache 42 are separated in the JOBP 40, access to this area from the instruction cache 41 is executed in the pot using the protect error storage key (
SKEY) is used to perform write protection, and together with the access key (AKEY) transferred from the requesting processor, the protection check circuit 76 determines whether write access is permitted or prohibited. In the latter case, the write protect error and the access key (AKEY) are 8KEY11 like this.
In addition to being used to check for write protection errors by comparison, it also contains information on whether or not it is a paging access from the ECP22 and information on whether or not it is an instruction read.
Also used for these protection checks.

Next, the conversion process will be sequentially explained with reference to the flowchart of FIG.

Types of memory access can be broadly divided into the following two types.

In other words, (1) Memory access by a general processor (2)
)Memory acquisition during basing with FCP22'x
.

There are two. This distinction between accesses (1) and (2) is transmitted to the address conversion controller 125 via the signal line 140 on the access key AKEY.

First, the address bus for memory access and determination of access permission in the general case (1) will be explained.

A virtual address output from a certain processor (JOBP40 or l0P30) is sent to the MC via the common bus 50.
It is set in the virtual address register 120 in the common bus reception register 71 in U12. The virtual address set in this virtual address register 120 is a segment address (SA) 121 and a page address (PA).
122 part 120-2 as an address, TLB
Access llo. The TLB read by this
IIO entry V pit, bit 111 and C bit 1
12 is communicated to the address translation controller 125,
Depending on the pattern, the subsequent processing is divided into three steps as shown in (1) to (2) below.

This corresponds to step (FO!5) in the flow of FIG.

■ V bit 111-0. When C bit 112=o.

This is shown in FIG. 12 by displaying "0, 0", but as mentioned above, the corresponding page (entry) in TLBIIO is invalid, and the conversion table 130 in main memory 10 is read out. . (FIO) The detailed operation when a TLB miss occurs will be described later.

■ V bit 111=1. C beep) 112=1(7) o'clock.

In FIG. 12, it is time II, IJ0, and at this time, the virtual address part 120-1 and the virtual address part VPA113i of TLBIIO are compared by the comparator 124, and they match, and the TLB hit signal 141 is output. For example (F2O3), since it indicates that the corresponding page is currently being paged, its memory access is prohibited and the missing page fault signal 142 is output from the address translation controller 125. (F45)TL
When the B hit signal 141 is not output, it is a TLB miss, and the conversion table 130 on the main memory 10 is read out in the same manner as in (2). (FIO) ■ v-via) 111
= 1', C beep) 112 = (1) time.

In FIG. 12, at the time of "1.O", the TLB hit signal 141 is checked first, and if it is not output (F2O), the protect error signal 143 from the gross protection/check circuit 76 is checked. , if no error has occurred, the selector 128 concatenates the in-page address field 123 of the virtual address register 120 and the part 114 of the physical address on the TLB 11'o to select the physical address.
, and sends its physical address to memory address bus 152 to access main memory 10.
In order to access the memory controller 77, the memory controller 77 outputs the simulator activation signal 151. (F2O) Next, F of (2)
Memory access during paging by the CP 22 will be explained.

The virtual addresses output from the FCP22 are transferred to the common bus 5.
0 to the virtual address register 12 in the MCU 12
Set to 0.

In this case as well, the TLB 110'f: is first accessed, and the subsequent processing is divided into three parts as before, depending on the V bit 111 of the accessed TLBIIO entry.

■ When ve knot 11=O, C bit 112=0.

Read conversion table 130 in main memory 10 ■ V bit 111 = 1. When bit 112=1.

At this time, the TLB hit signal 141 is checked. (
F30) If it indicates a TLB hit, access the main memory 10 using the physical address created on the access register 72. (F40) If the TLB hit signal is not output, the conversion table 130 in the main memory 10 is read. (FIO) ■ V via) = 1. C vinyl 7to112=0
(7) The TLB hit signal 141 is checked.

(F215) When the TLB hit signal 141 is output, it means that a prohibited area is being accessed, so an error is notified to the FCP' 22. (F220) Next, the process of reading the conversion table 130 on the main memory 10 in the case of a TLB miss will be described.

In order to reduce the memory capacity required for the conversion table 130n, it consists of a page table 132 having information necessary for address conversion and a segment table 131 holding the start address of the page table 132. When a TLB miss occurs, it is set to 1.First, the contents of the register 126 (STOR> that holds the start address of the segment table) and the segment address (SA) 121 of the virtual address register 120 are added to create a physical address, and then the segment The contents of the corresponding position in the table 131 are read onto the read data bus 155. This data holds the start address of the page table 132, and this value and the virtual address register 1200 ) 122 to adder 1
27 to create the address, page table 132
Read the information necessary for conversion from . (, F'I O) In this page table 132: In addition to the M bit, the TL
V pit 111 and virtual address in B110
' Contains emotional voices except for part 113 (VPA),
These M bits and C bits are transferred to the address conversion controller 125 via a portion 155-1 of the read data bus 155.
The following processing is performed based on these bit patterns.

■ When M bit 20 and C bit = 00, it indicates that the corresponding page is not in the main memory 10 but in the external memory 20, and 'missing page fault signal 142 is sent in response to an access request for this page. to notify the relevant processor of the page fault.

(F45) ■ When the M pit is 20 and the C bit = 1, the corresponding bit indicates that paging is currently in progress, so memory access other than FCP22 is prohibited, and the M7 page is disabled. A fault signal 142 is issued. (F45) In case of memory access from FCP22,! Climb to I'LB110 and access, (F20) OM pit=1. Part 155-2 of the read data read when the C bit is 20, part 120-1 of the virtual address, and the V bit "1" are TLB1.
registered in lo, (F20) V, C As mentioned above,
The address translation device 75' can centrally perform address translation from virtual addresses to physical addresses for memory accesses from virtual addresses from each processor, thereby simplifying control of address translation.

In addition, by changing the control method for access from the FCP 22 and access from other processors, it is possible to prohibit access from other processors to the page being paged, which improves data integrity. It becomes possible.

Next, the operation at the time of a missing page fault will be explained.

When a page fault signal is received by the requesting processor, it interrupts the task it is currently executing and activates FCP 22 to load the page containing the requested address into main memory 10. In response to this activation, the FCP 22 reads the corresponding page, and when this is completed, generates an end interrupt. At this time, since the necessary pages have been rolled into the main memory 10, the interrupted task is resumed. While this task is suspended, the processor performs other tasks.

Next, the instruction cache 41 and data cache 42 will be explained. FIG. 13 is a diagram showing an example of the configuration of the instruction cache 41. The data copied from the main memory 1° is located on the data section 81-■, and the addresses of the data are located in the directory 82-I and invalidation directory 83-■, and are these valid? Information indicating whether or not this is the case is in the valid bit register 84-I. The contents of the directory 82-I and the invalidation directory 83-I are the same, but they are separated to improve performance. The former is used to check whether the data accessed by the I unit 43 is in the cache data section 81-I, and the latter is used to check whether the data written to the main memory 10 by another processor is in the cache data section 81-■. If the data has been imported, it is already old and must be invalidated (this is called invalidation processing), but this is used to check for this purpose.

Next, this command character will be explained. Note that the instruction cache 41 is different from the data cache 'L42; write access processing is shown in FIG. 14, which shows the flow when a read access cache miss occurs, and FIG. 15, which shows the invalidation processing flow.

(1) Read access (see Figure 14) ■ When the activation signal 91- is received from the unit 43, the virtual address 92
Part of -■, here bits (18-27), read the contents of directory 82-I and data, and read the contents of directory 82-I and bits (0-17) of virtual address 92-■. The comparator 160-I performs a match check, and the contents are checked by the parity checker 16.
Check with 1-I. Then, if the comparator 160-I indicates a match, no parity error has occurred, and the valid bit register 84-I indicates that it is valid, the cache hit signal 170 is output via the gate 169-I. -I is issued to instruction cache controller 162-I, and instruction cache controller 162-I selects bits (18-29) of the virtual address.
An end signal 93-I is returned to the read data bar unit 43 for the contents of the cache data section 81-I accessed in the above.

(2) In the case of a cache miss, the instruction cache controller 162-I issues an activation bus occupancy request 51.

(2) When the occupancy request 51 is granted, the gate 85-I is opened and the virtual address (VA) is transferred to the startup bus 55.

Access type (FUNC), access key (AKE)
Transfer Y). In addition, this access key (AKEY)
Add that it is an instruction read.

(2) According to the set signal 172-I, the bits (θ to 17) of the virtual address are written to the directory directory 82-2 and the invalidation directory 83-I, and the bit (2) is set. When read data (RD) is sent from this center via the data bus 56, and an end signal and return code (information on errors and page faults that occurred during access) (RC) are sent via the response bus 57. As mentioned in the explanation of the 6MCU12 latched in the register 86-I, the first data sent is the data accessed by the unit 43, so the return code (RC) is one of the following (1) to ( 3), (when condition (a) shown in FIG. 14 (B) is satisfied),
■ End signal 93-I and read data 94 to unit 43
-I and return code 95-work are returned. □(1)
No Error (x −) - when no force is generated) (2) page pault (when a page fault occurs) (3) SOftEr'ror (software error,
For example, if a protection error occurs or if
rd Error (CD caused by hardware, x-ler)
In this case, the patent that features the main memory 10 can often be saved, so a retry is performed. For this reason, the above signal is not returned, but if the number of retries exceeds the specified number, that is, in the case of retry over, the above signal is returned in order to report an error. Then, the read data read from the main memory 10 is written into the cache data section 81-■.

■, ■, ■ Write the remaining read data sent from the MCU 12 to the cache data section 81-I. The end signal 93- has already been sent to the e-unit 43 at stage (3).
Since I is returned, during this time, unit 43 can perform other operations. In addition to this, in stage (2), it is checked whether an error or page fault has occurred in stages (2) to (2), and if no error or page fault has occurred, the operation of the instruction cache 41 is stopped.

■ If an error or page fault has occurred, the valid bit register 84-
The instruction cache controller 162-I outputs a valid bit clear signal 171-I to the instruction cache controller 162-I to clear the valid bit so that the corresponding data in the cache data section 81-H cannot be used. In addition, at stage (2) (if ard has not been overridden (the condition shown in FIG. 14(B)) is satisfied), the process jumps to stage (2) to perform a retry.

The above is the read access processing procedure (2), but in the case of the above-mentioned cache (both instruction and data cache), so-called invalidation processing is required.

The procedure will be explained below.

(2) Invalidation processing (see FIG. 15) ■ The virtual address (VA) and type of access (FUNC) being transferred by the activation bus 55 are taken into the register 87 each time.

■ At the pit (18-27) of the above virtual address, invalidate directory 83. The invalidation determination circuit 165-I reads out the contents of I and checks whether or not it needs to be invalidated.
is set in register 88-■.

(2) If invalidation is required, the corresponding valid pit 84-I is cleared using the address of the register 88-2. For this reason, the invalidation determination circuit 165-I outputs a high bit clear signal 171-I.

Next, cases in which invalidation is necessary will be explained in detail. First, the type of access (FUNC) taken in from the invalidation startup bus 55
) indicates a write access and it is from the other side. Then, invalidation is performed when any of the following conditions is met:

(a) Register 87-I address pit (18
-27) reads the invalidation directory 83-I, and compares its contents with the address pits (0-17) using the co/parator 163-I, and they match.

Φ) When a parity error is detected by the parity checker 164-I when reading the invalidation directory 83-I.

(C) Invalidate directory 83-I to JOBP4
When used indoors. (Because ■ cannot be checked) I have described the invalidation process above, but next (1) Glue-1
, write the address to the invalidation directory 83-I,
The reason why the valid pit register 84-I must be set will be explained.

FIG. 16 shows that when a read access does not result in a cache miss, and there is a conflict between cache invalidation processing when going to read the main memory 10 and when a write access is made from another to the main memory 10, A time chart shows how each part is used. The invalidation process is indicated by diagonal lines, and the startup bus 55. For ≧ite access during data bus 56 transfer, the invalidation directory 83-I is checked in time slots 2 and 4, and the valid bit register 84-■ is cleared in the first half of time slots 3 and 5. It is disabled. On the other hand, if a cache miss occurs, the access to the door transfers the address to the startup bus 55 in time slot 2, so the order of access to the main memory 10 is after the access in time slot 3. This occurs before a write access is made while the startup bus 55 is being transferred. Therefore, in order to keep the data in the cache and main memory 10 consistent, the address of the read access that caused the cache miss must be invalidated between time slots 2 and 4 when the write access checks the invalidation directory 83-I. Between timeslots 3 and 5, the valid bit register 84 must be written to the direct register 83 and also invalidates the check bit 84.
-I needs to be set. These controls are necessary because the main memory 10 processes multiple memory accesses simultaneously.

In this configuration example, the address information is stored in two places, 82-I
Since the invalidation directory 83-I has the invalidation directory 83-I, only the invalidation directory 83-I is subject to the above restrictions, but if the directory is located in one location, the above restrictions naturally apply.

Next, the data cache 42 will be explained.

FIG. 17 is a diagram showing an example of the configuration of the data cache 42, and the invalidation processing circuits 1sa-D are the instruction cache 42.
It is omitted because it is the same as 1.

In addition, in FIG. 13 and FIG. 17, the only difference in suffix is that they are equivalent. The instruction character string shown in FIG. 13 uses the suffix ``■'', and the data cache shown in FIG. 17 uses the suffix D.

In order to shorten this write access time, a common bus sending buffer 89-D is provided, and when writing, a virtual address 92-D is provided.
D. Write data 95-D.

By simply setting the control m-report 96 ffD in this buffer 89-D, the end signal 93-D is controlled like the E unit.

Next, regarding the operation of this data cache 42,
'I'll explain. However, since the read access processing is the same as that of the instruction cache 41, the description thereof will be omitted.

(3) Write access (see Figure 18).

■ When the activation signal 91-D comes from the E unit 44, the virtual address 92-D, write data 95-D, and control information 96-D (access type, access key, etc.) are sent to the common node (for sending out the sofa). 89-D and returns an end signal 93-D to the E unit 44. At this time, check the directory entry 82- and the valid pit register 84-D, and if the cache hit (signal 170-D is output). For example, data is written to the position indicated by the virtual address 18-271 in the cache data section 81.
- ■ Data cache controller 162-D activation bus occupancy request 51. A data node (space occupancy request 52) is issued.

■ When both occupancy requests are granted, open the gate 85-D and transfer the virtual address (VA), access type (FUNC), and access key (AKEY) to the startup bus 55, and write data to the data node 56. Transfer.

(2) When the end signal and return code are sent from the MCU 12 through the entire response bus 57, they are latched into the register 86-D. Then, the return code is checked, and if no error or page fault has occurred, the access is removed from the common bus sending buffer 89-D.1. Finish the process. On the other hand, the condition of ■ shown in FIG. 14(B),
That is, if ard Error occurs and the retry is not over, the process jumps to stage 2 to perform a retry.

■ In cases other than the above, the common bus sending buffer 89
-D address clears the valid pit register 84-D, and also sends the E unit 44 to the address 2-. The reason for reporting the occurrence of a page fault is that, in the case of a protection error, for example, data in the cache data section 81-D, which should not be written, has already been written at stage (3).

It should be noted that the address booted from the data cache 42 to the main memory 10 is also sent from the boot bus 65 to the data cache register 87-D (included in the invalidation processing circuit 180-D); Since this is generated by the data cache controller 162-D, the data cache controller 162-D sends a signal 173- to the JP invalidation processing circuit 180-D to control the data cache controller 162-D so as not to perform invalidation. Since the instruction cache 41 does not perform write access, there is no equivalent to this signal 173-D.

As described in detail above, according to the present invention, there are a plurality of processors, at least one of which has a cache memory that is accessed using a virtual address, and an address translation device is shared by all the processors. Processing equipment realized

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of a data processing device to which the present invention is applied, FIG. 2 is a diagram showing an example of the configuration of the common / Figure 4 shows an example of how the common bus is used; Figure 5 shows how the common bus is controlled; Figure 6 shows the input and tarlock signals. 7 is a diagram showing an example of the configuration of the occupancy control circuit, and FIG. 8 (A) to (,,C)
is a diagram showing an example of the processing flow in the MCU and how multiple accesses are processed by overlapping the MCU, FIG. 9 is a diagram showing an example of the configuration of the MCU, and FIG. 10 (,A
) , , (,13) are memory board configuration examples and 1
Figure 11 shows the order of data return when reading 6 bytes, Figure 11 shows the address translation device using TLB, Figure 12 shows the flow of address translation, and Figure 13 shows the structure of the instruction cache. A diagram showing an example, Figure 14 is an explanatory diagram of the processing flow at the time of read access to the cache, Figure 1
Figure 5 is an explanatory diagram of the processing flow of cache invalidation, No. 16
The figure shows the usage timing of each part of the cache, □Figure 17 shows an example of the configuration of the data cache, and Figure 18 is an explanatory diagram of the write access processing flow. DESCRIPTION OF SYMBOLS 10... Main memory device, 12... Memory access controller, 20... External partial storage device, 22... File processor, 30... Input/output processor, 40...
...Job processor, 41...Instruction cache, 4
2...Data cache, 43...E unit, 4
4...E unit, 50...Common bus, 75...
Address conversion cylinder t (jJ 1- - uvJz
Figure 3 Figure 01 Yo Iriko Figure 6 7747a (Cノ, I, I07. Reet・[=ζYO[=[Kotd d Koroko Shichinohe=]=Here)=]! $tlt Figure (AI Ret?y No. tS Country No. 18 Figure 1 page continued @ Inventor Takeshi Kato Hitachi Omika-cho 5-2-1 Inumika Factory, Hitachi, Ltd. Inventor Tetsuya Kawakami 3-2-1 Saiwai-cho, Hitachi City Hitachi Engineering Co., Ltd. 0 applicants Hitachi Engineering Co., Ltd. 3-2-1 Saiwai-cho, Hitachi City

Claims (1)

[Claims] 1. A main storage device that stores programs and data;
an external storage device that stores programs and data to be stored in the main storage device; at least one job processor that performs memory access using virtual addresses to the main storage device to execute instructions; The above for inputting and outputting programs, programs, and data between storage devices. A file processor that performs memory access to a storage device using a virtual address, and an address conversion device that is connected to the main storage device and is commonly used by each processor and converts a virtual address into a physical address. the job processor has a cache memory accessed by virtual addresses; the cache memory receives virtual addresses when the file processor writes to main storage; A data processing device including, when holding a data block corresponding to a virtual address, invalidation processing means for making the data block unusable. 2. The cache memory includes a data section that holds a copy of a part of the main storage device, and a directory section that holds a temporary address on the main storage device that is stored in the data section.
a validity display section that displays whether the virtual address is valid;
It has a latch register that latches the virtual address sent from the file processor, and a comparison means that compares the virtual address latched in the latch register with the virtual address held in the directory section, and the comparison result is 3. The data processing device according to claim 1, wherein the data processing device clears the valid display section when the valid display section is cleared.3.
2. The data processing device according to claim 1, further comprising means for determining whether or not the physical address exists on the main storage device, and communicating the result of this determination to the processor that has issued the access request. 4. The data processing device according to claim 1, wherein the job processor, file processor, and memory access controller are connected to a common bus. 5. The data processing device according to claim 4, wherein the cache memory is connected to a common bus and receives virtual addresses on the common bus.