JPS5856472A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a preferable high frequency characteristics by forming a structure that bonding pad wiring electrodes are led in addition to an element forming region, thereby reducing parasitic capacity. CONSTITUTION:An insulating layer 2 is formed on the surface of a P type semiconductor substrate 1, an insulating film of the region to becomes an element is selectively removed, and a hole 3 is formed. Then, an N type semiconductor layer 4 is formed by an epitaxial layer. A single crystal layer is formed on the part of the hole 3, and a polycrystalline layer is formed on the film 2. Then, the layer 4 is polished from the surface, the semiconductor layer on the film 2 is removed, and the semiconductor layer is allowed to remain only on the region 4a formed with the hole 3 and hence the element.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor wafer suitable for high frequency applications.

Generally, in the manufacture of semiconductor devices for high frequency applications, the structure of one semiconductor element is fine, and accordingly, fine and highly accurate patterning technology is required. These technologies include electron beam exposure, dry etching, ion ring technology, etc.In the production of semiconductor devices for high frequency applications, not only the above-mentioned fine patterning technology, but also
Techniques to reduce parasitic capacitance, inductance, etc. are also required.

As a conventional technique for reducing parasitic capacitance, for example, there is a method of increasing the thickness of the oxide film under the bonding pad by selective oxidation to reduce the capacitance. However, this method has the disadvantage that it increases the height difference in the substrate, which impairs the patterning accuracy of photoresist, etching, etching, etc. in the manufacture of semiconductor elements having fine structures.

The present invention eliminates the above drawbacks, provides a method for manufacturing a semiconductor device that reduces parasitic capacitance, and has better high frequency characteristics.

The method for manufacturing a semiconductor device of the present invention includes the steps of - forming an insulating Mt on the surface of a conductive type semiconductor substrate; selectively removing at least a portion of the insulating film to expose the surface of the semiconductor substrate; The method includes a step of forming a semiconductor layer of a conductivity type different from that of the semiconductor substrate over the entire surface of the semiconductor substrate, and a step of removing the semiconductor layer in areas other than the regions where the insulating film has been selectively removed.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (81-(C)) is a process sectional view for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), an insulating film 2 is entirely formed on the surface of a P-type semiconductor substrate 10, and an opening 3 is formed by selectively removing the insulating film in a region that will become an element portion.

Next, as shown in FIG. 1(b), a %N type semiconductor layer 4 is formed by an epitaxial method. A single crystal layer is formed in the opening 30 portion, and a polycrystalline layer is formed on the insulating film 2.

Next, as shown in FIG. 1(c), the semiconductor layer 4 is polished from the surface, the semiconductor layer on the insulating film 2 is removed, and the semiconductor layer 4 is polished only in the first opening 3, that is, the region 4a where the element will be formed. leave.

In the above embodiment, the semiconductor substrate is of iP type, but the present invention can be implemented even if the semiconductor substrate is of N type. In this case, the semiconductor layer to be grown is of P type. The semiconductor layer to be grown is of the opposite conductivity type to the substrate.

In the semiconductor wafer obtained according to the present invention, the element region 4a is surrounded by the insulating film 2, so that by arranging bonding pads on this insulating film, parasitic capacitance caused by bond ink hats can be reduced.

FIG. 2 is a cross-sectional view of a junction field effect transistor manufactured using the present invention. An insulating layer 24 is provided on the surface of a semiconductor wafer, and a P-type gate region 6. N-type source region7. N-type drain region8. Source electrode 9. A drain electrode 10 is provided.

In the N-channel junction effect transistor formed in this way, except for the element region 4a [if the structure is such that the bonding butt wiring electrode is placed, the insulating film will be 4 to 5
It can be made as thick as μm, and parasitic capacitance can be reduced.

In addition, unlike normal selective oxidation methods, the manufacturing process does not produce steps large enough to make fine patterning difficult. Therefore, it is possible to use highly accurate fine patterning technology, and semiconductor devices with good high frequency characteristics can be manufactured. is obtained.

As explained above, according to the method for manufacturing a semiconductor device of the present invention, an insulating film is formed before the formation of an epitaxial layer, so unlike the conventional selective oxidation method, the semiconductor device manufacturing method of the present invention can be performed without changing the concentration profile. By making the insulating film thicker, it is possible to reduce parasitic capacitance, enable the use of highly precise micro-turning technology, and achieve the effects of realizing a semiconductor element with good high-frequency characteristics.

[Brief explanation of drawings]

1A to 1C are process cross-sectional views for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a junction field effect transistor manufactured using the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... Insulating plate, 3... Opening, 4... N-type semiconductor layer, 4a-...・Element region, 5...Insulating film, 6...P type gate region, 7...N type source region, 8...N type drain region , 9...
...Source electrode, 10...--Drain electrode.

Claims (1)

[Claims] forming an insulating film on the surface of a semiconductor substrate of one conductivity type;
selectively removing at least a portion of the insulating film to expose the surface of the semiconductor substrate; forming a semiconductor layer of a conductivity type different from that of the semiconductor substrate over the entire surface of the semiconductor substrate; A method for manufacturing a semiconductor device, comprising: removing the semiconductor layer in areas other than the selectively removed regions.