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JPS5856428A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5856428A
JPS5856428A JP56155036A JP15503681A JPS5856428A JP S5856428 A JPS5856428 A JP S5856428A JP 56155036 A JP56155036 A JP 56155036A JP 15503681 A JP15503681 A JP 15503681A JP S5856428 A JPS5856428 A JP S5856428A
Authority
JP
Japan
Prior art keywords
solder
frame
substrate
semiconductor
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56155036A
Other languages
English (en)
Inventor
Yoichiro Nabeshima
鍋島　陽一郎
Shigeaki Nawata
縄田　恵昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56155036A priority Critical patent/JPS5856428A/ja
Publication of JPS5856428A publication Critical patent/JPS5856428A/ja
Pending legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明の半導体装置より詳しくは容器基体への半導体素
子の固着構造に関する。
従来の半導体装置の一例は第１図に示される如き構造を
有する◎同図において、１は金属製の基板（ステム）２
にろう材３にようてろう付けされた半導体素子、４は該
半導体素子１の電極と、基板２にガラス材５により植立
開蓋された外部接続端子６とを接続するリード線、７は
ス密封止用金属キヤ、プである。
このような構造を実現するにあたり、半導体素子１の接
層は、基板２の上にろう材をのせ、その上に半導体素子
１を置き、次に基板２を炉の内に入れ、約３００　（Ｃ
３の温度でろう材を溶融し、次いでステム２を炉から取
り出して冷却することにより行なわれ、しかる後に前記
したワイヤ取り付けなどの作業が行なわれる。
かかる従来の半導体装置においては、基板２のチ、デ取
付は面は、半導体素子ｌの面積に相対的にかなり余裕を
もつた面積になっている。このためこの取付は面に半導
体素子ｌを取付けた場合、半導体素子は一定の場所に定
まらず例えば同図に点線で示す位置に固着されることが
ある。かかる固着状態にあってはリード！４の取付け、
キャップ７の固着等の後の工程に支障をきたす、かかる
工程を人手によってなす場合は、それ相応の手間はかか
るとしてもとにかく半導体素子を収納することはできよ
うが、このことは工程時間の増大、すなわち歩留りの低
下となる。最も重大な問題は、半導体素子が一足の位置
に正しく接着されないとき、工程の自動化を実現し得な
い仁とである。
本発明の目的は上記した従来技術の問題点を解決するｋ
あり、そのために半導体素子が基体上にろう材により固
着され、前記半導体素子の電極が前記基体に植立固着さ
れた外部接続端子に接続されてなる半導体装置において
、前記基体の素子固着部の周囲に前記ろう材と親和性の
低い物質からなる枠体が配設されてなることを特徴とす
る半導体装置が提供される。
以下、本発明の半導体装置の実施例を添付図面を参照し
て説明する。
第２図以下に本発明にかかる半導体装置が示される。こ
れらの図において、第１図に示された部分と同じ部分は
同一符号を付して示す、かかる半導体装置を断面図と平
面図で示す、なお、半導体素子ｌは、１辺が０．５　ｖ
ｍ〜１５　ｍｍ角の大きさ、厚さが２００〜３００（μ
ｍ〕のもので、基板（ステム）２は例えば銅にニッケル
メッキしたものである。
本発明によれば基板２０半導体累子１が接層さるべき位
置の周囲に、ろう材と親和しなｉ例兄はアルミニウムの
薄膜の枠８を数〔μｍ〕の膜厚に図示の如き形状に蒸層
等によりて形匠する・この結果、基板２０表面には、ろ
う材に親和す不面すなわち半導体素子接着位置と、ろう
材に親和しない部分すなわち枠８の部分とが形成される
。ろう材にき半導体素子の寸法に応じて数〔μｍ〕の範
囲内で適宜定める。
枠８の内側寸法は半導体素子の外部輪郭より僅かに大と
し、枠８の幅は、半導体素子の１辺の長さの約２０％！
１度に定める・ 半導体素子１の接着は上記工程で行なわれる。
かかる接着工程にお−て、半導体素子１と基板２との間
忙は配置されたろう材３が加熱により溶融した場合でも
、かかるろう材は枠８の材料と親和しないから、枠８を
超えて外部に流出することがなく、枠８内に留まる。こ
のため該ろう材３の表面張力によって半導体素子ｌはそ
の接層されるべき位置に正確に位置ぎめされる。以後か
くの如く正確に位置ぎめされた状態を保ったｔま冷却し
て固定される。
かくして、以後の工程での例えば給電用のり一トＩ線４
の取り付は作業に訃いて、位置調整作業が簡略化され、
自動化が容易になし得るので、製造時間が大いに短縮さ
れるだけでなく、リード線接続などが設計通りに正しく
なされ得るので、製品の信頼性の向上に寄与するところ
大である。
本発明にかかる半導体装置は、基板２に複数個の半導体
素子が接着されるべき場合に特に効果的である。第４図
を参照すると、３個の半導体素子ｌが同一基板２に接着
され、各半導体素子１は、相互にリード線１４によって
接続されている。なお第４図において、既に図示した部
分と同じ部分は同一符号で示す。
半導体素子１は総合的に小型のものでその各々集積回路
が形成されているのであるから、リード線１４の各半導
体素子への取り付けＫＴｈけるトレランス（許容度）は
きわめて厳しい、かかる実施例において、・同時に溶融
したろう材３はそれぞれ薄膜の枠８内に留まって半導体
素子１の位置を正しく位置ぎめするので、位置ぎめの作
業性に顕著な効果がある。更に、リードｌ！４．１４の
取が付は作業の精度も向上し、複数個の半導体素子の基
板への接着およびそれ以後の工程の自動化が可能になる
。
以上に説明した如く、本発明にかかる半導体装置におい
ては、半導体素子を基板にろう付けによって接着する場
合に、かかる半導体素子が接層されるべき位置を囲んで
、当該ろう材に親和しない材料で薄膜から成る枠を形成
することにより、当該半導体素子の接層が正しい位置に
なされることを可能にし、その結果、かかる半導体素子
の接着および以後の工程を簡略化しそれが自動的になさ
れることを可能にするだけでなく、半導体素子の接着、
リード線の接続などがきわめて正確になされることを可
能和するので、完成された製品の信頼性の向上に寄与す
る。なお、上記の説明においては半導体素子の接着を例
にとったが、本発明の適用範囲はその場合に駆足される
ものでなく、その他の半導体装ｆａｔを基板に接置すべ
き場合にも及ぶ、ま恵、８Ｍされるべき半導体装置の数
も図示され説明された場合に限られるものではなく、よ
り多くの数のものを接！する場合も本発明の範囲に含ま
れる。
【図面の簡単な説明】
第１図は従来の半導体装置の断面図、第２図と第３図と
は本発明にかかる半導体装置の断面図と平面図、第４図
は本発明の他の実施例の平面図である。 １・・・半導体素子、２・一基板（ステム）、３・・・
ろう材、４．１４・・・リード融、５−プラス材、６−
外部接続端子、７・・・キャップ、８−・薄膜の枠・特
許出願人　富士通株式金社 第２図 第３図

Claims (1)

    【特許請求の範囲】
  1. 半導体素子が基体上にろう材により固着され、前記半導
    体素子の電極が前記基体に植立固着された外部接続端子
    に接続されてなる半導体装置において、前記基体の素子
    固着部の周囲に前記ろう材と親和性の低い物質からなる
    枠体が配設されてなることを特徴とする半導体装置。
JP56155036A 1981-09-30 1981-09-30 半導体装置 Pending JPS5856428A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56155036A JPS5856428A (ja) 1981-09-30 1981-09-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56155036A JPS5856428A (ja) 1981-09-30 1981-09-30 半導体装置

Publications (1)

Publication Number Publication Date
JPS5856428A true JPS5856428A (ja) 1983-04-04

Family

ID=15597265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56155036A Pending JPS5856428A (ja) 1981-09-30 1981-09-30 半導体装置

Country Status (1)

Country Link
JP (1) JPS5856428A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205730A (ja) * 1983-05-09 1984-11-21 Mitsubishi Electric Corp 半導体装置の製造方法
US4661835A (en) * 1984-01-17 1987-04-28 Robert Bosch Gmbh Semiconductor structure and method of its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205730A (ja) * 1983-05-09 1984-11-21 Mitsubishi Electric Corp 半導体装置の製造方法
US4661835A (en) * 1984-01-17 1987-04-28 Robert Bosch Gmbh Semiconductor structure and method of its manufacture

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