JPS5856258A - Controller for speed of reproduction - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reproduction speed control device in a signal reproduction device for a recording medium recorded in PCM.

FIG. 1 shows a block diagram of a signal playback speed control system proposed by the present inventors for digital audio discs. 1 in Figure 1 is a high-gauge audio disc, and in order to increase the recording density, the signal is recorded at a constant linear velocity regardless of the position on the inner or outer circumference of the disc.
(Corpt-α, nt L-er Verocity
) method is adopted. Therefore, depending on the read position of the disk, the motor 2. ) 20 rotational speed must be changed. 5. This is a synchronization signal detection and reproduction circuit, which detects the synchronization signal contained in the signal read from the disk and outputs only the synchronization signal pulse.
It is. This part also has the function of generating a pulse at the position where the synchronizing signal should normally be to supplement the missing synchronizing signal (due to scratches on the disc, etc.). In this synchronization signal detection reproducing circuit 3.

There is a limit to the reproduction range of the generated synchronization signal due to the recording modulation method. 1. .

The modulation method shown in FIG. 2 will be explained as an example.

Although details of the modulation method will be omitted, in this method, the reference clock frequency is (62+5Afflz).

As, information is recorded with a pulse width of 5T to 117'.
゜It has been done. Also, the synchronization signals are 117', 117', 11//.

It is defined as a continuous pattern of %J, /l or \l, //, 5sll tt, and is recorded every 588T. Therefore, from among the signals, 5T, 4T, 5T, ・
・10r, 117' signal -1,: It is necessary to count and accurately distinguish with the lock signal, but 10T and 1
In order to distinguish the signal from 17', the 11T signal must be 10
．． It needs to be 5r or more, and needs to be within ±4.5 factors.

Therefore, when the synchronizing signal frequency is other than ±4.5%, the synchronizing signal detection and reproducing circuit 5 becomes unable to identify the synchronizing signal and stops signal reproduction.

6 is a Daisimel type frequency voltage converter (hereinafter referred to as P'-
It is composed of a reference clock signal l·1 generating circuit 12, a counter 11, a reference value 14, a subtraction circuit 16, and a l4 converter 15. The reproduced synchronization signal output from the synchronization signal detection circuit 6 is input as a gate signal to the counter 11 via the '/0 frequency divider 21, and the clock signal 12 is counted to obtain the same 1, period signal cycle]. Detect and use the subtracter 13 to calculate the difference from the reference value.

The D/A converter 15 generates a voltage according to the difference.

and amplify it with amplifier 7 so that it has the required loop gain,
By feeding back the appropriate output pressure of the amplifier 7 to the motor to control the rotational speed, the speed at which signals are read from the disk is kept constant. Note that 5 is a pseudo synchronization signal generation circuit for starting the motor.

As described above, the six synchronizing signal detection and reproducing circuits do not operate unless the synchronizing signal frequency is within ±4.5% of the normal value, and therefore do not output a synchronizing signal at startup. Therefore, the purpose of the pseudo synchronization signal generation circuit 5 is to generate a pseudo synchronization signal to bring the rotational speed close to the normal value until the synchronization signal detection and regeneration circuit 3 starts operating. The switching device or synchronization signal was detected.
The discriminator 22 determines whether or not the process is switched to the α side at startup and to the b side at the time of sizing.

The operation of the pseudo synchronization signal generation circuit 5 will be explained below. As already explained, in this method, the signal is composed of a signal with a pulse width of 31 to 117', and the maximum pulse width is 11/J, East L〃 or Kame Ll, %E// 2 times. A continuous pattern is used as a synchronization signal, and the interval between the synchronization signals is 588T. Therefore, even if the synchronization signal cannot be detected, the maximum pulse width can be detected and determined, and this period can be determined. 5 is an embodiment of this, and 8 is a maximum pulse width detector.

The maximum pulse width detector 8 counts the pulse width using pulses narrower than at least the interval T, and calculates the maximum pulse width within a certain period of time. The arithmetic unit 9 multiplies the value obtained in □8 and predicts the synchronization signal interval. The pulse generator 10 uses the value obtained by the arithmetic unit 9 as a division ratio, counts the pulse width, and divides the frequency of the ratio pulse to generate a pseudo synchronization signal.

The operating principle has been explained above, but when determining the maximum pulse width within one hour, which is constant at startup, if the detection period is short, the maximum pulse width within the detection period (11 in the modulation method shown in Figure 2).
T) may not be entered even once, resulting in a false synchronous signal being generated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reproduction speed control device that can obtain a pseudo synchronization signal output proportional to the signal reproduction speed, regardless of the magnitude of the signal reproduction speed.

For this reason, the present invention sets the detection period for detecting the maximum pulse width to be at least 1°4 wider than the period in which the maximum pulse width is recorded, so as to ensure that the maximum pulse width is detected within the detection period. It's because I did it.

An embodiment of the present invention will be described below with reference to FIGS. 6 and 4. In FIG. 6, the same reference numerals as in FIG. 1 have the same functions. Reference numeral 25 denotes a timer for setting a detection period which receives the output of the reference signal generator 12 as an input. FIG. 4 is a time chart explaining the operation of FIG. 6.

As already explained, when outside the synchronous signal detection range, switch the ↓1° switch 4 to the output side of the pseudo synchronous signal generator 5,
The synchronizing signal period is predicted from the maximum pulse width included in the signal, and is returned to the motor 2 via the F-V converter 6 and amplifier 7 to perform speed control.
1-1 Here, the maximum pulse width detector 8 determines the maximum pulse width within the detection period determined by the timer 25. Since the maximum pulse 11T repeatedly exists in at least a 588T period, if the detection period of the timer 25 is set larger than 588T, the maximum pulse 11T will always occur within the detection interval. .

Large pulse 11T comes in.

FIG. 4 shows the maximum pulse width detection period of 1.0% of the synchronization signal period.
The timing relationship in the case of 5 times is shown. As will be seen from now on, it is possible to detect the width of the 11T Hals regardless of the phase of the synchronizing signal (111 section) and the detection cycle setting pulse, and it is possible to accurately predict the synchronizing signal cycle. - If the signal reproduction speed drops below approximately 1/1.5, the maximum pulse 11T may not fall within the detection period, and in this case, the prediction of the synchronization signal may be incorrect1 ()
There is. However, in reality, the maximum pulse width 117' is included in parts other than the synchronizing signal, and there is no practical problem if the detection cycle setting pulse is set to the timing shown in FIG.

However, in order to operate to reliably bring the playback speed to the target even when the playback speeds are extremely different by 1 and 1, such as when the motor is stopped, the detection cycle setting pulse is set in the following embodiment.

You can set it at the timing of

FIGS. 5 and 6 show an embodiment in which the reproduction speed can be reliably brought to the target reproduction speed from a wide reproduction speed range 1.1.

FIG. 5 is a time chart explaining the operation of this embodiment.

- It is. FIG. 6 shows changes in the maximum and minimum pulse widths when the signal reproduction speed is varied from 1/4 to 4 times.

As shown in Figure 5, the detection period is 4 synchronization signal widths (4X588
T) Set above. In this case, the signal playback speed is 1/4
Until ~~, the maximum pulse width 11T always enters within the detection period, and the synchronization signal period is correctly predicted i11. Playback speed is 1
/4 or less, the maximum pulse width may not fall within the detection period.

However, as shown in Figure 6, the minimum pulse width is also 1.
Since it extends over 2T, the output of the pseudo synchronization signal generation circuit 5 necessarily outputs a signal wider than the regular synchronization 1 signal interval, thereby accelerating the motor 2.

As a result, the number of rotations of the disk becomes high. When the playback speed becomes 1/4 or more of the normal speed, the maximum pulse width is detected as described above and the normal 2.0 speed is detected. .

− The speed is controlled to match the playback speed.

From this, the detection period is calculated by multiplying the ratio of the maximum pulse width and minimum pulse width included in the signal by the synchronization signal synchronization (for example, (
If it is selected to be 1"151-)1588T) or more, it is possible to draw in the target playback speed with respect to the playback speed up to 0-=-.

Therefore, according to the present invention, it is possible to correctly generate a pseudo synchronization signal over a wider range of playback speeds, and it is possible to bring the playback speed to the target playback speed.
1.

[Brief explanation of the drawing]

Figure 1 is a pCM signal readout speed control block diagram, Figure 2 is a block diagram of pCM signal readout speed control.
3 is a block diagram of an embodiment according to the present invention, FIG. 4 is a time chart diagram of the embodiment, and FIG. 5 is a diagram of playback speed versus signal no. , FIG. 6 is a time chart diagram of another embodiment. 1... Disk, 2... Motor, 3... Synchronous signal detection circuit, 4... Switch. - 5... Pseudo synchronous signal generation. circuit, 6...F-V converter, 7... amplifier, 25
...Pulse generator.

Claims (1)

[Claims] 1. A playback speed control device for a recording medium on which digital data including a synchronization signal is recorded, comprising a specific pulse width detector whose detection cycle is wider than the -synchronization signal cycle.