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JPS5851609A - Automatic gain controlling circuit - Google Patents

Automatic gain controlling circuit

Info

Publication number
JPS5851609A
JPS5851609A JP15098881A JP15098881A JPS5851609A JP S5851609 A JPS5851609 A JP S5851609A JP 15098881 A JP15098881 A JP 15098881A JP 15098881 A JP15098881 A JP 15098881A JP S5851609 A JPS5851609 A JP S5851609A
Authority
JP
Japan
Prior art keywords
output
voltage
circuit
level
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15098881A
Other languages
Japanese (ja)
Other versions
JPS6365165B2 (en
Inventor
Masato Tawara
田原 正人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15098881A priority Critical patent/JPS5851609A/en
Publication of JPS5851609A publication Critical patent/JPS5851609A/en
Publication of JPS6365165B2 publication Critical patent/JPS6365165B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3005Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To obtain an automatic gain controlling circuit inexpensively with small size, by providing a logical circuit using an output of an output side detector of the automatic gain controlling circuit and a control voltage of a variable attenuation element as input information. CONSTITUTION:An input signal is outputted from an amplifier 2 coupled with a variable attenuator 1, the output signal is detected at a detector 3 with a time constant, and an output voltage vd is inputted to a control circuit 4 and a logical circuit 6. The voltage vd controls the attenuator 1 via a switch SW5 with an output voltage vo amplifying the voltage vd to control the output of the amplifier 2 to be a constant level. An output of the SW5 is inputted to a comparator CMP7 via a delay circuit 10 of the circuit 6. When the input signal of an AGC circuit is a threshold value or less, the voltage VO inputted to the CMP7 is increased than a voltage vref1, the output of the CMP7 switches the SW5 to a constant voltage va via a gate 9 to constitute the amplifier 2 as a fixed gain. When the input level is increased, the voltage vd is higher, the output of the CMP8 of the circuit 6 switches the SW5 to the circuit 4 via the gate 9 to attain AGC operation.

Description

【発明の詳細な説明】 この発明は信号のレベル変動を抑圧するための自動利得
制御回路の改嵐に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved automatic gain control circuit for suppressing signal level fluctuations.

一般に、マイクロ波通信装置においては高品質伝送を要
求される丸め、フェーディング、機器のドリフト等によ
るレベル変動を抑圧して、レベルを一定に保つ自動利得
制御回路が必要となる。この場合自動利得制御回路の入
力レベルがある規定値以下に減衰すると利得が大幅に増
大し、高レベルの雑音が送出されて回線の品質を劣化さ
せる。
In general, microwave communication equipment requires an automatic gain control circuit that suppresses level fluctuations caused by rounding, fading, equipment drift, etc., which require high quality transmission, and keeps the level constant. In this case, when the input level of the automatic gain control circuit attenuates below a certain specified value, the gain increases significantly and high-level noise is transmitted, degrading the quality of the line.

これを防止するために従来の技術においては、自動利得
制御回路の入力側にて信号のレベルを監視し、そのレベ
ルが規定値以下になると利得を固定利得(lII準利得
)に切替える機能を備えていた。
To prevent this, conventional technology is equipped with a function that monitors the signal level on the input side of the automatic gain control circuit and switches the gain to a fixed gain (III quasi-gain) when the level falls below a specified value. was.

この方法杜本来の自動利得制御回路の他に、入力側で信
号゛レベルを検出するためのる波器、高利得増幅器、検
波器、比較器が必要であり、とOえめに高価かつ構造上
の寸法が大になる欠点があう九。
In addition to the automatic gain control circuit inherent in this method, a wave generator, high gain amplifier, wave detector, and comparator are required to detect the signal level on the input side, and it is expensive and structurally difficult. 9. The disadvantage is that the dimensions of the item are large.

この発明の目的は、従来の自動利得制御回路の入力側の
信号レベルを監視する機能をとり除き。
The purpose of this invention is to eliminate the function of monitoring the signal level on the input side of the conventional automatic gain control circuit.

出力側検波WhO出力と可変減衰素子の制御電圧を入力
情報とする簡単壜論理回路とを付加することKより、安
価かつ小型化した自動利得制御回路を定値以下に減衰し
た場合にその入力信号レベルの監視機能を用いずに、出
力側の情報のみKより固定利得に切替えるようにした自
動利得制御回路を提供することにある。
By adding a simple bottle logic circuit that uses the output-side detection WhoO output and the control voltage of the variable attenuation element as input information, the input signal level of the automatic gain control circuit, which is inexpensive and compact, can be adjusted to the level when the input signal level is attenuated below a fixed value. An object of the present invention is to provide an automatic gain control circuit that switches only information on the output side to a fixed gain from K without using the monitoring function.

この発明によれば、入力信号が可変減衰器を介して増幅
される増幅器と、この増幅器の出力を検波する検波器と
、この検波器の出力電圧を供給し前記可変減衰器の減衰
量を出力信号レベルを一定にするように可変する制御電
圧を出力する制御回路と、この制御回路の出力電圧と所
定値に設定された定電圧と管切替えるスイッチ手段と、
このスイッチ手段の切替出力を前記可変減衰器に接続す
る手段と、前記スイッチ手段の切替出力が所定値以下と
まったときそのスイッチ手段を前記定電圧に切替え前記
検波器の出力電圧が所定値以上になったときそのスイッ
チ手段を前記制御回路の出力に切替える論理回路とを含
む自動利得制御回路が得られる。
According to this invention, there is provided an amplifier for amplifying an input signal via a variable attenuator, a detector for detecting the output of the amplifier, and a detector for supplying the output voltage of the detector and outputting the amount of attenuation of the variable attenuator. a control circuit that outputs a variable control voltage to keep the signal level constant; a switch that switches between the output voltage of the control circuit and a constant voltage set to a predetermined value;
means for connecting the switching output of the switching means to the variable attenuator; and when the switching output of the switching means remains below a predetermined value, the switching means is switched to the constant voltage until the output voltage of the detector reaches a predetermined value or higher. and a logic circuit for switching the switch means to the output of the control circuit when the gain is reached.

以下図面によりこの発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.

第1図はこの発明の実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the invention.

入力端子間に接続され電圧又は電流制御による可変抵抗
素子からなる減衰器1と、この減衰器1に接続され出力
をその出力端子にとり出す固定利得増幅器2と、その出
力端にて分岐接続され信号レベルを検出する時定数丁の
検波Wh3と、この検波電圧Vdt−人力して反転し前
記減衰器1を制御する丸めの制御回路4と、この制御回
路4の出力に接続され前記減衰器1および増幅器2を固
定利得又は自動利得制御に切替えるためのスイッチ5と
An attenuator 1 connected between input terminals and consisting of a variable resistance element controlled by voltage or current; a fixed gain amplifier 2 connected to this attenuator 1 and taking out the output to its output terminal; and a branch connection at the output terminal to output a signal. A detection voltage Wh3 with a time constant of 1 to detect the level, a rounded control circuit 4 which manually inverts the detected voltage Vdt and controls the attenuator 1, and a control circuit 4 connected to the output of the control circuit 4 and connected to the attenuator 1 and and a switch 5 for switching the amplifier 2 to fixed gain or automatic gain control.

前記制御回路4の出力電圧Voと検波器3の検波電圧v
dt−人力とする論理回路6とを含み構成される。この
論理回路6はコンパレータ7.8.!:。
The output voltage Vo of the control circuit 4 and the detected voltage v of the detector 3
dt-human-powered logic circuit 6. This logic circuit 6 includes comparators 7.8. ! :.

アンドゲート9と、(τ+α)の遅延回路11とを含ん
でいる。
It includes an AND gate 9 and a (τ+α) delay circuit 11.

次に論理回路6を第2図から第4図の特性図を用いて説
明する。
Next, the logic circuit 6 will be explained using the characteristic diagrams shown in FIGS. 2 to 4.

第2図は制御回路40制御電圧Voと、減衰器1および
増幅a2とからなる増幅回路の利得との関係を示す特性
図であLvaはこの増幅回路を固定利得Kを与える電圧
であp、Vreflはこの増幅回路の信号入力レベルが
あるしきい値M以下になったときこの固定利得Kに切換
える直前の利得人を与える電圧である。    − 第3図(麿)はこの増幅回路の入力レベルと検波器3の
検波電圧Vdとの関係を示す特性図である。
FIG. 2 is a characteristic diagram showing the relationship between the control voltage Vo of the control circuit 40 and the gain of the amplifier circuit consisting of the attenuator 1 and the amplifier a2. Lva is the voltage that gives the amplifier circuit a fixed gain K, p, Vrefl is a voltage that gives the gain value immediately before switching to the fixed gain K when the signal input level of this amplifier circuit becomes below a certain threshold value M. - FIG. 3 is a characteristic diagram showing the relationship between the input level of this amplifier circuit and the detected voltage Vd of the detector 3.

自動利得制御となっている間は出力レベル、すなわち検
波電圧Vdがほぼ一定の電圧vb゛の特性線りとなって
いるが、固定利得KO場合には入力レベルに対応して検
波電圧Vdの変る特性線Cとなっている。ここでVre
f2は入力レベル(M+H)となったとき固定利得Kか
ら自動利得制御に切替える電圧を示□す、但し、Hは切
替時のヒステリシスを示す。
While automatic gain control is in effect, the output level, that is, the detected voltage Vd, follows a nearly constant voltage vb' characteristic line, but in the case of fixed gain KO, the detected voltage Vd changes in response to the input level. Characteristic line C is shown. Here Vre
f2 indicates a voltage at which the fixed gain K is switched to automatic gain control when the input level (M+H) is reached; however, H indicates hysteresis at the time of switching.

第4図(a)はこの増幅回路の入力レベルと制御電圧v
Oとの関係を示す特性図である。自動利得制御の動作時
は、特性IIEに示すように、入力レベルが高くなると
制御電圧vOを少くして減衰器1の減衰量を多くシ、入
力レベルが低くなると制御電圧Voを大きくして減衰器
2の減衰量を少くし、出力レベルが一定とまるように制
御している。この自動利得制御回路の入力レベルがしき
い値Mよシ小さくなると、制御電圧VoはVreflよ
シ大*<なp、コンパレータ7の出力はローレヘルトが
る。この結果アンドゲート9の出力はローレベルとなシ
、スイッチ5f:Va側に切替えて、この増幅回路の利
得を固定利得にとする。この固定利得への切替により制
御電圧は瞬間的にVaとなるが、検波Ws3の時定数τ
より大きい時定数τ+α(αはタイムマージン)の遅延
回路10を通っているので、コンパレータ7には(τ+
α)時間遅れてVaが供給されハイレベルに駆動される
。したからで、入力レベルが低下している時はコンバレ
ータフの出力は、第4図(b)に示すように、ノ1イレ
ベルが瞬時ローレベルとなる信号を出力する。
Figure 4(a) shows the input level and control voltage v of this amplifier circuit.
FIG. 2 is a characteristic diagram showing the relationship with O. During automatic gain control operation, as shown in characteristic IIE, when the input level increases, the control voltage vO is decreased to increase the amount of attenuation of the attenuator 1, and when the input level is low, the control voltage Vo is increased to increase the attenuation amount. The amount of attenuation of the device 2 is reduced, and the output level is controlled to remain constant. When the input level of this automatic gain control circuit becomes smaller than the threshold value M, the control voltage Vo becomes larger than Vrefl*<p, and the output of the comparator 7 becomes lower. As a result, the output of the AND gate 9 becomes low level, and the switch 5f is switched to the Va side to set the gain of this amplifier circuit to a fixed gain. Due to this switching to the fixed gain, the control voltage momentarily becomes Va, but the time constant τ of the detection Ws3
Since it passes through the delay circuit 10 with a larger time constant τ+α (α is the time margin), the comparator 7 has (τ+α).
α) Va is supplied with a time delay and driven to high level. Therefore, when the input level is decreasing, the output of the converter tough outputs a signal in which the NO 1 level momentarily becomes the LOW level, as shown in FIG. 4(b).

一方、コンパレータ8はスイッチ5により自動利得制御
から固定利得に切替られた瞬間に検波器3の出力電圧V
dがVref2以下となりコンパレータ80出力をsr
s図(b) Ic示すようにローレベルとしているので
、ゲート9の出力はローレベルを維持している。したが
って、コンバレータフの出力が瞬間的にローレベルにな
りたことによシスイッチ5は■1側を保持することにな
る。
On the other hand, the comparator 8 detects the output voltage V of the detector 3 at the moment when the switch 5 switches from automatic gain control to fixed gain.
When d becomes less than Vref2, the comparator 80 output becomes sr
Since the output of the gate 9 is kept at a low level as shown in FIG. s (b) Ic, the output of the gate 9 maintains a low level. Therefore, since the output of the converter tough becomes low level momentarily, the switch 5 is held at the 1 side.

次に、入力レベルが低レベルから高レベルに上りて、そ
の入力レベルがM+Hより大きくなるとコンパレータ8
の出力が、第3図(C)に示すようにハイレベルとなる
。一方、コンパレータ7の出力は、第4図(C)に示す
ようにハイレベルを維持しているので、コンパレータ8
の出力がハイレベルとなった時、ゲート90出力がハイ
レベルとなりてスイッチ5が制御回路4の出力Voに切
替接続され、この回路は自動利得制御に切替られる。
Next, when the input level rises from low level to high level and becomes greater than M+H, comparator 8
The output becomes high level as shown in FIG. 3(C). On the other hand, since the output of comparator 7 maintains a high level as shown in FIG. 4(C), comparator 8
When the output of the gate 90 becomes high level, the switch 5 is switched to the output Vo of the control circuit 4, and this circuit is switched to automatic gain control.

以上説明したように、自動利得制御回路の入力側に特別
に信号レベル管監視する機能をもつことなく、簡単な論
理回路を付加することによシ安価かつ小型化され、固定
利得に切替える機能を有する自動利得制御回路が実現で
きる。
As explained above, by adding a simple logic circuit to the input side of the automatic gain control circuit without having a special signal level tube monitoring function, it can be made inexpensive and compact, and the function of switching to a fixed gain can be achieved. An automatic gain control circuit can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の回路図、第2図は制御回路出
力電圧と増幅器の利得の関係を示す特性図、第3図(a
)は信号入力レベルと検波器の検波電圧との関係を示す
特性図、第3図(b) 、 (C)は入力レベルを低下
および上昇させるときのコンバレータフの出力レベル図
%第4図(a)は信号入力レベルと制御電圧との関係を
示す特性図sHa図(b) 、 (C)は入力レベルを
低下および上昇させる時のコンパレタ7の出力レベル図
である。図において1・・・・・・減衰器、2・・・・
・・増幅器、3・・・・・・検波器。 4・・・・・・制御回路、5・・・・・・スイッチ、6
・・・・・・論理回L7,8・・・・・・コンパレータ
、9・・・・・・アンドゲート、10・・・・・・遅延
回路、 第 f 図 制 樗 第2図 +(/1 第3図      第4図
Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a characteristic diagram showing the relationship between control circuit output voltage and amplifier gain, and Figure 3 (a
) is a characteristic diagram showing the relationship between the signal input level and the detected voltage of the detector, and Figures 3(b) and (C) are converter tough output level diagrams when decreasing and increasing the input level.Figure 4(a) ) is a characteristic diagram sHa showing the relationship between the signal input level and the control voltage, and (C) is an output level diagram of the comparator 7 when lowering and increasing the input level. In the figure, 1...attenuator, 2...
...Amplifier, 3...Detector. 4...Control circuit, 5...Switch, 6
......Logic circuit L7, 8...Comparator, 9...And gate, 10...Delay circuit, f Fig. 2 + (/ 1 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 入力信号が可変減衰器を介して増幅される増幅器と、こ
の増幅sO出力を検波する検波器と、この検波器の出力
電圧を供給し前記可変減衰器の減衰量を出力信号レベル
を一定にするように可変する制御電圧を出力する制御回
路と、この制御回路の出力電圧と所定値に設定された定
電圧とを切替えるスイッチ手段と、このスイッチ手段の
切替出力を前記可変減衰器に接続する手段と、前記スイ
、千手段の出力電圧が所定値以下とな、−)たときその
スイッチ手段を前記定電圧に切替え前記検波器の出力電
圧が所定値以上になったときそのスイッチ手段を前記制
御回路の出力に切替える論理回路とを含み、1Ill記
増幅器の出力によシ固定利得制御と自動利得制御とを切
替えることを特徴とする自動利得制御回路。
an amplifier to which an input signal is amplified via a variable attenuator; a detector to detect the amplified sO output; and an output voltage of the detector to supply the attenuation amount of the variable attenuator to a constant output signal level. a control circuit that outputs a variable control voltage, a switch means that switches between the output voltage of the control circuit and a constant voltage set to a predetermined value, and means that connects the switching output of the switch means to the variable attenuator. Then, when the output voltage of the 1,000 means is below a predetermined value, the switch means is switched to the constant voltage, and when the output voltage of the detector becomes equal to or higher than the predetermined value, the switch means is controlled as described above. 1. An automatic gain control circuit, comprising: a logic circuit for switching between fixed gain control and automatic gain control based on the output of the amplifier.
JP15098881A 1981-09-24 1981-09-24 Automatic gain controlling circuit Granted JPS5851609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15098881A JPS5851609A (en) 1981-09-24 1981-09-24 Automatic gain controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15098881A JPS5851609A (en) 1981-09-24 1981-09-24 Automatic gain controlling circuit

Publications (2)

Publication Number Publication Date
JPS5851609A true JPS5851609A (en) 1983-03-26
JPS6365165B2 JPS6365165B2 (en) 1988-12-14

Family

ID=15508824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15098881A Granted JPS5851609A (en) 1981-09-24 1981-09-24 Automatic gain controlling circuit

Country Status (1)

Country Link
JP (1) JPS5851609A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304947A (en) * 1992-03-17 1994-04-19 Ericsson Ge Mobile Communications, Inc. Arrangement for eliminating offset errors in a power control circuit of a pulsed transmitter final amplifier
US7193476B2 (en) 2003-10-15 2007-03-20 Nec Electronics Corporation Integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085259A (en) * 1973-11-28 1975-07-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5085259A (en) * 1973-11-28 1975-07-09

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304947A (en) * 1992-03-17 1994-04-19 Ericsson Ge Mobile Communications, Inc. Arrangement for eliminating offset errors in a power control circuit of a pulsed transmitter final amplifier
US7193476B2 (en) 2003-10-15 2007-03-20 Nec Electronics Corporation Integrated circuit

Also Published As

Publication number Publication date
JPS6365165B2 (en) 1988-12-14

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