JPS5850053A - Controlling system for history memory - Google Patents

Abstract

PURPOSE:To change contents of a history memory and to analyze a trouble effectively, by monitoring the time from a request signal to a response signal, and stopping updating of the history when this time attains a time required for accessing the prescribed number of addresses out o all addresses of the history memory. CONSTITUTION:A control signal CS is fetched in successively by a register R1 to generate history write data HWD to a history memory HM having addresses. A write address for this data is generated from a history address register R2 and is updates in every cycle time gamma or its m-fold time by adding +1 to contents to generate a history white address HA. A counter CTR which counts the half of the number of all addresses of the memory HM and a hang stop latch RT are provided in a history hang stop controlling circuit CNT1. The counting is stopped when a response signal RES comes during counting, and a stop signal S2 is transmitted to an update controlling circuit CNT2 when the counting is overhung before coming of the signal RES.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a history memory O write control system for control signals.

The control signal history memory is an effective function for debugging when a failure occurs, but when a failure occurs and the history memory is read out, it may be that all the contents are the same control signals. That is, as is well known, the combiator beam p
When a memory access request is issued in cycle 0, the access request is kept raised until a response is received.For example, when a response is received in cycle 2, the read address is sent in the next cycle. The procedure is as follows: leave it at 't~ until the read data arrives. The specified control signal is written to the history memory for each PTS, so if there is no response for a long time, the memory capacity is limited and when it becomes full, the old one will be deleted. The contents of the history recorder 49, which adopts a method of writing a new one there, are only control signals to which no response is returned.

Waiting for a response signal to a request signal to another device,
It is said that he received a knock when there was no response after the allowed time had elapsed. In such a hang state, the history memory is over 70
- Stores only the left signal that caused the hang, which is of no use in troubleshooting.Analysis of trouble requires the history before and after the request signal that caused the hang.

In other words, although it is said that the hang occurs suddenly, there are many cases where something goes wrong a few steps before that, and this is a remote cause that leads to the hang, but this is what caused the hang condition; I can't understand the situation. The present invention seeks to provide a history memory write control method that can provide useful information when a device hangs.

Combination data systems generally have a function to stop updating the history memory at that point when a hard error is detected. The same applies when a hang error is detected, but in the conventional method, the error detection and history update stop are too slow, and when it stops, the memory contents tend to contain only the same data.Therefore, in the present invention, when a request signal is issued, a response is sent. It monitors when the signal returns, and stops updating the history if the response signal is unsafe even after all of the history memory has been accessed. Quantitatively speaking, the cycle time of the memory is τ, the capacity of the history memory is N addresses, t,
If half of the memory is filled with the same data, the history update will stop, and if the control signal is stored in the history memory every 1τ, then the history update will stop after τ/2 after the request signal is issued, or Assuming that the control signal is stored in the history memory,
After whNτ/2.

If a response signal is returned after the history update is stopped after the above-mentioned time has elapsed and it is not a hang error, it is necessary to restart the history update. If there is a response signal, this restart can be performed by clearing the hardware or microprogram function that has stopped the history update.

If the response signal is delayed and the history update is stopped or restarted, the history stored data will be discontinuous at that point, so it is a good idea to add a bit indicating this, such as the history update stop signal itself, to the history memory stored data. 1
Next, the present invention will be explained in more detail with reference to the drawings and tables.

In FIG. 1, HM is a history memory with N addresses; 8.
The control signal CB is sequentially incorporated in the register, and this becomes the history write data HWD for the memory HM. The write address is generated by the history address register. This updates the contents by +1 every cycle time τ or once every cycle time τ, and outputs the history write address ■. CN'rl is a history hang stop control circuit and includes a counter CTB and a hang stop latch RT that can count up to half of the number N of addresses in the HMD@address. In the case of N=256, the number of bits of the counter is 7, which is 1 less than the number of bits of Lugistar.This counter CTR starts counting after being cleared when the request signal RIQ is generated, and counts up together with the register. Then, when the response signal RIB comes during counting, counting is stopped, and when the response signal RIB is overturned before the response signal arrives, the solder stop latch R is set to @1# and a stop signal is sent to the history update control circuit CWT. .

Control circuit commercial? , is the history count up signal 8, (
This outputs a clock that is generated every τ or 1τ, and is a signal that controls clock counting, etc., and counts are performed using the history address register and the color signal 81. , stop signal 8
．． When input, the control circuit CNT.

is signal 1. and sends a history update stop signal B4 to the memory HM. Therefore register and counter c
Counting of ti is stopped, and writing to memory HM is stopped.

The stop signal 84 is a control signal that turns to K so that the write enable (WE) signal is no longer sent to the memory.If the write control signal sent to the memory write circuit is at L level to enable writing, the signal 84 becomes R level. , if this is input to the OR gate along with WE, the output of the gate becomes H when 84 arrives.
It is fixed at the level and cannot be written to.

If it is a hang error, after the hissing update stops as described above, a timeout error is issued by a separately provided time monitoring circuit, and the ambiator stops operating. Therefore, the operator should set the address slightly before the address indicated by the register at the time of hiss F update stop (if the same data is N/2
If you read the history memory HM from an address that is probably stuck and check the stored data, you can get an idea of where the failure occurred. In this example, the history update stop occurs at half of the total number of addresses, so in the remaining half, N72 control signals preceding the control signal that caused the hang error must remain unerased. However, it is not the case that all of these have been replaced by the contomir signal that caused the hang error.

If the history update is stopped after the time required for N/2 address access has elapsed, but there is a response signal RIS thereafter, it is not a hang error, and therefore the time monitoring circuit does not generate a time-out signal and the combination controller continues to operate. Therefore, in this case, unless the history update is restarted immediately, when a true error occurs, it will not be possible to investigate the cause.This is the above-mentioned history update restart, which is carried out as follows. That is, when the response signal RE8 is input to the control circuit CNT1, the hangstop latch is cleared (ie, becomes @O'), and when the stop signal 8m disappears, the republic restart signal 8. occurs. With this, the sand signal 84 can be written.
When the L level changes, a signal 81 is generated again and the register starts counting. Figure 2 shows counter C and latch B.
This is a diagram illustrating the relationship between input and output signals of T, and the operation is as described above. The above is a case where hardware called a hang stop latch is provided, but this can also be processed by software. In this case, an interrupt signal 81 to the microprogram is raised, and in response to this, the microprogram stops counting and disables writing as described above, and sends a response signal R 81.
If it enters, send a hangstop clear signal S and count.
Forces writing to be resumed.

When history updates are stopped and then resumed,
The data in the history memory HM is discontinuous because the data from stop to restart is missing. When I read the information to check the cause of the failure (for example, when I resumed updating the history after receiving a response, it soon returned to a hang state), I found that I could not find the cause of the failure or that I had made a mistake. There is a risk of making a judgment. The fact that the history update stopped at that point is a historical record.
To explain using Figure 3, when the request signal RIQ rises at time t, the counter CT of the control circuit CN'r
R starts counting after clearing and reaches time 1. response signal R1e8
If there is, counting stops (8P).

Overflow occurs in this relation and e%/% is normal and 1
When no response is received and an overflow occurs, the latch BT is set, and the output of the latch BT causes the register to stop counting and the history update to stop. After that, response signal 11 [1]
, When the latch ET is reset, the register & starts counting and the history update is restarted.However, the history update stop signal 84#i is introduced into 1 bit of the write register R1, and the history update is resumed. The signal 84 at the KH level @1# is written to the history memory KM together with the control signal at the time. Therefore, when the update is restarted, @1' is attached only to the control signal that has been input to Kll, and other control signals are Since the relevant part of the signal is Fi@o'', this is k
This eliminates the fear that stopping and restarting the history update will lead to misunderstandings and misjudgments.

Iris 4111! HIS) RIME 4: To explain the contents of the HM, (&) indicates the state when the history update is stopped, and 佽) indicates the state after the update is resumed. Bit 111 is a bit indicating that the above-mentioned update is stopped.

In a combinator system, once a request is raised, the next request waits until a response is received.
A method is adopted in which the nine K that receive a response perform the following processing. Therefore, it is common that there are multiple request signals waiting for a response.
For each of them, the history memory is 0/<70-1
．． However, it is uneconomical to provide a counter that can count the number of addresses in the history for each request. To solve this problem, a counter that can count, for example, 178 of all addresses in the history memory is provided in common, and a 2-bit counter is provided for each request signal to count the overflow signal of the common counter.When this counter overflows, a hang stop is performed. The following method is effective. If N=256 and the number of bits of the common counter is 5, this will be explained with reference to FIG. If it's all gone, the plan will stop, but that's fine)
Overflows every 32 address counts, and each request signal RI
Q> - 2-bit counter CTR for RIeQt.

CTB is cleared when the request signal rises, and then counts the overflow pulses of the common counter CTR. ii over 70- to set the hang stop latch BT and stop the history update.

Request signal R] CQt rises next to RIQ, K, counter CTR is cleared, and counting starts, but common counter C?
After counting only 2 overflow pulses of R, a response signal RgB was generated and counting was stopped. Response signal n EQ s
A response signal to K, itgs, was then generated, which reset the three latches and resumed history updating. ') This is not a real hang -) As an example, if a common counter CTB and counters CT1m, CTB, -... for each request signal are provided, the time until the history update is stopped is The number of addresses is approximately 96 to 12 depending on the count value of the common counter at the time the request signal goes up.
Although it fluctuates within a range of 8, it has the advantage of being able to monitor the time for each request signal and reducing the counter capacity used.The details of the signal to be taken into the O Histology Memory 1M are as follows:
a) Including not only the left signal but also the machine status table,
These are various signals necessary for failure analysis. Further, when the request signals are raised one after another, each of them is taken into the history memory while the request signals are raised continuously.

Therefore, if the data written to one address of the history memory HM is one word, the length of one word O bits is quite long, about 40 to 60 bits.

The fact that there are not many response signals and the contents of the history memory are only the blaming request signal is only about the current request signal; the history data for other request signals is
If it's normal, it's changing gradually.

Another possible method is to not write the same data multiple times to the history memory. Even if this is done, only the same data is written to the history memory, which can be avoided if the content Fi is only the data, but for this purpose, it is necessary to compare the write data for each channel. Furthermore, since the data of the other normal control signal system is updated sequentially, it becomes impossible to synchronize, so to speak. Failures are often interconnected, and therefore, in order to investigate the cause of the failure, it is important to check not only the control signal system that caused the failure, but also data from other systems. It makes sense to stop the entire history update at the point where it is delayed.

As described above in detail, according to the present invention, when a hang error occurs, the history memory does not contain only the same data, and data useful for failure analysis can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 and FIG. 4 are partial block diagrams of FIG. 1, and FIGS. 5 and 5 are time charts for explaining the operation. In the drawing, HM indicates history memory, CTR1d counter, [
! 4 is a history update stop signal. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) Combination mode - In a history memory control method in which control signals are sequentially written in synchronization with voice music PTS, the time from when a request signal is generated by counting each of the above until a response signal is received. A counter is installed to monitor the
A control method for a history memory, characterized in that the history update is stopped when the count value of the counter reaches 4 at a time when a predetermined number within the total number of addresses of the history memory is accessed. Q) A counter that counts the number of p's and is common to each request signal, and a counter that is over 7o-. A control system for a history memory according to claims 8 to 11, characterized in that the control system comprises a counter that counts pulses and is dedicated to each request signal.