JPS5848952A - Lead frame for integrated circuit - Google Patents
Lead frame for integrated circuitInfo
- Publication number
- JPS5848952A JPS5848952A JP56148333A JP14833381A JPS5848952A JP S5848952 A JPS5848952 A JP S5848952A JP 56148333 A JP56148333 A JP 56148333A JP 14833381 A JP14833381 A JP 14833381A JP S5848952 A JPS5848952 A JP S5848952A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- glass
- sealing
- coated
- melting point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims description 25
- 238000007789 sealing Methods 0.000 claims description 19
- 238000002844 melting Methods 0.000 claims description 15
- 230000008018 melting Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000000956 alloy Substances 0.000 description 8
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000002241 glass-ceramic Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000011247 coating layer Substances 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000004453 electron probe microanalysis Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000005394 sealing glass Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は低融点ガラス封止型ＩＣ用リードフレームに関
するものであり、リードフレームと封止用ガラスとの界
面の接合性を改善し、ＩＣの信頼性を向上することが可
能なＩＣ用リードフレームを提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame for a low-melting glass-sealed IC, which improves the bonding properties of the interface between the lead frame and the sealing glass, and improves the reliability of the IC. The present invention provides an IC lead frame that is capable of
ＩＣのうち高信頼性を必要とするものには、多層セラミ
ックパッケージや低融点ガラスセラミック′９ツケージ
法が従来から用いられており、特に前者は極めて高い信
頼性を有するがパッケージコストが高いのが欠点である
。そのため後者の低融点ガラス・セラミックパッケージ
の信頼性向上が重要な課題となっている。For ICs that require high reliability, multilayer ceramic packages and low-melting glass ceramic packages have traditionally been used.The former has extremely high reliability, but the packaging cost is high. This is a drawback. Therefore, improving the reliability of the latter low-melting-point glass-ceramic package has become an important issue.
現在、この低融点ガラスセラミックパッケージ用に用い
られているリードフレームであるアルミストライプ４２
７０イ （４２％Ｎｉ−Ｆｅ合金）では、４２アロイ表
面に低温酸化皮膜を形成した後でガラス封止を行ってい
るが、この酸化皮膜とベースメタルとの密着性が不安定
であったり、封止後のアウターリード部への半田付性が
劣化するなどの問題があってなかなか信頼性を向上する
ことができなかった。Aluminum stripe 42, which is the lead frame currently used for this low melting point glass ceramic package.
For 70i (42% Ni-Fe alloy), glass sealing is performed after forming a low-temperature oxide film on the surface of 42 alloy, but the adhesion between this oxide film and the base metal is unstable, It has been difficult to improve reliability due to problems such as poor solderability to the outer lead portion after sealing.
一方、近年ｒｃチップの大型化が進む一方で、高密度実
装に対する要求もますます増大しつつある。このことは
必然的にガラス封止部の長さが減少することとなり、封
着特性の改善は高信頼性化とあわせて大きな問題となり
つつある。On the other hand, as rc chips have become larger in size in recent years, demands for high-density packaging are also increasing. This inevitably results in a reduction in the length of the glass sealing portion, and improvement of sealing characteristics is becoming a major issue along with the need for higher reliability.
本発明は以上の問題点、を解消し、従来の低融点ガラス
封止用リードフレームのガラス封止特性（従って信頼性
）の向上が可能なＩＣリードフレームを提供せんとする
ものである。The present invention aims to solve the above problems and provide an IC lead frame that can improve the glass sealing characteristics (and thus the reliability) of conventional low-melting point glass sealing lead frames.
第１図は従来広く用いられているアルミストライプ４２
アロイテープｌの外観図の一部であり、２が４２アロイ
テープ基板、３は被覆Ａ１層である。第２図はこのテー
プを打抜き加工により、リードフレームとしたものを用
いた低融点ガラス封止用ｒｃの断面構造を示したもので
４，４ｔがパッケージ用セラミック、５が封止用低融点
ガラス、７はボンディングワイヤーである。この従来の
パッケージの構造では、リードフレームの４２アロイ部
が低融点ガラスに直接接触するが、その接着性能は良好
でなく、長時間にわたる高温多湿試験により、４２アロ
イ／低融点ガラスの界面より水分や汚染物質がパッケー
ジ内部に浸入し、ＩＣチップ６の特性を劣化させること
が多い。Figure 1 shows the conventionally widely used aluminum stripe 42.
This is a part of the external view of the alloy tape 1, where 2 is the 42 alloy tape substrate and 3 is the coating A1 layer. Figure 2 shows the cross-sectional structure of an RC for sealing low melting point glass using this tape as a lead frame by punching. 4.4t is the ceramic for the package, and 5 is the low melting point glass for sealing. , 7 are bonding wires. In this conventional package structure, the 42 alloy part of the lead frame comes into direct contact with the low melting point glass, but its adhesion performance is not good, and long-term high temperature and high humidity tests have shown that moisture increases from the interface between the 42 alloy and the low melting point glass. In many cases, contaminants and contaminants enter the inside of the package and deteriorate the characteristics of the IC chip 6.
第３図は本発明のリードフレームの実施例の外観図であ
り、基板２上のワイヤーボンディング部分ニスポット状
にＡＪ８を被覆し、更にその外周部にガラス封止部でガ
ラスとの接着性を向上する為の酸化物薄層９を被覆した
も゛のである。図では被覆部が１つのみであるがフレー
ム状に等間隔で設けることは勿論である。FIG. 3 is an external view of an embodiment of the lead frame of the present invention, in which the wire bonding portion on the substrate 2 is coated with AJ8 in the form of a Nispot, and the outer periphery is further provided with a glass sealing portion to ensure adhesion to the glass. It is coated with a thin oxide layer 9 for improvement. In the figure, there is only one covering portion, but it goes without saying that they may be provided in a frame shape at equal intervals.
第４図は未発明によるリードフレームを用いて低融点ガ
ラス封止型ＩＣの断面構造を示したもので、封止用ガラ
ス５，５′は直接４２アロイ２と接することなく、４２
アロイ表面に形成された被覆酸化物層９を介して封止が
行われている為そこに拡散接合により強力で信頼性良好
なガラス封止がされている。FIG. 4 shows the cross-sectional structure of a low-melting point glass-sealed IC using a lead frame according to an uninvented invention.
Since sealing is performed through the coating oxide layer 9 formed on the alloy surface, a strong and reliable glass seal is formed there by diffusion bonding.
ここで被覆酸化物層９としては、ＡＪ ２０３ 、Ｙ
００３．５ｉｎ２、Ｂ２Ｏ３、ＰｂＯが有効である。こ
れは安価であることは勿論、封止用低融点ガラスの成分
と近似し、相互に拡散溶融によって安定した接合を得る
ことができるからである。上記酸化物は単体でもよく２
種以上の複合酸化物でも本発明の効果は変らない。酸化
物層の厚みとしては０．１〜３μｍが適当であり、０．
１μｍ以下では封着効果が少く３μｍ以上では被覆層の
剥離などの問題があり被覆コストも高くなる。Here, as the coating oxide layer 9, AJ 203, Y
003.5in2, B2O3, and PbO are effective. This is because not only is it inexpensive, but it is also similar in composition to the low melting point glass for sealing, and stable bonding can be obtained by mutual diffusion melting. The above oxide may be used alone2
Even if more than one type of composite oxide is used, the effects of the present invention will not change. The appropriate thickness of the oxide layer is 0.1 to 3 μm, and 0.1 to 3 μm.
If the thickness is less than 1 μm, the sealing effect will be poor, and if the thickness is more than 3 μm, there will be problems such as peeling of the coating layer, and the coating cost will increase.
又酸化物の被覆法としては、薄く均一に被覆すること及
び、リードフレームの他の部分に悪影響を及ぼすことな
く密着性のよい被覆を行う必要から物理的気相蒸着法（
ＰＶＤ法という）又は化学的気相蒸着法（ＣＶＤ法とい
う）が最適である。In addition, as a coating method for oxide, physical vapor deposition method (
PVD method (referred to as PVD method) or chemical vapor deposition method (referred to as CVD method) is optimal.
以下実施例によって詳細説明する。A detailed explanation will be given below using examples.
所要のパターンに形成されたリードフレームのワイヤボ
ンディング部表面にのみ真空蒸着法により３μｍのＡＪ
を蒸着しに後、その外周部のガラス封止部にイオンブレ
ーティング法（Ｐ Ｖ Ｄ）により０．５μｍのＡ７＋
２０８皮膜をリードフレームの表裏に被覆した。イオン
ブレーティング方法としては、原料としてＡｌ２Ｏ３焼
結体を用い電子ビーム加熱により蒸発させ、酸素圧４Ｘ
１０ ’Ｔｏｒｒで１８．５６ ＭＨｚ １１００〜
２００Ｗの高周波電力を印加して実施した。AJ of 3 μm is applied by vacuum evaporation only to the surface of the wire bonding part of the lead frame formed in the required pattern.
After vapor deposition, 0.5μm A7+ was applied to the glass sealing part of the outer periphery by ion blating method (PVD).
208 film was coated on the front and back of the lead frame. In the ion blating method, an Al2O3 sintered body is used as a raw material, evaporated by electron beam heating, and an oxygen pressure of 4X is used.
18.56 MHz 1100~ at 10'Torr
The test was carried out by applying a high frequency power of 200W.
又部分コーテングは夫々マスキング法によって行った。In addition, partial coating was performed by a masking method.
このようにして得られたリードフレーム材と打抜き加工
により、リードフレームとしてＰｂＯ−Ｂ２Ｏ３系低融
点カラスを用イテ４５０℃、１ｏ分間のガラス封着を行
ってその封着部界面の状態を断面のＥＰＭＡ法による観
察を実施したところ、従来の４２アロイ／ガラス界面に
は相互拡散が殆んど認められないのに対し、Ａノ２ｏ３
／ガラス界面では相互拡散層の形成が確認され、安定し
たガラス封止が為されていることが判った。又本実施例
によるリードフレームで作製した低融点ガラス封止型Ｉ
Ｃは高温多湿試験でも水分の浸入が無（ＩＣ特性の劣化
も認められなかった。Using the lead frame material obtained in this way and punching process, we used PbO-B2O3 low melting point glass as the lead frame and sealed the glass at 450°C for 10 minutes to examine the state of the interface of the sealed part in the cross section. When observed using the EPMA method, almost no interdiffusion was observed at the conventional 42 alloy/glass interface, whereas Ano2o3
The formation of an interdiffusion layer was confirmed at the /glass interface, indicating that stable glass sealing was achieved. In addition, low melting point glass sealed type I made with the lead frame according to this example
In C, there was no infiltration of moisture even in high temperature and high humidity tests (no deterioration of IC characteristics was observed either).
以上説明しな如く、ワイヤーボンディング部にスポット
状にＡ）を被覆□した後、その外周のガラス封止部にガ
ラスとの接着性の良好な酸化物層を薄く被覆形成したリ
ードフレームを用いることによって、ガラス封止性を改
善し、安価でかつ信頼性の向上した低融点ガラス封止型
ｒｃを製作することができた。又これシテよってＩＣチ
ップの大型化、高密度実装の双方にも充分対応できるＩ
Ｃパッケージが可能となった。As explained above, a lead frame is used in which the wire bonding part is coated with A) in a spot shape, and then the glass sealing part on the outer periphery is coated with a thin oxide layer that has good adhesion to glass. As a result, it was possible to manufacture a low-melting-point glass-sealed RC with improved glass sealing properties and improved reliability at low cost. In addition, this feature allows it to fully support both large-sized IC chips and high-density packaging.
C package is now available.
第１図は従来のアルミストライプテープの外観図、第２
図は従来のテープを用いたＩＣ断面図、第３図は本発明
のリードフレームの外観図、第４図は本発明のリードフ
レームを使用したＩＣの断面である。
ｌニアルミストライプテープ、２：リードフレーム基板
、３：被覆Ａｌ、 ４．４’：パッケージ用セラミッ
ク、５．５’：封止用低融点ガラス、６：ＩＣチップ、
７：ボンディングワイヤー、８ニスポット状Ａ／、９：
酸化物被覆層、１０ニスポツトアルミリードフレーム。Figure 1 is an external view of conventional aluminum stripe tape, Figure 2
FIG. 3 is a cross-sectional view of an IC using a conventional tape, FIG. 3 is an external view of a lead frame of the present invention, and FIG. 4 is a cross-sectional view of an IC using the lead frame of the present invention. 1 Ni aluminum stripe tape, 2: Lead frame substrate, 3: Covering Al, 4.4': Ceramic for package, 5.5': Low melting point glass for sealing, 6: IC chip,
7: Bonding wire, 8 Nispot shape A/, 9:
Oxide coating layer, 10 varnish spot aluminum lead frame.
Claims (3)
、フレーム上のボンディング部にスポット状にＡノを被
覆されてあり、そのＡノ外周部のガラス封止部分に０．
１〜３１ｚｍの厚みの酸化物薄層が被覆されていること
を特徴とするＩＣ用リードフレーム。(1) In an IC lead frame for sealing with low melting point glass, the bonding portion on the frame is coated with A in a spot shape, and the glass sealing portion on the outer periphery of A is coated with 0.
A lead frame for an IC, characterized in that it is coated with a thin oxide layer having a thickness of 1 to 31 zm.
、Ｂ２Ｏ３、ＰｂＯから選ばれた１種以上の酸化物であ
ることを特徴とする特許請求の範囲第（１）項記載のＩ
Ｃ用リードフレーム。(2) The coating oxide layer is Ano208, Y2O3, 5i02
, B2O3, and PbO as defined in claim (1).
Lead frame for C.
覆されていることを特徴とする特許請求の範囲第（１）
項乃至第（２）項記載のＩＣ用リードフレーム。(3) Claim No. (1) characterized in that the coating oxide layer is coated by a PVD method or a CVD method.
The IC lead frame described in items (2) to (2) above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148333A JPS5848952A (en) | 1981-09-18 | 1981-09-18 | Lead frame for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148333A JPS5848952A (en) | 1981-09-18 | 1981-09-18 | Lead frame for integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5848952A true JPS5848952A (en) | 1983-03-23 |
Family
ID=15450420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56148333A Pending JPS5848952A (en) | 1981-09-18 | 1981-09-18 | Lead frame for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5848952A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984059A (en) * | 1982-10-08 | 1991-01-08 | Fujitsu Limited | Semiconductor device and a method for fabricating the same |
-
1981
- 1981-09-18 JP JP56148333A patent/JPS5848952A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984059A (en) * | 1982-10-08 | 1991-01-08 | Fujitsu Limited | Semiconductor device and a method for fabricating the same |
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