JPS5846390A - Chip selection of lsis connected in plurality - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for selecting chips in a plurality of connected LSIs, and more particularly to a method for selecting chips in an LSI having several chip select terminals using a single signal line.

Conventionally, when a plurality of LSIs of the same type, such as display drivers, are connected, a chip select signal is generally required to distinguish each chip. Therefore, a plurality of signal lines must be individually connected to the plurality of chip select terminals from the outside. Normally, a plurality of lines are formed on a printed wiring board, but when aiming for a compact design, that is, when attempting to improve packaging density, the plurality of signal lines becomes a significant burden.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to improve packaging density by eliminating the need to connect individual signal lines to chip select terminals when connecting multiple LSIs each having a plurality of chip select terminals. be.

To achieve this objective, the present invention provides a first fixed level voltage or a second fixed level voltage to each of a plurality of chip select terminals.
While applying a fixed level voltage in advance, serial data is input to the other commonly connected terminal of the LSI, and this serial data is converted into parallel data inside the LSI, and this parallel data and It is characterized in that only a predetermined LSI is selected based on combination data given in advance to a chip select terminal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings, through the overall configuration and functions of an LCD driver to which the invention is applied.

FIG. 1 applies the method of one embodiment. LCD driver L
FIG. 2 is a block diagram of an internal circuit of SI.

The LCD driver 1 can be roughly divided into a RAM section 1 that stores display data. Shift register section 2 for extracting RAM contents as display signals; h and C color/return section 3 for forming LCD display signals; 4. Serial/Noclarel control unit for data transfer with the outside. Chip select section 5. , to clear section 6. It is composed of an LCD driver section 7 and a clock generator section 8. The configuration and functions of each of these parts will be described in detail below.

(The 11 RAM section I RAM II has a 64x20 bit configuration, and each bit of the RAM corresponds to one dot 102 on the display. FIG. 2 shows the relationship between the RAM and the display.

AD□-AD7 is the address of RAM II, which is AD.

~AD5 is for row selection, and AD6 and AD7 are for column selection. H□-R19 is the backplate timing, HO to H7 are column selection A
D6=Q, AD7=Q, H8--5 corresponds to column selection AD6=l, AD7=0, and H16 to H19 column selection AD6=0. Compatible with AD7-1. S.O.
~s63 is a segment, row selection AD□-AD5
It corresponds to The actual RAM configuration is divided into odd and even fields, as shown in FIG. 3(a), and the address A□ selects odd and even columns. This divides and takes out the odd numbered signal and even numbered signal of the segment, and at the same time separates them into separate shift registers 2.
1.22 to perform data transfer. but,
The correspondence relationship between the RAM II and the display on the LCD dot matrix 101 is shown in FIG.

As shown in Figure 1, the address for RAMII is
A1 to A5 and CO to C4 are stored in the data selector 12, A□, A6. A7 and hO to h4 are given, but CO to C4 are serial signals SR@ which are used to sequentially take out the contents of the RAM and display them on the LCD.

Given to create SR1. In addition, AO to A7
Reference numeral 13 denotes an address flip-flop (hereinafter, the flip-flop will be referred to as F/F) that is applied to the RAM II only when data is transferred with the outside.

Therefore, in order to perform LCD display, CO~C
4, hO to h4 are given as a RAM address and data selector, and data transfer from the outside is given in the form of an interrupt. Normally, at the time of this interrupt, an address completely different from the address to which the display signal should be given is given, so
During this time, the display signal is disturbed and normal display on the LCD is no longer possible. Therefore, in this LSI, RAM11
By providing a data buffer at the output of , it is possible to always output the correct display signal even if a data transfer interrupt occurs from the outside at a timing such as .

Details of part of the address controller and part of the data selector in FIG. 1 are shown in FIGS. 3A and 3B.

In FIG. 3(a), the signal CS is the CSF shown in FIG.
/F46 output signal, and as described later, when cs-1, the chip is in the selected state, and when C3=0,
It is in a non-selected state. R.A.S.

RAF is a signal that is generated only when data is transferred from the outside, and when RAS occurs in cs-1, RAM
The address and selector are switched to addresses Al to A7. cs:=, 0 or when RAS does not occur, the RAM row decoder 14 contains co-C4
However, h3 and h4 are also given to the column selector 15.

Here, C counter 31 consisting of CO~C4, h□~
As described in (3), the h counter 32 consisting of h4 is a counter for creating a display signal for the LCD, and as is clear from the time chart shown in FIG.
For example, while a puck play) B19 is occurring, h
□-h4 is "0", RAM0 column select is selected as AD6=AD7=0, h□ = hl =
Since h2 = Q, SRΦ has mO, that is, RAM
The 0th bit line of the even numbered area is scanned by the C□-C4 counter to form serial data. The same applies to SR1. In other words,
The display data to be given in the next H□ is shifted to the shift registers A and B during back plate l (1g), and is latched and output when switching from B19 to Ho. After that, the ho-h4 counter is By sequentially counting up, the contents of the RAM can be taken out as a display signal.

FIG. 3(C) shows a time chart of the RAS and RAF signals. When data is transferred from the outside to the RAM, RΔS and RAF occur. Here mi, ni
The flip-flops 16 and 17 that output the are latch type F/Fs whose clock input ΦN is ΦN = cs - RAF, and when C5-〇 or RAF does not occur, that is, when ΦN = "'HIGH", , input M
Output the contents of i and Ni as they are. and cs=
1, when RAF occurs, that is, ΦN = ”L
OW”, data is held. Therefore,
RAS for data transfer with the outside.

Even if RAF occurs and the RAM output changes to another content,
The F/Fs 16 and 17 can store the previous correct display data and prevent the display signal from being disturbed.

Here, the RAF signal includes the RAS signal because the RAM address switching is RAS, and the change in the RAM output signal at the time of switching is not transmitted to the F/Fs 16 and 17 that output mi and ni. This is to ensure that. RAS and RAF will be described in more detail in (4).

(2) Shift register part 2 As a means to take out the RAM contents as a display signal',
The RAM output, which is normally output in bytes, is converted into a serial signal, transferred to a shift register, and latched with a clock ΦS synchronized with the LCD signal to obtain a segment signal. As shown in Figure 1, shift register part 2
is divided into two blocks, A and B. Shift registers A shown at 21 are provided at odd numbered segments, and shift registers B shown at 22 are provided at odd numbered segments. The reason why the shift register is divided into even and odd numbers is to divide the output pins of the LSI into even and odd numbers for output.

Figure 4 shows the LCD driver LSI explained here.
FIG. 3 is an LCD pattern diagram corresponding to the above. Applications of this LSI include kanji and graphic displays, but these have a large number of segments, and in order to extract the segment signal as a terminal, it is necessary to extract every other segment vertically due to terminal pitch restrictions. . Therefore, in order to ensure that there is no crossing between the LSI segment signals and the LCD segment terminals, the LSI output pins are also numbered evenly.

It is divided into two odd numbered parts and output. Furthermore, A, 8
Another reason for dividing into two blocks is to reduce power consumption of the LCD driver LSI. A,
By dividing into 82 blocks, the clock that transfers the RAM data to the shift registers 21.22 is:
It only costs d8.

If it is not divided, 64 transfer locks will be required, and in order to create 64 transfer locks within a certain period of time, the frequency of the fundamental oscillation must be doubled, as in this example. This is because if the CMO8 is used, the power consumption will be doubled.

(3) H and C counter part 3 Figure 5 shows the h counter 32. The details of the C counter 31 and its surroundings are shown in FIG. 6, and a time chart of the C counter is shown. The C counter 31 performs a counting operation using the basic clock Φ1 generated by the clock generator→81, and generates the clock ΦS when C4C3C2CIC□=1. A signal H line is connected to the reset terminal of the C counter 31, and synchronization is achieved by this signal H. In addition, C counter 31
is a 32-decimal counter. h counter 32 is ΦS
It is a counter whose clock is reset 7 B,
It is given by HR=H+HOR. This signal I] is a synchronization signal as before, while HOR is determined by the value of the N register 33 (consisting of N□-N3). The value of the N register 33 can be set externally.

The ROM matrix 34 shown in FIG. 5 is a circuit for generating a reset signal HOR for the h counter 32 depending on the value of N. In the time chart of Figure 6, HOR occurs at the timing h4h3h2h1h□, and
The counter 32 is in 2o base. H8F/F3
5, the clock is ΦS and the input is H (H5 HOR), so it is synchronized by the H signal and the HO
It is inverted every time the R signal is input. As is clear from the above, the h counter 320 count number is
It determines the duty of the back plate, so the N register 33 is a register for setting the duty. Further, the signal H8 is a signal used to form an alternating voltage of the LCI.

+4) All data processing inside the serial/parallel control unit 4 is performed in parallel, and the external
Serial/parallel conversion is required to receive and receive data serially.

In FIG. 1, the L register 41 is a shift register with serial-in/parallel-out and parallel-in/serial-out functions, S D □ is a serial data bus or serial data input terminal, and C
L□ is serial transfer lock.

LC is a synchronization signal.

The 8-bit data serially transferred from the outside via the serial data input terminal (SD□) is temporarily stored in the L register 41, and is stored in the internal RAM address data.
Chip select and duty data or RAM1
It is given as data written to 1. When taking out the contents of the RAM, the RAM data is first input in parallel to the register 41, and then taken out as a series of serial data by the shift function. In order to distinguish between these data transfer types, 2 bits are added in front of the 8-bit 7 real data, making it 00.0.
1, 10, and 11 are detected and each data transfer is performed.

Here, “00” is for writing duty and chip select data, “01” is for writing RAM address data, “10” is for writing RAM data, and “11” is for reading RAM data. In addition,
After writing or reading RAM data,
RAM address A is automatically incremented by +1. This is to prevent the complexity of specifying addresses each time in continuous data transfer with RAMII.

FIG. 7 shows details of the serial/parallel control section 4, and FIG. 8 shows a time chart of 7 real data transfers.

The serial data transfer operation starts from the rising edge of LC using CLo as the basic clock. K counter 42
is a 4-bit binary counter, and LC is “
The counter 42 counts from 0 to 14 and completes the transfer of one serial data. 2 bits are added to the beginning to distinguish the type of data. ΦLS□ and ΦLS1 are clocks that receive the 2-bit contents as control bits, and LS□ and LSI flip-flops 43 and 44 are used as control bits. Bit (Figure 8(a)
The contents of A and H) are statically stored in the serial data transfer period. ΦL is the clock of the L register 41, and the K counter 42
, 3, 4, 5, 6, 7°8.9 and 12. Clock of previous 8 shots (2~
9) is the clock for the L register 41 to perform the shift operation, and the last clock (12) is the clock for the built-in RAM II.
This is a clock for importing the contents of . This distinction is
The AND which controls the input gate of the L register 41 is performed by the signal 3·K2.

RAS is K counter 42y6Z, 10, 11. .

12, RAF is a signal output during 9, 10, 11, 12, and 13. RAS is used as a clock for chip selection, duty writing, and address writing.

It is also used as address switching when writing/reading data to/from RAM. Regarding RAF, (1)
As mentioned above.

SD□ is a bidirectional data line, as shown in FIG. 7(a), and is normally an input, but when the SDD flip-flop 45 is "1", it becomes an output.

As shown in the time chart in Figure 8(b), the SDD is a flip-flop that is set only when reading RAM data to the outside.After the control 2 pit is given, the serial signal of the RAM data is sent to the outside. This is a signal that continues for seven seconds until the end of the transfer.

Next, we will specifically describe the four operations identified by the control bits.

(a) Chip select and duty writing Figure 8 (
As shown in the time chart in b), when the control bit "00" is sent, LS□=Q.

LSI=Q, and the ΦCS clock is generated.

At the rising edge of ΦCS, the shift of the 8 bits of serial data following the control bit has been completed in the L register 41, and among the 8 bits, the upper 4 bits L4~
The contents of L7 are written to N register 33. Furthermore, as shown in the input conditions of the CS flip-flop 46 in FIG. 7(a), the external chip select terminals CS, 0-
With the code given to CS 3.

Lower 4 bits of 8 bits of serial data L □ -L
If the contents of 3 match, C5F/F 46 is set, and if they do not match, it is reset. In other words, 1. When chip select data is transferred to a large number of connected driver LSIs, C5F/F 45 of the chip selected to double this code will be set, and other chips that do not match this code will All C5's are reset. Here, l-4=L5=I, 6=L7=1
In this case, ΦCS is prohibited. This is because only when this code is used, setting of chip select and duty is prohibited and auto clear is canceled. Address writing and data transfer to RAM shown below are valid only when C5 is set.

(b) Writing of address data A time chart is shown in FIG. 8(b). When control bit “01” is given, LS□=O.

LSI=1 and ΦA clock is generated. ΦA
At the rising edge of , the 8 bits of serial data following the control bit have already been shifted to the L register 41, and as shown in FIG. 7(b), LS□=0, so the address flip-flops (AO to A7) The input of 13 becomes L□-L7, and address data is written.

(c) Writing of RAM data A time chart is shown in FIG. 8(b). When control bit “10” is given, LS□ = l, LS
I-0, and a write clock WR for the RAM is generated. The clock WR is a clock generated between the RAS signals, and while the RAS is being output, the 8 bits of serial data following the control bits have been shifted to the L register 41, as shown in Figure 3(a). As shown, L O-L 7 is given as a RAM input and WR
Written to RAM by the clock. The address at this time is determined by the row decoder 14 based on the RAS signal.
．． The column decoder 15 receives address signals AO to A7.
is given, and data is written to addresses indicated by AO to A7. Here, K counter 42
The ΦA clock is generated at the 13th position. Figure 7(b)
As shown in , since LS□=1, AO to A7 are incremented by +1 by this ΦA clock. This means that when continuously writing data to the internal RAM, you do not have to specify the address each time.The address is incremented by +1 just by writing the data, so there is no need to specify the address each time, and the data can be quickly Transfers can be made.

B) Reading of RAM data A time chart is shown in FIG. 8(b). When control bit "11" is sent, LS□=1. LS□=1, 5DDF/F45 is set from the next bit of the serial data, and as shown in FIG. 7(a), S D □
is given the least significant bit L□ of the L register 41, and as a result of shifting the contents of the ljL register by the clock ΦL, it is given to the outside from 5l)0 as serial data.

Here, the L register 41 stores l(AM data) indicated at addresses A□ to A7.

This is based on the following reasons. That is, before this RAM data is read, the four operations shown in FIG. 8(b) are always performed. What these four operations have in common is the clocks ΦL and R in FIG. 8(a).
AS is always given. clock ΦL
At the rising edge of the last applied clock, since the RAS signal is output to the RAM, A □ -A 7 is applied as the address signal, and the RAM output output -6 to
0□Ao, the contents of the RAM indicated by A7 are being output. - On the other hand, as shown in FIG. 7(a), 00-07 is given to the input of the L register 41, and A
□-The contents of the RAM indicated by A7 are read.

Therefore, when reading out RAM data is started, the contents of the RAM are always stored in the L register 41, and the contents of the RAM data can be read by shifting this and taking it out. R.A.
The reason why the ΦA clock is generated at the end of reading M data is exactly the same as in the case of writing RAM data.

(5) Chip select section 5 The segment signals of the LCD driver 100 illustrated here are 64 S□-563, and normally this L
Use multiple SIs. In this case, in order to select one LSI from among multiple chips, the chip select terminal C
5□-C83 is provided. 4 Up to 16 LCD driver LSIs can be connected through this chip select terminal.

Here, as a feature of one embodiment of the present invention, there is no need to provide four external signal lines as chip select signals, and each of the four terminals can be connected to GND or a fixed power supply level of VCC. good.

Figure 9 shows the case where the LCD driver LSI 1 is connected, but even in this case, as a signal line,
Only SD□, CL□, LC, Φ, and H are required 0■A・■B
TVCCIGNDIvDISP indicates power supply lines, and these five lines are essential. That is, up to 16 LCD drivers 100 can be connected using a total of 10 lines, which is very useful from the viewpoint of packaging density.

To explain the aspect of chip selection with reference to FIG.
There is a flip-flop 46 named 3, and when C5 is set, this driver LS1100 is in the selected state, and when C5 is reset, it is in the non-selected state. The chip select data is input as a serial signal from the outside via the serial data input terminal SD□.
It is given to L□-L3 of the register 41, but the contents of L□ to L3 at this time and the chip select terminal CS
If the contents of the identification signals based on the combination of fixed power supply levels given in advance to the o-CS 3 match, C5 is set;
If there is a mismatch, C5 is placed in a reset state.

When RAM address data and RAM data write/read signals are sent, only the driver LSI with C8 in the set state will receive them, and the driver LSI with C5 in the reset state will receive them.
- Do not accept disconnected data.

Note that the details of the setting and resetting conditions for C5 are as described in (4). What controls the set/reset of the C8F/E 46 is the chip select controller 55 shown in FIG. 4 It is composed of a four-man power AND circuit that receives the output of this matching circuit.

(6) Auto clear part 6 The pack plate, segment signals, and data ties of the LCD driver 100 in this example can be controlled by software from the outside, but in the case of software processing, normal signals are generated after power is turned on. It will take time to do so. During this time, the LCD will not be able to display images properly, which may seriously damage the image of the product. Therefore, in the LSI of this example, the internal solve flop ACL is set immediately after power is turned on, and the AC
While L is in the set state, the data to shift register part 2 is always “0” and the LCD is “OFF”.
I try to keep it in good condition.

ACL is reset by external control. In this example, when a code for "1111" is sent in the duty setting, the ACL is reset without setting the duty.
I am trying to reset L.

Therefore, after turning on the power, use the software to set the pack plate and segment to their initial values, and also set the duty, and then reset the above ACL.
It is possible to transition the CD from the "0FF-" state to a normal display.

FIG. 10(a) shows a specific circuit configuration of the auto-clear part 6, and FIG. 10(b) explains its function.

When vcc is given, point A becomes a waveform as shown in Fig. 10(b) by the C and R differentiator, and ACLF
/F is set to "1". This state is maintained until a reset input is received.

As shown in FIG. 3(b), the signal ACL is a signal that cuts the inputs SRΦ and SR1 of the shift registers 21 and 22, and while the ACL is held at 1, the shift register has 60 ``As data is provided, the display remains OFF.

The ACLF/F (included in the auto clear controller 61) is released when the code corresponding to the duty is selected as "1111" in writing the chip select and duty in FIG. 8(b).
At this time, the Re5et signal shown in FIG. 10(a) is generated and releases the ACL F/F.

(71L CD driver part 7 FIG. 11 shows details of the LCD driver part 7.

In FIG. 11(a), shift register 22.21
The exclusive logic M sum (Excut, 5IvEOR) outputs of H8 and SR, and H8 and SR1 are given to the inputs of , respectively. This is to create a seven-inversion signal in accordance with the period of H5. Φ1. ΦS is Φ1. shown in the time chart of FIG. The SRΦ and SR1 signals, which are the same signal as ΦS and have been converted into serial data, are shifted into the respective shift registers 22 and 21 by the Φ1 clock, and are connected to the next stage of flip-flops 72' and 71' by the ΦS clock. The signals are latched into respective latch circuits 72 and 71. So, S G in Figure 11(a)
□-S G 63 is a segment signal latched in ΦS synchronization. Also, $1 in FIG. 11(a). The circuit indicated by $2 is an L CD )"Leiper cell, and its specific configuration is shown in FIG. 11(b) and FIG. 11(C), respectively.

Here, #2 in FIG. 11(C) is an LCD segment driver, while #1 in FIG. 11(b) is a driver that can be used for both segment/pack plate. It is also a driver cell that also serves as a passive rate. In this usage example, the #1 type driver cell is used for the S□-519, so the S□-519 can be output as a back plate or as a segment.

#3 shown in FIGS. 11(a) and 11(d) is a circuit for supplying power to the LCD driver. FIG. 12 shows how to provide VA, VB, and VM power supplies. As shown in the figure, VA, VB, and VM obtain a single power supply of VDISP by resistor division. FIG. 13(0) schematically shows these mutual relationships.

When displaying the 13th internal body, (a) back plate signal, (b) segment signal * (C) VAIVB) VM
I(d) (H8) signal and (e) (SGo)'
Indicates signal timing.

Note that FIGS. 11(e) and 11(f) show the internal connection configuration for #1 type driver cell when outputting as a segment signal (FIG. 11(e)) and the internal connection configuration when outputting as a back plate signal. Connection configuration (shown in the same figure).

In addition, in FIGS. 11(b) to 11(f) and others, the signals whose names are given parentheses mean the level-converted signals shown in the parentheses.

The features that make up this driver part 7 as described above are as follows:
The distinction between the back plate signal and the segment signal is a part of the final dry signal, in other words, it can be determined simply by selecting the output as either the back plate type or the segment type, so the RAM
From this point of view, both back plates and segments can be handled in the same way as RAM data. Figure 14 shows S.
The RAM data arrangement is shown when O~819 is used as a back plate. In this case, data is set in the N register 33 so that the duty is 1/20,
The h counter 32 counts as shown in FIG. At H19 timing, the 0th bit line of the RAM area with A7A6=00 is transferred to the shift register 21.22, and at the 9th H□ timing, the latch clock Φ
Data is outputted to flip-flops SG□ to 5G63 by S. The type of LCD driver shown in FIG. 11(f) for this output SG□ is selected here, and the shift register manual power is SR
Φ■H3゜S R1■H5 (■ indicates exclusive OR symbol), so the output waveform of SG□ is
The waveform will be as shown in FIG. 3(e), and the back plate waveform will be as shown in FIG. 13(a). 7 directions, 5G20-8G
63 is a driver shown in FIG. 11(C) as a segment, so depending on the content, for example, FIG.
) is the waveform shown. Here, N register 33
By changing the settings, the duty for the LCD can be changed arbitrarily. Furthermore, the order in which the back plates come out can be changed arbitrarily by changing the RAM data.

(8) Clock Generator Unit 8 The LCD driver LSI 100 shown here to explain one embodiment has a built-in clock generator 81 so that the display function can be executed by the driver alone. As shown in FIG. 9, when multiple drivers are connected, only one of them is configured to oscillate a clock using this clock generator 81, and the other chips are clocked from this one. be supplied with. Most of the signals required inside the LSI are created based on this clock. On the other hand, as a synchronization signal for synchronizing a plurality of LSIs, a signal generated within one LSI, preferably an LSI serving as the source of the basic clock, is used. This signal is then supplied to other chips to ensure overall synchronization.

This is shown in FIG. 1, where Φ is the basic clock and H is the synchronization signal. Whether these Φ and H are generated or received can be changed by the LSI mask.

In FIG. 1, h, c counters 32, 31 and H
8F/F is asynchronous after power-on, and is synchronized by the first H signal. The H signal is a signal that is generated for each frame of the LCD, and is synchronized for each frame.

It was explained with reference to FIG. 6 that the c counter and H5 are reset and synchronized by the H signal, but this synchronization signal H is a signal generated by the circuit shown in FIG. This is the signal with the longest period among the repeated signals.As is clear from FIG. 6, the pulse width of the signal H is the same as ΦS, and therefore the same as the pulse d of the clock of Φ1.

As shown in FIG. 15, there are two ways in which the H signal is supplied: one is supplied to the outside, and the other is supplied from the outside, and this can be switched by a mask.

On the other hand, the clock used internally is Φ shown in Figure 5.
Although not clearly shown in FIG. 1 and FIG. 5, in this embodiment, two-phase clocks Φ1. It is configured to generate Φ2 and supply it to the internal circuit. The clock Φ shown in FIG. 1 is Φ1
．． It is the basic clock that constitutes the two-phase clock of Φ2,
Φ1. Φ2 is asynchronous between each chip, but the above-mentioned H
This two-phase clock Φ1. Φ2 is also synchronized. FIG. 16 shows two-phase clock Φ1. The generation circuit of Φ2 is shown.

HT is a signal generated from signal H, and is for synchronizing Φ1Φ2. FIG. 17 shows a time chart. Φ1. for H by the H signal. This means that the phase of Φ2 has been changed.

As is clear from the above description, according to the present invention, the plurality of chip select terminals of each LSI are fixed at the first power level or the second power level, the select number of each chip is determined in advance, and the select number of each chip is determined in advance. By transmitting a chip select code, which is serial data corresponding to this predetermined number, to one terminal, a predetermined chip is selected from among multiple LSIs. It is possible to improve the packaging density by eliminating the need for signal lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the system configuration of the LCD driver 100, FIG. 2 is an explanatory diagram showing the relationship between RAM and display, FIG. 3 is an explanatory diagram around the RAM, and (a) is a block diagram of the circuit. , (b) is the signal SRΦ. A circuit diagram for generating S R1, (C) shows a time chart. Figure 4 is an LCD pattern diagram, Figure 5 is a block diagram of the h and C counters and their surrounding circuits, Figure 6 is a time chart of the h and C counters, and Figures 7 (a) and (b) are serial numbers. / Detailed circuit diagram of parallel control section, No. 8
Figure (a) is a time chart of serial data transfer.
Figure (b) shows a transfer time chart of each data. 9th
The figure is a diagram showing an example of the connection configuration of an LCD driver LSI to which the method of one embodiment of the present invention is applied. b) is an explanatory diagram of the operation. Figure 11 is an explanatory diagram of a part of the LCD driver, (a) shows a specific circuit diagram, and (
b) is a detailed view of #1 in Fig. 11(a), and (C) is a detailed view of #2. (d) is also a detailed diagram of #3, and Figure 11 (C) is a circuit diagram when outputting as a segment signal, Figure 11 (
0 is a circuit diagram when outputting as a back plate signal. Fig. 12 is an explanatory diagram of how to power the LCD driver, Fig. 13 is an explanatory diagram showing the relationship between the levels of each signal waveform in (a) to (e), and Fig. 14 is an explanatory diagram of how to connect the S□ to 19 to the back plate. Explanatory diagram of RAM data arrangement in case of binding, No. 15
The figure is a circuit diagram for explaining the generation of the 4N signal, and FIG. 16 is a two-phase clock Φ1. FIG. 17 is a circuit diagram for explaining the generation of Φ2, and a time chart for explaining clock synchronization. 100...L CD driver, 5...Chip select section, 55...Chip select controller, 41
...L register, 46...chip select flip-flop, C5□, C51, C52, C53-each chip select terminal or signal given thereto, SD
□ ... Serial data input terminal or serial data bus. Patent applicant: Sharp Co., Ltd. Agent: Patent attorney: Aobai Ao and two others Fig. 15b Fig. 16 φ1 φ Fig. 17

Claims (1)

[Claims] (1) A method of chip selecting by connecting a plurality of LSIs each having a plurality of chip select terminals, wherein a first fixed level voltage or a second fixed level voltage is applied to each of the plurality of chip select terminals in advance. While giving,
Serial data is input to the other commonly connected terminal of the LSI, this serial data is internally converted to parallel data, and this parallel data is compared with the combination data given to the chip select terminal. A chip selection method for a plurality of connected LSIs, characterized in that only a predetermined chip is selected according to the result, thereby eliminating the need to individually connect a plurality of signal lines from the outside to a plurality of chip select terminals. .