JPS5845974A - Thermal head - Google Patents
Thermal headInfo
- Publication number
- JPS5845974A JPS5845974A JP14680181A JP14680181A JPS5845974A JP S5845974 A JPS5845974 A JP S5845974A JP 14680181 A JP14680181 A JP 14680181A JP 14680181 A JP14680181 A JP 14680181A JP S5845974 A JPS5845974 A JP S5845974A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- thermal head
- bumps
- film carrier
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 5
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000011888 foil Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/345—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads characterised by the arrangement of resistors or conductors
Landscapes
- Electronic Switches (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はサーマルヘッドに関する−ものであり、特にこ
のサーマルヘッドに組み込まれた半導体装置の配線の改
良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal head, and more particularly to an improvement in the wiring of a semiconductor device incorporated in the thermal head.
サーマルヘッドは周知のように微小な抵抗発熱体を一列
またはマトリクス伏に配置し、その発熱体を選択的1通
電発熱さよ、4発熱抵抗体に瘤触させた感熱紙を発色さ
せて電気的情報をi電化する装置である。As is well known, the thermal head consists of minute resistive heating elements arranged in a line or in a matrix, and the heating elements are selectively energized (1) to generate heat, and (4) thermal paper brought into contact with the heating resistors is colored to generate electrical information. This is a device that converts electricity into i-electronics.
第1図は従来のサーマルヘッドの平面図、第2図は同サ
ーマルヘッドのX−X/断面図を示している。これらの
図においては1は放熱用基台、2はこの放熱用基台1上
に設置された表面を、グレーズしたセラミック等よりな
る耐熱性基板である。3は耐熱性絶縁基板2上に形成さ
れた発熱抵抗体であり、通常1m当り8個(8ドツト/
m)程度の微細なパターンとして形成されている。前記
発熱抵抗体は各組に分けられ、この各組に分けられた発
熱抵抗体3の一方端は共通電極4として各組ごとに電気
的に接続されている0また、発熱抵抗3の他端側には分
離電極6が形成されている。FIG. 1 is a plan view of a conventional thermal head, and FIG. 2 is a sectional view taken along line X-X of the same thermal head. In these figures, 1 is a heat dissipation base, and 2 is a heat-resistant substrate made of ceramic or the like with a glazed surface, which is placed on the heat dissipation base 1. 3 is a heating resistor formed on the heat-resistant insulating substrate 2, and usually there are 8 heating resistors per 1 m (8 dots/
m) is formed as a fine pattern. The heat generating resistors 3 are divided into groups, and one end of the heat generating resistors 3 divided into each group is electrically connected to each group as a common electrode 4, and the other end of the heat generating resistors 3 is electrically connected to each group. A separation electrode 6 is formed on the side.
6は放熱用基台1上に配置された放熱板であり、この放
熱板6上には半導体装置7が固定されている。8は半導
体装置7のコーテイング膜、9はヘッド配線実装部の全
体を覆うノくシベーション膜である。−
10は半導体装置7に形成された回路と耐熱性絶縁基板
2上の分離電極6とを電気的に接続するフィルムキャリ
アの導体部、10′は多層配線板11上の゛信号線12
と半導体装置T上の回路とを電気的に接続するフィルム
キャリアの導体部である。Reference numeral 6 denotes a heat radiating plate placed on the heat radiating base 1, and a semiconductor device 7 is fixed on the heat radiating plate 6. Reference numeral 8 indicates a coating film for the semiconductor device 7, and reference numeral 9 indicates a sintering film that covers the entire head wiring mounting portion. - 10 is a conductor portion of a film carrier that electrically connects the circuit formed on the semiconductor device 7 and the separation electrode 6 on the heat-resistant insulating substrate 2; 10' is the signal line 12 on the multilayer wiring board 11;
This is a conductor portion of the film carrier that electrically connects the circuit on the semiconductor device T and the circuit on the semiconductor device T.
前記従来のサーマルヘッドにおいて、ファクシミリの二
速化にともなってサーマルヘッドを高速記録すること糸
必要となり、多数の発熱抵抗体3を同時に駆動させる方
式がとられるようになってきた。このとき用いられる半
導体装置7は、シフトレジスタ、ラッチ、ドライバーを
多数ビット集4 ゛
積した特殊な高密度集積回路を用いる必要がある。In the conventional thermal head, as facsimiles have become two-speed, it has become necessary to use the thermal head for high-speed recording, and a method has been adopted in which a large number of heating resistors 3 are driven simultaneously. The semiconductor device 7 used at this time needs to be a special high-density integrated circuit in which shift registers, latches, and drivers are integrated into a multi-bit cluster.
一方、このような半導体装置は、通常8ビツト/■の微
細ハターンで形成された発熱抵抗体に対応して狭い領域
に多数個配列せねばならず、そのため集積回路を高密度
化して半導体装置を小型化する必要があった0
そのため半導体装置の集積回路は、多層配線構・造にし
て高密度化を図っていたが、多層配線の集積回路は製造
プロセスが複雑となり歩留りが悪かった0
さらに、この半導体装置7の両側(発熱抵抗体3側およ
び多層配線板11側)より集積回路の配線を取り出す必
要があり、配線が複雑になっていた。。On the other hand, such semiconductor devices must be arranged in large numbers in a narrow area to accommodate the heating resistor, which is usually formed with a fine pattern of 8 bits per square inch. There was a need for miniaturization. Therefore, the integrated circuits of semiconductor devices were made with multilayer wiring structures to increase the density, but the manufacturing process of integrated circuits with multilayer wiring was complicated and yields were poor. It is necessary to take out the integrated circuit wiring from both sides of the semiconductor device 7 (the heating resistor 3 side and the multilayer wiring board 11 side), making the wiring complicated. .
以下、従来のサーマルヘッドにおける半導体装置7の集
積回路およびその周辺の配線について詳細に説明し、そ
の欠点について述べる。Hereinafter, the integrated circuit of the semiconductor device 7 and its peripheral wiring in a conventional thermal head will be explained in detail, and its drawbacks will be discussed.
第3−はサーマルヘッドの基本的な回路図、第4図は同
部分の実体図である。第3図において、21μ半導体装
置7内の出力トランジスタ22と発熱抵抗体3とを1対
1で接続する出力側端子であり、この出力側端子21に
はバンプ(他の部分との電気的接続のためΦ凸状の導体
)が形成されている。3- is a basic circuit diagram of the thermal head, and FIG. 4 is an actual diagram of the same part. In FIG. 3, this is an output side terminal that connects the output transistor 22 and the heating resistor 3 in the 21μ semiconductor device 7 on a one-to-one basis. Therefore, a convex conductor (Φ) is formed.
23は出力トランジスタ22の共通接地線、24は出力
トランジスタ22を駆動するために同トランジスタのベ
ースに接続される駆動用電源線、23’、24’はそれ
ぞれ共通接地線23および駆動用電源線24と電気的1
に接続されている入力側の配線ライン、31は半導体装
置7上に形成されたラッチ、レジスタ等よりなる集積回
路、26は半導体装置7の入力側端子、26はフィルム
キャリアの導体部と多層配線板11上に形成された信号
線12との接続点を示す。23 is a common ground line for the output transistor 22; 24 is a driving power line connected to the base of the output transistor 22 to drive the transistor; 23' and 24' are the common ground line 23 and the driving power line 24, respectively. and electrical 1
31 is an integrated circuit formed on the semiconductor device 7 and includes a latch, a register, etc., 26 is an input terminal of the semiconductor device 7, and 26 is a conductor part of the film carrier and multilayer wiring. The connection point with the signal line 12 formed on the plate 11 is shown.
第4図は第3図に示した配線を有する従来のサーマルヘ
ッドの要部平面図である。同図において、−半導体装置
7は多数のトランジスタが配列された出力トランジスタ
゛部32.出カドライブ部33゜ラッチ、シフトレジス
タ等で構成される論理回路部34および入力回路部36
よりなる集積回路を上面に有している。FIG. 4 is a plan view of essential parts of a conventional thermal head having the wiring shown in FIG. 3. In the same figure, the semiconductor device 7 includes an output transistor section 32 . in which a large number of transistors are arranged. Output drive section 33; logic circuit section 34 and input circuit section 36 composed of latches, shift registers, etc.
It has an integrated circuit on its top surface.
6 ・
この集積回路の出力側端子21には発熱抵抗体3側との
結線のためのバンプが形成されている。この出力側端子
21は、樹脂フィルム41と導体箔42よりなるフィル
ムキャリア1oを介して、耐熱性絶縁御飯2上に多数個
配列された発熱抵抗体3と電気的に接続されている。6. A bump is formed on the output side terminal 21 of this integrated circuit for connection to the heating resistor 3 side. This output side terminal 21 is electrically connected to a large number of heating resistors 3 arranged on the heat-resistant insulated rice 2 through a film carrier 1o made of a resin film 41 and a conductive foil 42.
一方、半導体装置7の他方側に配置された多層配線板1
1上には信号線12が平行に多数本形成されており、こ
の信号線12上に樹脂フィルム41′と導体箔42′よ
りなるフィルムキャリア10’が配置されている。導体
箔42′はL字形をしており、その一端は信号線12と
接続部26において電気的に接続され、他端は半導体装
置7の入力側端子26と電気的に接続されている。On the other hand, multilayer wiring board 1 placed on the other side of semiconductor device 7
A large number of signal lines 12 are formed in parallel on the signal line 1, and a film carrier 10' made of a resin film 41' and a conductive foil 42' is arranged on the signal line 12. The conductive foil 42' has an L-shape, and one end thereof is electrically connected to the signal line 12 at the connection portion 26, and the other end is electrically connected to the input side terminal 26 of the semiconductor device 7.
このようにフィルムキャリアで半導体装置の入力部と出
力部の結線を行なうサーマルヘッドにおいて、従来の場
合は出力部に位置する出力トランジスタ、の共通接地線
23や駆動用電源線24を配線の煩雑な論理回路部34
を通して入力側に取り出す構成にしているため、半導体
装置上で多層配線構造にする必要がある0すなわち、共
通接地線23はスルーホール32′を通して、また駆動
用電源線24はスルーホール33′を通し多層配線部2
3二24#から入力側で端子の取り出しを行なっており
、これらの配線の取り出しには多層配線構造を用いてい
る。ここで、共通接地線や駆動用電源線は大きな電流容
量が必要なため配線幅を大きくせねばならずそのため多
層配線における交叉部の電流リークが生じる。In a thermal head that connects the input and output parts of a semiconductor device using a film carrier, in the conventional case, the common ground line 23 and driving power supply line 24 of the output transistor located in the output part are connected without complicated wiring. Logic circuit section 34
Since it is configured to be taken out to the input side through the wire, it is necessary to create a multilayer wiring structure on the semiconductor device. That is, the common ground line 23 is passed through the through hole 32', and the drive power supply line 24 is passed through the through hole 33'. Multilayer wiring section 2
Terminals are taken out from 3224# on the input side, and a multilayer wiring structure is used to take out these wirings. Here, since the common ground line and the drive power supply line require a large current capacity, the wiring width must be increased, which causes current leakage at the intersections in the multilayer wiring.
本発明は、上記従来の欠点に鑑み半導体装置の集積回路
の多層配線を少なくするためになされたものであり、バ
ンプを集積回路内の所定箇所に形成し、半導体装置の両
側に配置されたフィルムキャリアの導体部を前記バンプ
まで延長して多層配線回路の一部として利用するもので
あり、半導体装置の集積回路を簡略化できる。The present invention has been made in view of the above-mentioned conventional drawbacks in order to reduce the number of multilayer wiring in an integrated circuit of a semiconductor device. The conductor portion of the carrier is extended to the bump and used as part of a multilayer wiring circuit, and the integrated circuit of the semiconductor device can be simplified.
以下、図面をもとにして本発明の詳細な説明1 する。Detailed explanation of the present invention 1 below based on the drawings do.
第6図は本発明の一実施例におけるサーマルヘッドの半
導体装置およびその周辺の構成を示す平面図、第6図は
第6図のY−Y/断面図である。なおこれらの図におい
て従来例を示す第4図と同一箇所には同一番号を示して
いる。FIG. 6 is a plan view showing the structure of a semiconductor device of a thermal head and its surroundings in an embodiment of the present invention, and FIG. 6 is a YY/cross-sectional view of FIG. In these figures, the same parts as in FIG. 4 showing the conventional example are designated by the same numbers.
これらの図において、半導体装置7の上面には従来の場
合と同様に出力トランジスタ部32.出カドライブ部3
3.ラッチ、シフトレジスタ等で構成される論理回路部
34および入力回路部36より准る集積回路が形成され
ている0この実施例の特徴は、出力トランジスタ部32
.出カドライブ部33.入力端子25にそれぞれノ(ン
プ61z53’、25’を設け、これらのバンプ間をフ
ィルム・キャリアの導体部C以下フィンガーとよぶ)に
よって電気的に接続していることである。具体的には、
出力トランジスタ部32における接地用のバンプ61′
と入力端子26のバンプ26′とは、入力端子25よシ
延長されたフィンガー62によって電気的に接続され、
また出力ドライブ部33における信号電圧vcc印加用
のバンプ63′と入力端子26のバンプ25’とは、フ
ィンガー64によって電気的に接続されている。In these figures, the upper surface of the semiconductor device 7 has an output transistor section 32. as in the conventional case. Output drive section 3
3. An integrated circuit is formed from a logic circuit section 34 and an input circuit section 36, which are composed of latches, shift registers, etc. The feature of this embodiment is that the output transistor section 32
.. Output drive section 33. The input terminal 25 is provided with bumps 61z53' and 25', respectively, and these bumps are electrically connected by conductor portions C of the film carrier hereinafter referred to as fingers. in particular,
Grounding bump 61′ in the output transistor section 32
and the bump 26' of the input terminal 26 are electrically connected by a finger 62 extending from the input terminal 25,
Further, the bump 63' for applying the signal voltage vcc in the output drive section 33 and the bump 25' of the input terminal 26 are electrically connected by a finger 64.
ここで各バンプ間を電気的に接続するフィンガーは、突
出したバンプによって上方に持ち上げられているため、
バンプ以外の部分で半導体装置上の集積回路と接触する
ことはなく短絡等の不良は発生しない。Here, the fingers that electrically connect each bump are lifted upward by the protruding bumps, so
There is no contact with the integrated circuit on the semiconductor device at any part other than the bumps, and defects such as short circuits do not occur.
なお、バング51′と25’は第6図に示すようにそれ
ぞれ拡散防止層61′および25′を介して接地用端子
61および入力側端子26上にそれぞれ形成され、これ
らの端子61および26とそれぞれ電気的に接続されて
いる。Incidentally, as shown in FIG. 6, the bangs 51' and 25' are formed on the grounding terminal 61 and the input side terminal 26 through diffusion prevention layers 61' and 25', respectively, and these terminals 61 and 26 are connected to each other. They are electrically connected to each other.
一方、出力側端子21上に拡散防止層21′を介して形
成されたバンプ21’は、発熱抵抗体側の分離電極6と
フィルムキャリア導体部1oにより電気的に接続されて
いるが、この構成は従来のものと同様である。On the other hand, the bump 21' formed on the output side terminal 21 via the diffusion prevention layer 21' is electrically connected to the separation electrode 6 on the heating resistor side by the film carrier conductor part 1o. It is the same as the conventional one.
なお、61は多層配線部の層間絶縁層、62は保護絶縁
層、23’;24’は第2層目の導体層を示す。Note that 61 is an interlayer insulating layer of the multilayer wiring section, 62 is a protective insulating layer, and 23' and 24' are second conductor layers.
上記実施例のサーマルヘッドは以下に列挙するような利
点を有する。The thermal head of the above embodiment has the following advantages.
0)半導体装置7における出力部側の配線を入0
先部側より取り出す構成として、出力部側の配線部近傍
に設けたスルーホールバンプまでフィルムキャリアの導
体部を延長させ、この導体部を配線として利用している
ため、半導体装置内の多層配線を簡略化でき、半導体装
置の歩留を大幅に向上させられる。0) In a configuration in which the wiring on the output side of the semiconductor device 7 is inserted and taken out from the tip side, the conductor part of the film carrier is extended to the through-hole bump provided near the wiring part on the output side, and this conductor part is connected to the wiring. Since it is used as a semiconductor device, multilayer wiring within a semiconductor device can be simplified, and the yield of semiconductor devices can be greatly improved.
@)バンプ間を橋わたしするフィルムキャリアの導体部
は、幅、厚みが大きいため接地線等の電力系配線として
有効に利用できる0そのため、従来半導体集積回路にお
いて幅の広い導体配線を用いていたために生じる第1層
と第2層間の電流のリークによる故障を防止でき゛る。@) The conductor portion of the film carrier that bridges between bumps has a large width and thickness, so it can be effectively used as power system wiring such as grounding wires. Therefore, conventionally, wide conductor wiring was used in semiconductor integrated circuits. Failures caused by current leakage between the first layer and the second layer can be prevented.
第1図は従来のサーマルヘッドの平面図、第2図は同サ
ーマルヘッドのx−x’断面図、第3図はサーマルヘッ
ドの電気配線を示す図、第4図は従来のサーマルヘッド
における半導体装置の周辺の結線状態を示す図、第6図
は本発明の一実施例における半導体装置周辺の結線状態
を示す図、第6側は第6図のY −Y/断面図である。
1−・・・・・放熱用基台、2・・・・・耐熱性絶縁基
板、3・・・・・・発熱抵抗体、7・・・・・・半導体
装置、10゜10’・・・・・・フィルムキャリア、”
11・・・・・・多層配線板、21126161′、6
3′・・・・・・バンブ、52゜54・・・・・・フィ
ルムキャリアの延長した導体部。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第、2 図
第3図
第4図Figure 1 is a plan view of a conventional thermal head, Figure 2 is a sectional view taken along line xx' of the same thermal head, Figure 3 is a diagram showing the electrical wiring of the thermal head, and Figure 4 is a semiconductor in a conventional thermal head. FIG. 6 is a diagram showing the wiring state around the semiconductor device in an embodiment of the present invention, and the sixth side is a Y-Y/cross-sectional view of FIG. 6. 1-...Base for heat dissipation, 2...Heat-resistant insulating substrate, 3...Heating resistor, 7...Semiconductor device, 10°10'...・・・Film carrier,”
11...Multilayer wiring board, 21126161', 6
3'... Bump, 52° 54... Extended conductor part of the film carrier. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4
Claims (3)
半導体装置と、多層配線板とを放熱用基台上に配列し、
前記発熱抵抗体と半導体装置間および前記発熱抵抗体と
多層配線板間の電気的接続をフィルムキャリアを用いて
行なうとともに、前記半導体装置の集積回路の所定部に
スルーホール珀バンプを設け、前記フィルムキャリアの
導体部を前記バンプまで延長させて前記半導体装置の回
路配線の一部としたことを特徴とするサーマルヘッド。(1) A heat-resistant i-edge substrate on which a row of heating resistors is formed;
A semiconductor device and a multilayer wiring board are arranged on a heat dissipation base,
Electrical connections are made between the heating resistor and the semiconductor device and between the heating resistor and the multilayer wiring board using a film carrier, and through-hole bumps are provided at predetermined portions of the integrated circuit of the semiconductor device, and the film A thermal head characterized in that a conductor portion of the carrier extends to the bump and becomes part of the circuit wiring of the semiconductor device.
子を有するとともに他方端に信号系および電力系の入力
端子を有しておシ、少なくとも前記電力系の入力端子に
設′けられたバンプにフィルムキャリアの導体部が延長
されて電゛気的に接続されている−とを特徴とする特許
請求の範囲第・項一、載のサーマルベッド。 2 ・(2) The semiconductor device has a multi-bit output terminal at one end thereof and input terminals for a signal system and a power system at the other end, and at least the input terminal for the power system is provided. The thermal bed according to claim 1, characterized in that a conductor portion of the film carrier is extended and electrically connected to the bump. 2 ・
子としたことを特徴とする特許請求の範囲第2項記載の
サーマルヘッド。(3) The thermal head according to claim 2, wherein the input terminal of the power system is a ground terminal into which the head current flows.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14680181A JPS5845974A (en) | 1981-09-16 | 1981-09-16 | Thermal head |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14680181A JPS5845974A (en) | 1981-09-16 | 1981-09-16 | Thermal head |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5845974A true JPS5845974A (en) | 1983-03-17 |
Family
ID=15415833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14680181A Pending JPS5845974A (en) | 1981-09-16 | 1981-09-16 | Thermal head |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5845974A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61102862A (en) * | 1984-10-25 | 1986-05-21 | Hitachi Ltd | thermal recording head |
JPS6356546A (en) * | 1986-08-26 | 1988-03-11 | Sumitomo Chem Co Ltd | Peelable protective film |
JPH08220U (en) * | 1995-05-22 | 1996-02-06 | 三洋電機株式会社 | Drive element connection body |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5613187A (en) * | 1979-07-12 | 1981-02-09 | Matsushita Electric Ind Co Ltd | Thermal head |
-
1981
- 1981-09-16 JP JP14680181A patent/JPS5845974A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5613187A (en) * | 1979-07-12 | 1981-02-09 | Matsushita Electric Ind Co Ltd | Thermal head |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61102862A (en) * | 1984-10-25 | 1986-05-21 | Hitachi Ltd | thermal recording head |
JPH0511458B2 (en) * | 1984-10-25 | 1993-02-15 | Hitachi Ltd | |
JPS6356546A (en) * | 1986-08-26 | 1988-03-11 | Sumitomo Chem Co Ltd | Peelable protective film |
JPH0518341B2 (en) * | 1986-08-26 | 1993-03-11 | Sumitomo Kagaku Kogyo Kk | |
JPH08220U (en) * | 1995-05-22 | 1996-02-06 | 三洋電機株式会社 | Drive element connection body |
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