JPS5840919A - Voltage comparator - Google Patents

Abstract

PURPOSE:To realize the discrimination of voltage difference less than several V, by providing an FF having a means to lower the source electrode to a differential amplifier containing a transistor (TR) having a drain electrode connected to a gate electrode of a different polarity from a signal input TR as its load. CONSTITUTION:A differential amplifying circuit 14 has TRs M13 and M14 having different polarities from input TRs M2 and M3 with the gate and drain electrodes connected together. The TRs M10 and M11 having the same polarity as the TRM13 are connected cross to the load drain electrode of the circuit 14. A flip-flop (FF)15 having a means to lower a common source node 16 is connected to the circuit 14. When the potential of an input terminal 2 is higher than that of an input terminal 3, an output terminal 6 has a higher potential than an output terminal 5. Then the pulse is applied to a terminal 17, and as a result a TR12 conducts. Thus the potential at the node 16 drops, and the FF15 is activated to lower the voltage of the terminal 6. However, the voltage of the terminal 5 has virtually no change.

Description

Detailed Description of the Invention The present invention is mainly used in semiconductor integrated circuits with a complementary layer insulating layer F structure, such as MU/D converters. This invention relates to a voltage comparator circuit suitable for outputting nine logic voltages.

Conventionally, as shown in No. 111, a voltage comparator circuit used in a semiconductor integrated circuit having a complementary insulated gate configuration uses Ml as a constant current source, Ml and M3 as input transistors, and M4 as shown in FIG.
, MS is configured as a current mirror load, and an output voltage proportional to the difference between the voltages applied to terminal λ3 is outputted from terminals 6 and 9 by a differential amplifier circuit, and M6 is a constant current load. An amplification circuit having a membrane configuration was used for further amplification by an inverting amplifier 11.

Symbols used in this application, including FIG. 1, are defined as P-channel transistors in Figure 2 (→) and 9!-channel transistors in Figure 2 (BL).

The gate is denoted by G, the source D is denoted by S, and the drain is denoted by G. This two-stage amplifier circuit usually provides a gain of 2000 to 5000 times, but
In order to obtain margin for gain, one stage of inverting amplification @12 is usually added. Reference numeral 13 denotes a bias voltage supply device for operating M1 and M6 in a constant current region ζ, which is realized, for example, by the circuit shown in FIG. The circuit in Figure 3 is a MOS) transistor with its gate electrode and drain electrode! ! Three so-called diode-connected transistors are connected in series to divide the power supply voltage applied between terminals 1 and 9.
It is.

In such a voltage comparator circuit, as the input voltage difference decreases, the number of amplification stages must be increased accordingly, resulting in an increase in the occupied area O in the integrated circuit and an increase in power consumption. Furthermore, the common-mode voltage rejection of the first RO differential amplifier cannot be said to be perfect; if the common-mode component of the input voltage changes, the node/O output voltage changes, and this voltage is amplified by the inverting amplifier. In a pigeon house with a voltage difference of several volts or less, depending on the common mode voltage, the state of logic @l'' and the state of logic ''O# may be switched at the output of the final stage. 1+, the same phenomenon occurs when the power supply voltage fluctuates. Therefore, such a voltage comparator circuit has a drawback that it is impossible to distinguish a difference in the order of magnitude or less when the common mode component of the input voltage is large.

The present invention aims to eliminate such drawbacks and realize a highly sensitive voltage comparator circuit with a reduced number of elements.

The present invention provides a differential amplifier having as a load a transistor whose gate electrode and drain electrode are connected to each other with a different polarity than that of the signal input transistor, and a differential amplifier whose load transistor has the same polarity as the load transistor.
)? a flip-flop circuit having means for cross-coupling two transistors and intermittently lowering their common source electrode to the ground potential of the load transistor; The two drain electrodes are connected to the drain electrodes of the differential amplifier load, respectively, and when the potential intermittently decreases, the differential amplifier l! The voltage comparator circuit is designed to obtain a sufficient output voltage as a logic output at the output terminal of the differential amplifier according to the magnitude of the input voltage of the differential amplifier.

The present invention will be described below with reference to FIG. 4, which shows an example of a specific circuit, and FIG. 5, which shows an example of the timing of the voltage applied to the terminal 17.

What is shown in FIG. 4 is an example of the implementation of the invention in the main building 1.

Signal input transistor M2, MS and constant current source M1
1 to 7) Connect the drain electrode of the P-channel transistor MIID to the source electrode of M2 and MS using the channel transistor, the source electrode of Ml is connected to the positive power supply, and the MIO gate electrode is connected to the source electrode of M2 and MS through node 4. /(A constant current source is configured by connecting to the IAsumi pressure generator 13 and applying a constant voltage. So-called diode-connected two-channel transistors M13 and M14 serve as loads to the drain electrodes of M2 and M30, respectively. A differential amplifier is configured by these.M
l3. The drain electrode of Ml4 is outputted to the outside as an output terminal 5.6, and the output terminal 5 is connected to the gate electrode of the z channel transistor MIO and the drain electrode of the duck channel transistor Mll.
The drain electrode of MIO and the gate electrode of Mll are connected to form a cross-coupling), MIO and Ml
A social channel transistor M1 is connected to the lO common source electrode.
The drain electrode of Ml2 is connected to 71, the source electrode of Ml2 is connected to a negative power supply, and the gate of Ml2 is connected via terminal 17 to a device that generates pulse "A" in FIG. ni MIO! A differential amplifier circuit with a diode-connected transistor as the load as shown in FIG. The gain is several minutes e compared to that of an amplifier.
)1) and the common-mode rejection ratio is also poor, which was considered to be a drawback, so this circuit configuration has never been pursued as an analogue of a semiconductor integrated circuit with a complementary insulated gate configuration.

However, the 4E15 79-tube flop of the present invention is
The inventor's idea is that the rounding gain caused by positive feedback is infinite, and the common-mode rejection effect is also very large, so the above-mentioned drawbacks are no longer a problem.In fact, as a result, as will be described later, It was previously expected that the return to the differential amplifier would be faster after the voltage comparison was performed, but we were able to obtain the large 1'& 0.0 points, which had not been achieved.

Now, when the 51st ilK is shown, it will be explained from the 1asso state.

At time -, the pulse "I" is in the zero state, and at the input terminal λ3 in FIG. 4, the voltage 0 of 2 is higher than the voltage 30.

Then, the current aM2 flowing through M3 becomes larger. Therefore, the voltage at the output end 6 becomes higher than the voltage at the output end 5.

This voltage difference is usually several times to 10 times the input voltage difference.At this time, the voltage at node 160 is smaller than the threshold voltage at node 6. The voltage is lower than the voltage at the output terminal 6 by the threshold voltage of the channel/channel transistor. If this difference is large (like the threshold voltage), s becomes equal to the voltage at the lower output terminal 5 of 10. This is MIO, Mll
are the output terminal 6 voltage O source 7 O 7 circuits. Next, when the pulse "I" rises at time mt, M12 becomes conductive and the voltage at node 16 drops.
0 tube is activated, Mll conducts first, and the output terminal 60
Drop the voltage. As the node 16 descends, the output t
Since a6 drops, the current flowing through MIG is much smaller than the current flowing through Mll, so the output terminal 5 maintains approximately the voltage before the pulse "I" was applied. Here, in order to make the final voltage on the low voltage side sufficiently low (as compared to the channel transistor 0@value voltage), the quotient (W/L) obtained by dividing the channel width by the channel length for MIO and M12 is set as M4 and M5'). It is desirable that the value be five times or more the value obtained in the same manner. In the voltage comparator circuit shown in FIG. 4, before applying the pulse "A", the differential amplifier 14 must be a pure differential amplifier or the output terminals 5 and 6 must be at equal potential. No. When the pulse "I" falls at time -, M12 turns off, and no current flows through the flip 70 knob. At this time, M14 is off, so M3
All current flowing through the circuit is used for rounding the charge. Even if the output terminal 5 exceeds the threshold voltage and M14 becomes conductive, M14 remains at the output terminal 5.
The differential amplifier II can be returned to the O state in a short time (with M14 as the load), which has the characteristic that as the voltage increases, the resistance decreases. Even if the input voltages are reversed, this circuit is symmetrical and operates in the same way.

Now, in the case of such a voltage comparator circuit, it is not only quick to return to the state of operating as a differential aS after voltage comparison, but also
j! It may be difficult to operate at high speed. It is also possible to adapt the method in an advanced manner to the case of the 11 companies according to the present first sIA Akira. What is shown in FIG. 6 is an example of the implementation of WJ4 from the 20th issue of this book, which was finally obtained).In the 4110In path, the source and drain of the transistor MISII are connected to the output terminals s and s, respectively. te>11, M
The fifth pulse is applied to the gate terminal 18 of 2S. As shown in No. 511, when the pulse "I" falls at the timing of time -, and the pulse "A" rises to break the conduction of Mls, the voltage of the output terminal 6 becomes equal. 31, just before Mis becomes conductive. The voltage of the rod 6 is approximately the average O voltage. Next, when the pulse is lowered, M
Since the difference between the currents flowing into the terminals 5 and 5 and M3 is proportional to the voltage OII input to the terminal λ3, the output terminal 0 connected to the resistor (with the lower input voltage)
Since the voltage rises first in the first case, the next voltage comparison can be made immediately.

[Brief explanation of the drawing]

Figure 1 shows the conventionally used differential increase @510 and inversion layer @
A voltage comparator circuit with nine voltage comparators using devices 11 and 12 is used, and 13 is output. gsl! This is an example of one circuit of a bias voltage supply device manufactured by one company. FIG. 4 This is an embodiment of the nine inventions shown in Clause 1 of the claims.
, FIG. 6 is an embodiment of the invention shown in Section 2 of the present claim. Figure 5 shows an example of the pulse timing and output waveform supplied to each figure tij14all and Figure 6. In the figure, MXX is a transistor, and only numbers are shown. What is attached is a node or terminal. l+T Object I Note 3 Diagram No. zU Nest 4 Mouth $51￥El t, t, t,, t/. 61st

Claims (1)

[Claims] 1. A differential amplifier having a transistor as a load whose gate electrode and drain electrode are connected to each other with a different polarity from that of the input transistor, and a transistor whose polarity is the same as that of the load transistor are cross-coupled to form a common source. a flip-flop circuit having means for intermittently lowering the electrodes to the zero ground potential of the load transistor; and a flip-flop circuit using complementary insulated gate transistors, and connecting two drain electrodes of the flip-flop to the differential voltage. A voltage comparison circuit connectable to a drain electrode of an amplifier load. 2. A differential amplifier whose load is a transistor whose gate electrode and drain electrode are unified with the polarity different from that of the input transistor, and a transistor 2 whose polarity is the same as that of the load transistor.
a flip-flop circuit having means for cross-coupling the two flip-flops and intermittently lowering the common source electrode thereof to the ground potential of the load transistor; are connected to the drain electrodes of the differential amplifier loads, respectively, and further includes means for forcibly equalizing the drain potentials of the first load transistor in synchronization with the intermittently lowering common source electrode potential of the flip-flops. A voltage comparator circuit with 41 features.