JPS5840203B2 - Power control circuit for electronic equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply control circuit for electronic equipment, and in particular, in electronic equipment including an arithmetic processing unit, a reset signal given to the arithmetic processing unit when the power is turned on or off is
] The present invention relates to a power supply control circuit.

For example, an arithmetic processing device such as a microcomputer is provided with a program counter for specifying the address of a read-only memory that stores a program.

This program counter is configured to be reset by a power supply reset signal and return to the initial state when the power is turned on.

Then, when the program counter returns to its initial state, the instruction word at the first address stored in the read-only memory is read out, and an operation is executed based on the instruction word.

Therefore, the power reset signal is essential for the CPU, and if the power reset signal is not given when the power is turned on, the program counter will not be reset to its initial state. It becomes impossible to know which instruction is to be read from which address in the ROM, which causes an abnormality in the operation of the CPU.

Further, when the DC voltage applied to the CPU becomes lower than the minimum voltage necessary for the operation of the CPU, the CPU immediately stops operating.

However, in random access memory, etc., when the power is cut off, the previously stored data is erased, so it is necessary to transfer the previously stored data to nonvolatile memory when the power is cut off. .

Furthermore, in line printers and the like, it may be necessary to print, for example, one line of data when the power is turned off.

Therefore, the present invention provides an electronic device that reliably resets the processing unit when the power is turned on, and that enables necessary processing without stopping the operation of the processing unit immediately when the power supply drops below a predetermined voltage. Its purpose is to provide power supply control circuits for equipment.

In summary, the present invention detects a first voltage necessary for constant voltage operation of a DC constant voltage power supply for supplying DC voltage to an arithmetic processing unit, and a second voltage higher than the first voltage. Then, based on the detection of the second voltage, the arithmetic processing unit is brought into a reset release state.

Then, the external device is controlled to be operable only from the time when the operation command signal is derived from the arithmetic processing unit until the power supply voltage drops and the first voltage is detected.

The present invention will be described in more detail below along with embodiments shown in the drawings.

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention.

In the configuration, an AC input is provided to a rectifier 1 and rectified into a DC voltage.

This direct current voltage is not a complete direct current but includes an alternating current component, and is supplied to the direct current stabilizing circuit 2, where it is regulated to a complete direct current voltage of, for example, 5 cm.

Further, the voltage rectified by the rectifier 1 is applied to a first detection circuit 3 and a second detection circuit 4.

The first detection circuit 3 includes a Zener diode 31, a transistor 32, and resistors 33-35.

This detection circuit 3 detects the minimum voltage of the DC voltage rectified by the rectifier 1 necessary for the operation of the DC stabilization circuit 2. This minimum voltage PFl may be set to, for example, about 16V. The detection signal of the detection circuit 3 is applied to the reset input terminal of a flip-flop 6 as state storage means.

The second detection circuit 4 includes a Zener diode 41, a transistor 42, and resistors 43-45.

This second detection circuit 4 detects a voltage PF2 (
For example, it detects when the
The detection signal is applied by an inverter 5 to one input terminal of the AND gate door.

Further, this detection circuit 4 provides a detection signal as an interrupt signal when the rectified voltage becomes lower than the detection voltage PF2.

The input terminal of the AND 7 is supplied with the output of the flip-flop 6, and the output signal of the AND gate 7 is supplied via the OR gate 8 to the reset input terminal of the CPU 9.

Further, the Q output of the flip-flop 6 is applied to a reset input terminal of the CPU 9 via an OR gate 8, and is also applied as an enable signal to a memory 10 and a printer 11 as external devices.

This flip-flop 6 is set by a program start command signal as an operation command signal given from the CPU 9 when the detection circuit 4 gives an interrupt signal to the CPU 9.

FIG. 2 is a waveform diagram for explaining the operation of an embodiment of the present invention.

Next, the specific operation of one embodiment of the present invention will be described with reference to FIGS. 1 and 2.

When an input is applied to the rectifier 1, the rectifier 1 rectifies the AC input into a DC voltage.

The rectified output of the rectifier 1 gradually rises as time passes, as shown in FIG. 2a.

In addition, the DC stabilizing circuit 2 increases the DC voltage of the rectifier 1 by +5■
Make the voltage constant.

At this time, flip-flop 6 has been reset,
The output is at a high level (hereinafter referred to as "■").

However, since the detection signal of the second detection circuit 4 does not detect the second detection voltage PF2, its output is rHJ
It has become.

This rHJ signal is inverted by the inverter 5 and becomes a low level (hereinafter referred to as "L").

Therefore, since AND gate 7 is not opened, "L"
A signal is given to the OR gate 8.

At this time, since the Q output of the flip-flop 6 is also "L", the OR gate 8 applies the rLJ signal (FIG. 2d) to the reset input terminal of the CPU 9 to reset it.

The rectified voltage of rectifier 1 further rises, and the detection voltage PFi
Then, the Zener diode 31 of the first detection circuit 3
becomes conductive, and a DC current flows through the resistor 33.

The voltage across resistor 33 is applied to the base of transistor 32, which turns on transistor 32' and brings its collector to the rLJ level (FIG. 2b).

Further, when the rectified voltage of the rectifier 1 rises and reaches the second detection voltage PF2, the Zener diode 41 of the second detection circuit 4 becomes conductive, and a direct current flows through the resistor 43.

When a DC current flows through the resistor 43, the voltage across it is applied to the base of the transistor 42.
is conductive.

As a result, the collector of transistor 42 becomes rLJ level (FIG. 2C), and this rLJ level signal is applied to inverter 5.

The inverter 5 inverts the "L" signal to the rHJ signal, and uses the rHJ signal as a reset release signal to the CPU 9.
give to

In response, the CCPU 9 sends a program start signal (Fig. 2 e
) is made conductive and the flip-flop 6 is set.

Thereby, the Q of the flip-flop 6 shown in FIG.
An H reset release signal is applied from the output terminal to the CPU 9 via the OR gate 8 .

At the same time, this reset release signal is given to the memory 10 and printer 11 as an enable signal.

Therefore, the CPU 9 is enabled to control the memory 10 and the printer 11 since the reset state is released.

As described above, the CPU 9 is reset by detecting the first detection voltage PF1 and then detecting the second detection voltage PF2, and the CPU 9 is kept in the reset state for the period T until the program start signal is derived from the CPU 9. Therefore, even if the power is suddenly turned on, the CPU 9 can be sufficiently reset.

Next, when the power is cut off due to, for example, a power outage, the rectified output of the rectifier 1 gradually falls as shown in FIG. 2a.

Then, when the rectified voltage reaches the second detection voltage PF2, the detection circuit 4 gives an interrupt signal at the normal level to the CPU 9, and inverts it by the inverter 5 to close the AND gate 7.

Thereby, the CPU 9 immediately transfers the data stored in the memory 10 to another non-volatile memory (not shown) or causes the printer 11 to print one line.

Then, when the rectified voltage of the rectifier 1 further decreases and the detection circuit 3 detects the first detection voltage PFi, the flip-flop 6 is reset.

By resetting the flip-flop 6, the Q output becomes H and the Q output becomes "L", so the CPU'
9 is given an L level reset signal.

This causes the CPU 9 to enter the reset state.

As described above, according to the present invention, it is detected that the DC voltage applied to the DC stabilizing circuit has reached the first voltage and the second voltage, and when the DC voltage reaches the second voltage, the CPU is Since the reset state is canceled when the operation command signal is derived from the CPU by applying the input signal, the CPU can be reliably brought into the reset state even if the power is suddenly turned on.

Furthermore, the memory can be saved 1 immediately when the input voltage of the DC stabilizing circuit falls to the second voltage.

[Brief explanation of drawings]

FIG. 1 is an electrical circuit diagram of one embodiment of the present invention, and FIG.
The figure is a voltage waveform diagram of each part in FIG. 1. In the figure, 1 is a rectifier, 2 is a DC stabilization circuit, 3 is a first detection circuit, 4 is a second detection circuit, 5 (1 inverter, 6 is a flip-flop, 7 is an AND gate, 8 is an OR gate, 9 1 is a processing unit, 10 is a memory, and 11 is a printer.

Claims (1)

[Scope of Claims] 1: an external device, a central processing means for controlling the external device, a rectifying means, and a DC voltage rectified by the rectifying means, which is supplied to at least the central processing means. A first step of detecting whether the output voltage of the rectifying means reaches a predetermined first voltage necessary for the DC voltage regulating means to operate at a constant voltage. 1 detection means, a second detection means for detecting whether the output voltage of the rectification means has reached a predetermined second voltage higher than the first voltage, and the first detection means The central processing means includes state storage means for storing a first logic state in response to detecting the first voltage, and the central processing means receives the regulated DC voltage from the DC voltage regulation means. In response to the detection of the second voltage by the second detection means, the initial reset is canceled, and the state storage means is stored in a second logic state, and the state is and means for maintaining an initial reset release state in response to the storage means being set to the second logic state, and providing the second logic state output of the state storage means to the external device as an activation signal. A power supply control circuit for electronic equipment, characterized by: