JPS5839034A - Forming method for electrode - Google Patents
Forming method for electrodeInfo
- Publication number
- JPS5839034A JPS5839034A JP13794581A JP13794581A JPS5839034A JP S5839034 A JPS5839034 A JP S5839034A JP 13794581 A JP13794581 A JP 13794581A JP 13794581 A JP13794581 A JP 13794581A JP S5839034 A JPS5839034 A JP S5839034A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- resist film
- overhangs
- protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置に於ける電極形成方法に関する。[Detailed description of the invention] The present invention relates to a method for forming electrodes in semiconductor devices.
半導体装置にアルミニウム等の電極を形成するに際して
レジストで描いたパターンと実際に形成される電極パタ
ーンとの間の差、即ち変換差を少くした電極の微細化に
適した方法としてリフトオフ加工が知られている。とこ
ろが電極材料としてアルミニウムを用いたりフトオ7加
工の場合、レジスト膜厚を極端に厚く、オーバーハング
等1〜なければならず、その結果、再現状の点で問題か
あった。Lift-off processing is known as a method suitable for miniaturizing electrodes by reducing the difference between the pattern drawn with resist and the actually formed electrode pattern, that is, the conversion difference when forming electrodes of aluminum etc. on semiconductor devices. ing. However, in the case of using aluminum as the electrode material or using foot-scanning, the resist film thickness must be extremely thick and there must be overhangs, etc., and as a result, there are problems in the current state of the art.
本発明はこのような問題点に鑑みて為されたものであっ
て、電極材料形成前に電極パターンの溝をその下部の表
面保護に形成し、す7トオ7加工で電極パターン形成す
るものである。The present invention has been made in view of these problems, and involves forming grooves for the electrode pattern on the surface protection of the lower part before forming the electrode material, and forming the electrode pattern by a 7-to-7 process. be.
本発明は図面を参照しつつ説明する以下−の記述から明
らかになるであろう。The present invention will become clearer from the following description with reference to the drawings.
本発明は第1図に示す構造の半導体装置を出発点として
いる。同図に於て、(1)はシリコン基板、(2)はフ
ィールド酸化膜、(3)はゲート絶縁膜、(4)はゲー
ト電極、(5)は半導体装置の表面を保護する表面保護
膜で、酸化シリコン膜或いはPSG等から成る。(6)
はこの表面保護膜(5)上に設けられたレジスト膜で、
電極を形成すべきパターンに従って骸保護膜(5声出し
ている。The present invention is based on a semiconductor device having the structure shown in FIG. In the figure, (1) is a silicon substrate, (2) is a field oxide film, (3) is a gate insulating film, (4) is a gate electrode, and (5) is a surface protection film that protects the surface of the semiconductor device. It is made of a silicon oxide film, PSG, or the like. (6)
is a resist film provided on this surface protection film (5),
The skeleton protective film (sounds 5 times) according to the pattern in which the electrodes are to be formed.
本発明の第1の工程は第2図に示す如くレジスらの一部
だν声系のエッチャントでウエットエッチングし、それ
と同時にレジスト膜(6)端部直下の保護膜を除去して
レジスト膜(6)の端部に庇部(力(力・・・を形成す
る。In the first step of the present invention, as shown in FIG. 2, a part of the resist film (6) is wet-etched using a V-tone etchant, and at the same time, the protective film immediately below the edge of the resist film (6) is removed, and the resist film (6) is 6) Forms an eave part (force (force...) at the end.
次工程は第2図で示された基板(1)の表面からアルミ
ニウム(8)をEB無蒸着スパッター等の方法!蒸着す
る(第6図)。この蒸着工程時に基板(1)を加熱せず
、蒸着速度を上げる事でアルミニウム膜(8)のステッ
プカバレージを僅かに悪くする。アルミニウム膜(8)
はレジスト膜(6)の側面、表面保護膜(5)の側面及
び同保護膜(5)の庇部(7)(力・・・には殆ど被着
されず、その結果、この庇部(7)(7)・・・には空
1!1(91(9)・・・が生じる。The next step is to sputter aluminum (8) from the surface of the substrate (1) shown in Figure 2 without EB deposition! Vapor deposition (Figure 6). During this vapor deposition process, the step coverage of the aluminum film (8) is slightly deteriorated by increasing the vapor deposition rate without heating the substrate (1). Aluminum film (8)
is hardly adhered to the side surfaces of the resist film (6), the side surfaces of the surface protection film (5), and the eaves (7) of the same protection film (5), and as a result, this eaves ( 7) (7)... has an empty 1!1 (91(9)...).
続いてアルミニウム膜(8)を僅かにエツチングしCレ
ジスト膜(6)の側面を完全に露出した後、レジスト制
離剤を用いてレジスト膜(6)を除去する。その結果、
第4図に示す如く、レジスト膜(6)上に存在したアル
ミニウム膜(8)も同時に除去され、ゲート電極(4)
上や表面保護膜(5)上のアルミニウム膜(8)のみが
残存し、これが最終的に半導体装置の電極となる。Subsequently, the aluminum film (8) is slightly etched to completely expose the side surfaces of the C resist film (6), and then the resist film (6) is removed using a resist release agent. the result,
As shown in FIG. 4, the aluminum film (8) present on the resist film (6) was also removed at the same time, and the gate electrode (4)
Only the aluminum film (8) on the top and surface protection film (5) remains, which will eventually become the electrode of the semiconductor device.
護膜に庇部を形成しているので、電極材料の分離が容謳
に行え、配線等の微細化が可能となるっSince the protective film has an overhang, it is possible to easily separate the electrode material, making it possible to miniaturize wiring, etc.
第1図乃至第4図は本発明電極形成方法を工程順に示し
た断面図であって、(1)は基板、(5)は表面保護膜
、(6)はし′−)スト膜、(7)は庇部、(8)はア
ルミニウム膜、・を夫々に示している。1 to 4 are cross-sectional views showing the method of forming an electrode according to the present invention in the order of steps, in which (1) is a substrate, (5) is a surface protective film, (6) is a strip film, ( 7) shows the eave portion, and (8) shows the aluminum film.
Claims (1)
形成するパターンに従って該保映膜を露出したレジスト
膜を設け、該レジスト膜にて露出された保護膜の表面か
らの一部をエツチングする事に依ってレジスト膜端部直
下の保MWをも除去してレジスト膜を庇状とし、その庇
状レジスト膜の直上から電極材料を被着して後、レジス
ト膜を除去する事を特徴とした電極形成方法。1) A resist film exposing the reflective film is provided according to a pattern for forming an electrode on a surface protective film that protects the surface of a semiconductor device, and a part of the surface of the protective film exposed by the resist film is etched. The resist film is characterized by removing the retained MW directly under the edge of the resist film to make the resist film into an eave-like shape, depositing an electrode material directly above the eave-like resist film, and then removing the resist film. Electrode formation method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13794581A JPS5839034A (en) | 1981-09-01 | 1981-09-01 | Forming method for electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13794581A JPS5839034A (en) | 1981-09-01 | 1981-09-01 | Forming method for electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5839034A true JPS5839034A (en) | 1983-03-07 |
Family
ID=15210371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13794581A Pending JPS5839034A (en) | 1981-09-01 | 1981-09-01 | Forming method for electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5839034A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030045574A (en) * | 2001-12-04 | 2003-06-11 | 엘지이노텍 주식회사 | Method of metal electrode patterning |
-
1981
- 1981-09-01 JP JP13794581A patent/JPS5839034A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030045574A (en) * | 2001-12-04 | 2003-06-11 | 엘지이노텍 주식회사 | Method of metal electrode patterning |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS61171131A (en) | Formation of patterned conductive layer on semiconductor | |
JPS5839034A (en) | Forming method for electrode | |
JP2821623B2 (en) | Method for manufacturing semiconductor device | |
JP2842405B2 (en) | Method for manufacturing semiconductor device | |
JPS5825229A (en) | Manufacture of semiconductor device | |
JP2002141762A (en) | Manufacturing method for surface acoustic wave filter | |
JPS6059742B2 (en) | Semiconductor device and its manufacturing method | |
JPS6130418B2 (en) | ||
JPS5952542B2 (en) | Manufacturing method of semiconductor device | |
JPS58192338A (en) | Semiconductor device and its manufacturing method | |
JPS60154539A (en) | Forming process of aluminium wiring | |
JPS6064435A (en) | Manufacture of semiconductor device | |
JPS58137215A (en) | Etching method of insulating film for semiconductor device | |
JPS5815253A (en) | Manufacture of electrode of semiconductor device | |
JPS6386453A (en) | Manufacture of semiconductor device | |
JPS5984442A (en) | Manufacture of semiconductor device | |
JPS6028237A (en) | Manufacture of semiconductor device | |
JPH01161769A (en) | Memory cell having two-layer polysilicon structure | |
JPS6362104B2 (en) | ||
JPH07245286A (en) | Method for manufacturing semiconductor device | |
JPH04144228A (en) | Manufacture of semiconductor device | |
JPS5843540A (en) | Wiring formation in semiconductor device | |
JPS5885547A (en) | Forming method for conductive pattern | |
JPS63287037A (en) | Manufacture of semiconductor device | |
JPH0748518B2 (en) | Method for manufacturing semiconductor device |