JPS5837898A - Peak holding circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution and to attain a high-speed operation with high accuracy for a peak holding circuit, by charging a peak holding capacitor via an emitter follower and performing a process with a differential amplifier which receives a feedback control via the emitter follower. CONSTITUTION:For a transistor TRQ1 forming an emitter follower, a capacitor C which is controlled in accordance with an input is charged in response to the input peak. This charged voltage is applied to a noninverse input terminal of a differential amplifier A which receives a feedback control via a TRQ2 forming an emitter follower. Thus the number of feedback stages is decreased along with an amplifying stage. In such way, the holding of the peak value is possible at a high speed and high accuracy through a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a peak hold circuit that operates at high speed and with high precision.

A peak hold circuit that holds the peak value of an analog waveform is useful, for example, when performing MU/D conversion on the output of a MOS image sensor. Since the output of the image sensor itself is a pulse train with an extremely narrow pulse width, it is necessary to convert the peak value of each pulse into a digital value and store it in memory, or to display the peak value on a tester at high speed. An operable and highly accurate peak hold circuit is required. Figures 1 and 2 show different examples of conventional peak hold circuits, where Al e AM is a differential amplifier, C is a capacitor for peak hold, SW is a reset (discharge) switch, and D is a low output impedance. This is a diode that prevents the charge of the capacitor C from discharging to the differential amplifier AI side.

Both circuits are the first differential amplifiers! non-inverting input terminal (
G) Apply the K input voltage vtt-, charge the capacitor Ct with its output, and further apply the terminal voltage of the capacitor C to the non-inverting input terminal of the second differential amplifier AI (g) K to obtain the output voltage Voi. The same thing is true, but I'm happy 1
In the circuit shown in the figure, the output voltage Vo k is fed back to the inverting input terminal θ of the amplifier Al e AN. Differential amplifier A! If the mA gain is extremely large, the voltage at both the inverting and non-inverting edges will be tl, so in Figure 1, Vi=V.

However, since feedback is required from the output stage M to the input stage AI, it is difficult to expect stable high-speed operation. On the other hand, in the circuit shown in Fig. 2, each amplifier Al e AI only individually constitutes a feedback loop, so high-speed operation is possible.
The output of AI is approximately the charging voltage of v11 capacitor C, so the input voltage is approximately Vi-VF, and the output VO of AI is also approximately Vi-VF, and the peak value of input Vi and output Vo
An error corresponding to the forward voltage VF of the diode D occurs between the two. Therefore, it is difficult to use when high precision operation is expected. In this way, the circuits shown in FIGS. 1 and 2 sacrifice either speed-up or high-precision operation.

The present invention provides a peak hold circuit which is capable of high precision and high speed operation with a simple configuration. Then, the terminal voltage of the capacitor is applied to the non-inverting input terminal of the differential amplifier, and the second
The transformer pressure t of the differential amplifier is connected to be fed back to the inverting input terminal of the differential amplifier, and a reset switch is further provided to discharge the charge of the capacitor, see the embodiment shown below. This will be explained in detail.

FIG. 3 is an embodiment of the present invention, which is an example of a circuit for holding a positive voltage. Ql is the first npn transistor, whose collector is connected to a positive power supply, e.g. +15V, through the resistor R1.
)K connected. This transistor QI is used as an emitter follower, and the capacitor C is charged by the input voltage ViK through its base and emitter. The terminal voltage of the capacitor C with respect to ground is given to the non-inverting input (K) of the differential amplifier A.The output VO of this differential amplifier A is applied to the open terminal of tJIE2 connected as an emitter follower.
)B is fed back to the inverting input terminal θ through the transistor (ht).Specifically, the series resistors VR and R are connected from the output terminal of the differential amplifier A through the base and emitter of the transistor.
An electric current is applied to the amplifier, and the voltage generated at the sliding end of the edible resistor VR is applied to the inverting input terminal θ of the amplifier. Furthermore, transistor Q! The collector of is connected to the positive power supply v''K*, and the variable resistor VR and the resistor - are connected in series between the emitter of the transistor and the negative power supply v- (for example, -15V).The reset switch sw is MJK* is connected between the high potential side of the capacitor C and the negative power supply V-, and is periodically turned on and off by the reset pulse R8T.

FIG. 4 is a waveform diagram of each part, and the reset pulse R8T is generated in synchronization with the clock signal that receives the input v1.

Then, the switch SW is turned on while the pulse R8T is L (low) to discharge the charge in the capacitor C (reset).
. Also, during the period when pulse R8T is H (hey), switch SW
Since the switch SW is off, the capacitor C is charged with the input voltage Vt, and this value is held until the next switch/chip SW is turned on. In this circuit, R1 = R + VR %R May) VR
Set up the IC and set the voltage between the base and emitter of the transistor Qz - (h is the same type, Vlllly V
Make i+g snow' equal. The charging voltage of capacitor C is V
l −Vmm, which is input to the ten terminal of amplifier A, so the voltage at one terminal of the amplifier is also Vi−vl! , resistance VRI
Ignoring the partial pressure effect due to C, the output Vo rises by the voltage V1 of Q snow, which is 9V1-Vm = Vi. In this way, the drop of the transistor 9, Vm is compensated by the drop of the transistor Q, and the output '
Since Vo becomes Vi, no error occurs, and since only one stage of differential amplifier A is used, the configuration is simple.
Shikamo feedpa.

Since the process is performed only in that stage, high-speed operation is possible. The vRt-potentiometer type variable resistor is used because of the offset amount of amplifier A (this amplifier operates with positive and negative power supplies, and the output Vo when unmanned is at zero level, but this level varies slightly depending on the amplifier). Up and down.Output Vof
The input voltage that brings it to zero level is called the offset voltage) t-
This is to enable adjustment. Moreover, if ~ is also made into a variable resistor, the error between Vmml and Vmml can be corrected by changing the current flowing between the base, emitter, and rib of the transistor Q.

! Fig. 5 shows another embodiment of the present invention applied to negative voltage hold, and differs from Fig. 3 only in that the transistor Qt*QstP gap type is used, and the positive and negative power supplies V''ev- are switched. Since the operation can be considered in the same way as shown in FIG. 5, voltage waveforms at various parts are shown in FIG. 6 and detailed explanation will be omitted.

As described above, according to the present invention, there is an advantage that a peak hold circuit that can operate at high speed and with high precision can be realized with a simple configuration.

[Brief explanation of drawings]

FIGS. 1 and 2 are circuit diagrams showing different examples of conventional peak hold circuits, FIGS. 3 and 4 are circuit diagrams and waveform diagrams showing an embodiment of the present invention, and FIGS. 5 and 6 2 is a circuit diagram and a waveform diagram showing another embodiment of the present invention. FIG. Q in the diagram! -Qs are the first and second transistors, C is the peak hold capacitor, A is the differential amplifier, VR
e-R is a series resistor, SW is 1 reset, switch for G, and switch for H. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 1 Figure 3 v1FIST V- Figure 4 Hold Lit Figure 5' Figure 6 Hold 'Rimmato

Claims (1)

[Claims] A peak hold capacitor is charged with the input voltage through the first transistor connected as an emitter follower, and the terminal voltage of the capacitor is applied to the non-inverting input terminal of the differential amplifier. A reset process in which a current is passed from the output terminal of the differential amplifier to a series resistor, a voltage divided by the series resistor is returned to the inverting input terminal of the differential amplifier, and the charge in the capacitor is discharged. A peak hold circuit characterized by having a switch and a switch.