JPS5834003B2 - How to check signal integrity - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for ensuring data integrity of a data signal during a signal transfer operation, in particular a signal transfer operation using a recording step.

Data storage devices for automatic data processing machines take a variety of forms and have correspondingly different data storage capabilities.

There continues to be a strong trend to increase the storage capacity of data storage devices.

In particular, data storage devices that are under the full control of automatic data processing machines offer many economic benefits to the user.

This is because human intervention is reduced to a minimum, thereby increasing the efficiency of the data processing system.

Even with such nearly error-free automatic data storage, the need for data integrity and the absence of undetected data errors is limited.
This continues to be the greatest demand for data processing equipment.

A relatively large capacity data storage device is IBM's Model 3850 Mass Storage System (hereinafter abbreviated as MSS).

This fully automated, on-line data storage has two levels of data storage and a single address field.

The first level (or staging level) is direct access storage (DA) using disk storage.
(abbreviated as SD).

As such, ASDs enable fast access to data recording and data sets and are therefore gaining popularity in data processing applications.

Unfortunately, DASD is much more expensive than magnetic tape storage systems.

The latter is sequential in nature (as opposed to random access) and has long access times that are detrimental to overall data processing efficiency.

Additionally, the data capacity of DASDs is often not as large as desired in data processing applications.

The IBM 3850MSS combines the advantages of DASD and tape storage.

That is, lower level storage uses magnetic tape in the form of data cartridges, which automatically
data recording device DR
D, and signals are exchanged between the data cartridge and DASD under fully automatic control.

The user of the data processing system is then only exposed to a disk storage device with the capacity of a tape storage device.

When such an MSS is operating fully automatically, signals shuttle between two levels at a relatively high data rate.

Storage of signals on lower (or destaged) level magnetic tape uses the same information-bearing characters as used in DASD.

Magnetic tape storage is allocated on a so-called cylinder basis for recording.

A DASD cylinder consists of tracks on multiple recording surfaces.

For example, if a DASD has nine rigid disks and a "comb head," and the head holds 18 transducers to exchange signals with the 18 surfaces of the nine disks, then the cylinder It consists of a total of 17 tracks on 17 surfaces.

The 188th surface has a servo for controlling the positioning of the transducer of the comb head with respect to the recording surfaces of the nine disks.
It's a truck.

It will therefore be appreciated that data formats are unified throughout the various levels of data storage to increase efficiency.

The transfer of signals from a lower level (destaging level) to an upper level (staging level) is called staging signal conversion.

Staging operations move data to DASD and make it immediately available to users of the data processing system.

The transfer of signals from a higher level to a lower level is called destaging signal exchange.

In any signal exchange, it is important that not only the transferred data be detected and corrected by the error detection and correction system, but also that the integrity of the data be maintained.

That is, the staging and destaging operations are interrupted and only a portion of the data set is transferred from one level to another so that some of the cylinders have the desired data and the remaining portions have the undesired data. It shouldn't be something you should have.

When this situation occurs, it is called a loss of data integrity.

Computer programs working with such data may produce errors if a loss of integrity of such data occurs.

Although loss of data integrity is extremely rare, it can occur undetected.

This fact presents a significant challenge to all data processing systems with respect to ensuring the integrity of the computer calculations and the data on which they are based, on which they are so heavily relied upon to be satisfactorily accurate in a wide range of applications. .

In the rare case that the destaging operation is interrupted and data integrity is lost, the loss of data set integrity occurs even though powerful error detection and correction systems correct the resulting error system. is not necessarily displayed.

An object of the present invention is to provide a method for ensuring data integrity in magnetic recording and reproduction.

The method of the invention is characterized by identical first and second data integrity signal patterns characteristic of the data signal block to be recorded, interleaving the data signal book;
Data integrity is ensured by recording a third identical data integrity signal pattern a predetermined length behind the data signal block, and checking the identity of at least two of these data integrity signal patterns when data is reproduced. The purpose is to test gender.

In other signal transfer operations that may include a recording step, the area on the recording medium may be of fixed length, for example when storing signals in so-called cylinders of data.

In such a situation, before recording of data signals begins, a -set of data integrity signals is recorded first, followed by recording of data signals, and then a second recording of data integrity signals.

The remainder of the cylinder portion of the recording medium is erased (all zeros are recorded) and a third recording of the data integrity signal is made in the so-called RO area of the assigned cylinder portion of the recording medium.

In a preferred form of the invention, the computer has a program that allows it to perform the desired functions indicated above.

Additionally, hard-wired sequential circuits may be used to implement the method of the present invention.

Referring to the drawings, like numbers indicate like parts and structural features in each figure.

The present invention ensures data integrity during fully automated operation in signal transfer using magnetic recording media such as (but not limited to) magnetic tape, particularly in mass storage systems with multiple levels of storage. It is most beneficial when used for

First, the technology behind the present invention will be explained with reference to FIGS. 1, 2, and 3.

As best shown in Figures 1, 2 and 3,
The magnetic tape 1° sends the data signal to the data integrity signal Kl, 2. 3 and 21.

A 1 interposes the first recorded data set DATAI in the first recorded data integrity signal.

When the recording is successful, the 1 in position 11 is the same as the 1 in position 12.

When reading signals from tape 1°, a 1 in location 11 is first read, then the data signal DATAI, and finally a 1 in location 12.

If the two are equal, then data set DATA1 has high integrity.

Of course, the data detection and correction system
This guarantees that data errors will not occur due to data gaps or recording or reading.

The recording start point BOR precedes the 1 at position 11, and the recording end point EOR follows the 1 at position 12.

Similarly, on tape 10 there are other data sets DATA2 and DATA3 sandwiched between data integrity signals 2 and 3.

The size of the data set is not important to the implementation of the invention.

Data detection and correction systems handle the much more frequent data errors caused by record/read operations.

During normal data processing operations, tape 1o updates its recorded data sets from time to time.

In some situations, the size of a data set may be expanded or actually decreased.

Assume that data DATAI is manipulated by a data processing system such as utilization device 13 of FIG.

As a result, a new data cell (DATA21) is created by the utilization device 13.

At that time, the utilization device 13 stores the new data set DATA.
21 on tape 1o in the same area where data set DATA1 was previously recorded.

Then, as shown in FIG.
The first data integrity signal is received at 21, followed by the data set DATA 21, and the second data integrity signal at location 15 is followed by 21.

The old data set OLD DATAI remains unless erased, followed by a 1 in position 12.

Such an update would result in data set DATA1
There are two end-of-recording characters: EoRl, which represents the end of the original recording, and BOR2, which represents the end of recording the newly updated data.

All old data must be OLD DAT for security purposes.
Although it is desirable for AI to be deleted along with the 1 in position 12, this is not always done and may be omitted for efficiency in some systems.

Therefore, when the format depicted in FIG. 2 is read, position 14
and 21 of 15 is the newly recorded data set D
Represents data integrity of ATA21.

When the data cell DATA 21 is read by the computer or the utilization device 13, the utilization device 13 will know the range of the data cell DATA 21 and interrupt the reading at BOR2.

Alternatively, a gap or erased portion of tape 10 may be placed in BOR2 to indicate the end of recording.

Other codes may be used in addition to erasure.

However, if for some reason it changes from position 14 to position 21
When all records up to 1 in 2 are read, tape 1
The lack of data integrity of the signal transferred from o is indicated by the difference between the data integrity signal 1 and 21.

Appropriate error recovery procedures (which are outside the scope of this invention) are then taken to recover data set DATA from tape 10.
Read the record again to try to recover 21.

There is a possibility that the recording operation may be interrupted due to an accident.

This interruption may go undetected for several reasons.

If recording is interrupted at position 16, the BORl following 21 at position 14 follows new data NEW DAT
A2L Interruption point 16 and remaining old data OLD D
A data record having an ATAI occurs on tape 10.

The 1 at position 12 is still present on tape 10.

When the recorded signal of FIG. 3 is taken, the utilization device 13 expects 21 to be recorded at the second location 14.
The signal 21 does not match either the 1 at position 12 or the old data OLD DATAI at position 17.

Since the second 21 has not been recorded, a mismatch between the signal read from location 17 and the signal at location 14 with 21 indicates a lack of data integrity as well as an interruption in recording.

The representation of tape 10 in FIGS. 1, 2, and 3 is schematic and includes disk files, magnetic core memory, semiconductor memory, optical memory, and any other suitable device for receiving and receiving signals. It should be understood that this includes other recording media.

Returning to FIG. 1, the utilization device 13 connects a set of a recording circuit 20 and a reading circuit 21 to an actual tape recording device 22 (DRD
A recorder used with the tape 10 exchanges signals with the tape 10.

A data integrity signal of the first order is generated by the destage counter 23.

Destage counter 23 best performs its function with computer programming.

When the desired recording operation begins, utilization device 13 sends a first signal over line 25 to energize AND circuit 26 and pass the count contained in destage counter 23 to OR circuit 27.

From this point on, the recording circuit 20 is modulated to record on the tape 10.

Simultaneously with the signal on line 25, device 13 supplies a control signal via line 30.

This is for energizing the destage counter 23 and shifting the contents of the count through the AND circuit 26 and the OR circuit 27 and recording it at position 11 as 1.

Since the count field from counter 23 is of known size, the utilization device, once it has counted the number of bits supplied by counter 23, begins supplying the data signal of data DATAI via line 31 and OR circuit 27 to recording circuit 20. .

When the recording of data DATAI is finished, the device used is line 32.
and energizes AND circuit 33 to record the signal from destage counter 23 initiated by the signal on line 30 as a 1 in position 12. pass.

When the signal on line 30 is removed, the destage counter 23
is advanced to the next count.

In this regard, the destage counter 23 contains 3 bytes of 2
It may be a decimal counter, a linear feedback shift register counter, a decimal counter, or any other form of sequential count generator.

As mentioned above, the destage counter 23 is modified or incremented for each recording operation, thus providing a unique count for each recording operation.

The above mode of operation is the first best mode.

The second best mode is that the utilization device 13 supplies an increment signal via line 35, which may be periodic or aperiodic, but at least more frequently than recording operations, to the destage counter 23.
It is to change the count of .

This mode of operation is the second best mode in that the sequential data integrity signals recorded on tape 10, with or without encryption, are not sequential counts.

Further, the 1 in the signal at position 11 and the 1 in the signal at position 12 may differ by a predetermined count number or may differ depending on the encryption algorithm.

For simplicity purposes, the counts in positions 11 and 12 are preferably the same.

Verification of the data integrity of the data DATAI is performed in a read circuit check register 42.47 which receives and receives signals from the read circuit 21.

The read operation is carried out via line 40 to the read circuit 21 and the DRD.
commanded by the utilization device by a read signal provided to 22.

A 1 is read at the initial position 11 and supplied to the first register 42 via the AND circuit 41.

It is also supplied to the utilization device 13. The energizing signal applied via line 43 from read circuit 21 is applied to AND circuit 4.
1 and passes only the count portion corresponding to K1, the first three bytes read after BOR.

The read circuit 21, having counted three bytes, then removes the energizing signal from the line 43 and inhibits the AND circuit 41 so that the signal DATAI goes only to the utilization device 13.

When the reading of the data DATAI is completed, 1 is read in the signal at position 12 and is supplied from the AND circuit 46 to the second register 47.

The signal on line 48 is asserted to condition AND circuit 46 for three bytes in one period until EOR arrives.

At this time, registers 42 and 47 should both contain 1's.

These registers 42 and 47 are 1. In order to check the identity of 2, a count signal of 1 is output to the comparison circuit 50.

The comparator circuit 50 is activated by a signal provided on line 51 by the read circuit 21 which has detected the FOR.

If the comparison is successful, comparison circuit 50 sends a data integrity confirmation signal to utilization device 13 via line 52.

Also, when the comparison fails, the comparator circuit 50 sends a signal on line 53 to the error log register 54 to capture the contents of register 42.47.

Utility device 13 can then read the error log register using line 55 for data integrity evaluation and analysis.

A preferred form of the invention is shown in FIG.

The invention is now implemented in a mass storage system using an upper storage level 61 consisting of a plurality of DASDs and a lower storage level 61 consisting of tape library type storage devices.

The lower level 61 includes a mass storage device (hereinafter referred to as MSF) 58 consisting of a storage type of data cartridge.

Data cartridges can be automatically moved between storage locations in storage walls and between multiple DRDs 22.

It should be understood that the DRD 22 in FIG. 4 also includes a recording circuit 2o, a reading circuit 21, etc.

In place of the generation and detection circuits made of the hardware of FIG. 1, a computer 62 performs the functions described in FIG. 1 through a computer program.

Level 61 is a mass storage system controller (hereinafter referred to as M).
59 (referred to as SC).

It controls the operation of the MSF' and DRD 22 and the cooperative operation between the two levels 60 and 61.

The computer 62 has a data processing circuit and a memory 63 shown in FIG. 4A.

Memory 63 includes a register 23 containing a destage count, corresponding to destage counter 23 of FIG.
Contains A.

Additionally, it is desirable to identify the signal path through which signals are transferred from DASD 60 to lower level 61.

Therefore, the register 23A further includes a portion for recording on the magnetic tape and identifying the DRD 22 indicated in the memory by the unit number.

Similarly, when applied to a multi-path storage system such as the circuit-like capacitive storage system in FIG.
It has a register that is unalterable to contain the 22 addresses, ie, identifies the signal path on which the destage or write operation occurs.

Calculator 62 further includes a counter register 42A for containing the initial count read from tape 10 and a unit identification signal.

Additionally, a second register 47A contains a second count, corresponding to register 47 of FIG.

Additionally, the RO count of the third copy of the data integrity signal is stored in register 64.

Under ideal conditions registers 42A, 47A during read operation
and 64 are all equal.

Flag bit position 65 of memory 63 is lower level 6
1 to DASD level 60 to indicate to a connected higher-level computer 66 the results of a comparison of count fields 42A, 47A and 64.

Therefore, the host computers 66 including the main host computer 67 are DA
When requesting a data transfer from SD 60 to its own main memory (not shown), the integrity of the data signal is known.

Additionally, memory 63 of computer 62 includes a set of programs in a set of registers 68 for operating a portion of the mass storage system.

A good example of the tape format used when using the present invention in a mass storage system is shown at the bottom of FIG.
It is depicted as being written by one person.

DRD 22 is preferably a rotating head recorder in which storage tracks (or stripes) are present in diagonal bands on tape 10.

As mentioned above, the recording tracks are divided into cylinders according to the format of the DASD 60.

Since such cylinders of data recorded on tape 10 are not real cylinders, they are called virtual cylinders 70.

Each virtual cylinder is separated by a gap 71 to facilitate updating and identification.

Thus, the first virtual cylinder 72 is separated from the virtual cylinder 70 by a gap 71, and similarly a gap 73 separates the virtual cylinder 70 from the next virtual cylinder 74.

Generally, the recording operation of tape 10 proceeds from left to right as seen in FIG.

That is, the first recording track 75 of the virtual cylinder 7o is recorded first, and the DRD 22 that executes the recording operation is recorded there.
A data integrity signal is included along with the address of.

A second track 76 then contains the data signal DATAI.
is recorded.

The last track 77 containing the data signal to be recorded also contains ten copies of the data integrity signal.

However, it is very rare that the entire virtual cylinder 70 is completely filled with data signals.

This is to allow expansion and contraction of the data set during normal data processing operations.

Therefore the last track 77 containing 10 in the data integrity signal
After recording, the DRD 22 performing the recording operation erases the remaining tracks of the virtual cylinder 70 up to the last track RO.

10 to data integrity signal in track RO, track 77
This data integrity signal is recorded as a backup data integrity signal for 10.

That is, if track 77 cannot be read and data integrity cannot be verified for the first 10 of the first track 75, 10 and RO can be used for backup.

Even if track 77 is not read in this example, it can be seen that the erased track in region 78 between track 77 and RO contains an erased signal pattern which may be a DC erase or all O modulation signal.

As shown in FIG. 4, virtual cylinder 72 has data integrity as indicated by 65 in the data integrity signal, and virtual cylinder 74 has data integrity as confirmed by the data integrity signal.

This means that virtual cylinder 70 was probably written first and the adjacent virtual cylinders 72, 74 were recorded later, as indicated by the higher number data integrity signal.

If an error occurs in the recording of any of the virtual cylinders 72.74, for example a gap 71.73 is violated and overrides part of the virtual cylinder 70, the data integrity signal 10 will detect such an error. .

Because the recorded tracks are recorded as entities by the DRD 22, the error detection and correction circuitry will not detect such accidental overrides and the resulting destruction of the desired recorded data.

Only by using the present invention in a particular mass storage system can such data integrity corruption be accurately detected.

The address of the recording DRD identifies such inadvertent errors, thereby assisting maintenance personnel in diagnosing faults in the automatic operation of such large data recording devices.

The computer 62 switches between the DASD 60 and the DRD 22 and transfers data via one of the multiple computers 62.
It is possible to stage to ASD60 and destage from ASD60.

Therefore, the address recorded on tape 10 not only includes the DRD actually performing the recording, but also indicates which computer 62 handled the destage operation.

The combination of count and address fields thus provides an indication for the diagnosis and assistance of errors resulting in loss of data integrity, as well as an indication of abnormally high data error rates, for example.

Both the MSC 59 and the computer 62 are microprogrammable processing devices, and the computer 62 is further connected to the higher-level computer 6.
Between 6.67 and DASD60 or DASD60 and D
It has a special circuit for exchanging data signals between RD22.

Since part of the invention begins with microprogram control, two microprocessors are shown diagrammatically.

FIG. 4A shows one computer 62.

The interconnection between the MSC 59 and the computer 62 is described in U.S. Pat.
According to No. 400372.

That is, the main host computer 67 and other host computers 66 are MSC
Communicate with 59.

Furthermore, the MSC works as a host computer for the computer 62.

For convenience, computer 62 has a four-channel interface.

That is, the computer 62 can be connected to up to four higher-level computers.

Although the MSC 59 appears as one of the host computers, it is always on the same interface connection.

If the four connections are named A, B, C and D, the host computer MSC is connected to interface A, and the main host computer 67 and some other host computers 66 are connected to the other three interfaces. Connected.

Although the main host computer 67 does not need to be connected to all computers 62, the MSC must be connected to all computers 62.

The calculator portions of calculator 62 and MSC are the same.

The calculator problem and its relationship to calculator 62 are shown in sufficient detail in the flow chart for a better understanding of the microprogramming involved in the present invention.

In the computer 62, the program storage device 81 (4th A
) sends the instruction word to the instruction holding register 85.

The output of register 85 drives a decoding circuit 86 to provide a set of micro subcommands to all units.

Such decoding circuitry is constructed as is well known to those skilled in the art;
Useful for sequence operation of all units.

A portion of the instruction word is used for program branching and accessing the next instruction word from program storage 81.
It is fed back to an instruction address register 110 (hereinafter referred to as IAR) consisting of a W register 111 and an X register 112.

All operations of the computer circuit 80 are centered around the ALU 82.

ALU 82 has two inputs, A register 113 and B register 114.

These two registers receive and receive signals from multi-car output circuits 115 and 116, respectively.

The multiple input-output circuit simply receives signals from multiple signal buses and gates them into the A and B registers under control of decoder circuit 86.

Two of the input buses to the multi-input-output circuit transmit signals from the set of microprogram registers 87 to the A register 11.
3 to bus A1 and one selected microprogram register 87 and instruction word holding register 8
5 to the B register 114.

As previously shown, microprogram register 8
7 supplies the signal to the ALU 82 and receives the signal from the ALU 82 via the bus line.

The register 87 also sends signals to the host computers 66, 67 and M
In order to replace the SC59, a signal is supplied to a parallel/serial conversion circuit 90 and a channel circuit 91.

Therefore, the data loop of computer circuit 80 is ALU8
0, bus D1 microprogram register 87, bus A and B1 and A register 113 and B register 11
Contains 4.

Input from the program storage device 81 to the ALU 82 is via bus B.

All communications in the computer circuits flow through ALU 82.

For example, the bus signal also goes to the IG register 93, and the IG register 93 supplies a signal to the channel circuit 91.

Furthermore, the channel circuit 91 is connected to one of the host computers.

Channel circuit 91 is a channel circuit defined as a control unit in US Pat. No. 3,400,372.

Further examination of FIG. 4A clearly shows the data flow of computer circuit 80.

Each computer 62 has what is called a staging adapter.

This connects the DRD22 to the DASD control device 9 of the DASD60.
This is a data buffer system that connects to 5.

Because the tape device operates at a different speed than the disk storage spindle 96 of the DASD 60, the count up/count down buffer memory 92 (D
(connected to the ASD 60) parallel/serial conversion circuit 90.

Buffer memory 92 has independent control circuitry for automatically transferring signals to DRD 22 and receiving and receiving signals from DASD 60 via parallel to serial conversion circuit 90.

All these operations are independent of the computer circuit 80.

The computer circuit 80 connects the DASD 60 to the host computer 66.
67 or to the MSC 59 via the parallel/serial conversion circuit 90.

Buffer memory 92 has two parts that are used alternately.

The first part receives and takes signals from the DRD 22, and the second part simultaneously supplies signals to the parallel-to-serial conversion circuit 90 (staging).

When the transfer is finished, the operation is switched such that the first part supplies the signal to the parallel-to-serial converter circuit 90 and receives the signal from the second part DRD 22 in order to convert the data signal without interruption. .

When moving data from DASD60 to DRD22 (
(Destage) The same operation is performed.

Such buffer memory operation is well known and will not be discussed further.

The operation of calculation tank 62 for recording data signals on tape 10 in accordance with the present invention is shown in abbreviated form in FIG.

What has been omitted is the normal operation of the computer 62, which is an operation for recording signals, but is not relevant to the understanding of the present invention.

Such omitted subroutines are indicated by the ellipsis 100 in FIG.

Before starting the recording operation, the computer 62 clears a part of the memory 63 in response to subroutine QT235 in FIG. 7, and clears a portion of the register 42A.

Reserve count storage areas such as 47A, 64 and 65.

The destage count in register 23A is then incremented by QB 455 according to the first best mode.

In a second best mode structure of the present invention, described below in connection with FIG. 9, the destage count is stepped non-cooperatively with respect to the recording operation.

In any case, the first recording track is subroutine QT
150 is set up by the computer.

Next, the first recording track is written through subroutine QT401.

Intermediate tracks are recorded as shown in FIG. 4, but such operation is well known and will not be described.

The last track like track 77 is subroutine Q
Written in T360.

Intermediate track 78 is then erased to all zeros and subroutine QT writes track RO containing the data integrity signal.
The last track of the virtual cylinder 70 is written via 401.

The above steps describe recording one virtual cylinder on tape 1o.

It should be understood that addressing of the tape is completed prior to the operation shown in FIG. 5, i.e., the first track 75 is placed in a relationship in which the DRD 22 can perform the conversion operation.

In one embodiment of the invention, virtual cylinders, such as virtual cylinder 70, are written such that each cylinder is recorded independently.

However, in some systems it may be desirable to record such virtual cylinders continuously.

In that case, branch instruction 101 senses whether the appropriate number of cylinders have been recorded on tape 1o.

If so, the recording operation moves on to other operations of the computer 62.

On the other hand, if further cylinders are to be recorded in this sequence, steps QT235 to QT401 are performed again for each cylinder.

The data integrity signal is recorded three times for each virtual cylinder, while the address of the signal transfer path is recorded in the first track 75.
It is recorded only once.

Track R instead marks the end of the virtual cylinder 70.
0 and the last track 77 can record addresses.

Each subroutine is shown in abbreviated form, ie, only those instructions relevant to the implementation of the invention are shown.

Subroutine QT235, shown in FIG. 7, consists of a single instruction that zeroes and records a zero in a count storage area such as register 42A.

Register 42A contains a byte indicating whether the count value is valid.

Therefore, instruction 8E00 also resets the counter valid flag indicating that no examples were read from or recorded on tape 1o.

Subroutine QB455 performs the destage count (MV
(also called D count).

The three instructions shown in FIG. 8 are instruction 7A5C where the previous count value is
3A and placed in the computer circuit 80 of FIG. 4A.

The next retrieved count is AL in instruction 7A68.
It is stepped at U82.

The incremented count is then returned to register 23A and stored by instruction 7D2C.

As previously mentioned, the destage count increment described in FIG. 5 is only one of the two best modes.

FIG. 9 shows that the computer 62 is a DASD 60 or a lower level 6
The idle scan routine (idle 5oanrout-ine) that is repeatedly entered when waiting for an action request from computer 6
2 shows the second best mode that 2 has.

Such an idle scan routine consists of a plurality of branch instructions that are responsive to attention conditions or interrupts for branching to the appropriate program contained in register 68.

As shown in FIG. 9, the destage count is incremented once for each execution of idle scan routine QB 455.

Since idle scan routines are always used more often than record operations occur, the number of times the destage count is incremented is independent of the number of record operations, but is always greater than the number of record operations.

The reason for incrementing the destage count during the idle scan routine is to facilitate programming considerations.

Returning to FIG. 5, subroutine QT150 is shown in detail in FIG.

A portion consistent with the present invention includes an instruction to retrieve the DRD address located at 8770 in register 68.

That is, this is the address to be recorded on track 75.

Instruction 8BD8 is stored in data buffer storage (hereinafter referred to as DR8) 92 of FIG. 4A to record the address.

The address is automatically set to DRD for recording from DR892.
Go to 22.

Instruction 86DC then retrieves the destage count from destage register 23A.

Instruction 86BO then stores the count in DBS 92 and records it on tape.

As shown in FIG. 4, the KIO is recorded before the address.

The other situation is also appropriate. The advantage of recording the address second is that it is checked for data integrity along with the data signal.

Next, the first track is written by subroutine QT401 shown in FIG.

In fact, Figures 11 and 12 are almost the same except for the position of the instructions.
It is.

Therefore, I will explain both at the same time. First, a count is retrieved by instruction 9C54.

The count is then stored in a buffer by instruction 915C.

The remainder of the track is then retrieved and stored in DR892.

Then, of course, the intervening tracks are written before the last track is written.

Then, as shown in the instruction level flowchart of FIG. 5, the count of the data integrity signal is written by subroutine QTa60.

Next, a track RO defining the boundaries of the virtual cylinder 70 is written by subroutine QT401 shown in FIG.

Verification and reading of the data integrity signal is illustrated in FIG.

Computer 62 receives read instructions from one of the host computers and is set up for a read operation.

Parts relevant to the implementation of the invention are shown in block form in FIG. 6 and will be described in detail later.

The aforementioned count storage area is stored in the aforementioned subroutine QT235.
Cleared by

Subroutine QT165 then reads the first track containing the first copy of the recorded data integrity signal.

The next track is read when the last track 77 is read.
be read.

Branch instruction 102 then determines whether an error condition existed on the last track 77 read.

If the read is successful, that is, if the error detection and correction circuit (not shown) of the read circuit (not shown) is provided with error-free data from the last track 77, the computer responds to subroutine QT380. Read the last count from DBS 92 and compare it with the first read count read in subroutine QT165.

The result of the comparison is set in a flag and the read routine exits via branch instruction 103.

Branch instruction 103 operates similarly to branch instruction 101 previously described.

If the last track 77 contains an error condition, for example if the validity of 10 is questionable in the data integrity signal read, then in response to subroutine QT434 the computer overrides the last count read. In other words, it sets them all to zero and resets the count valid flag (not shown).

The next track is then read, including track RO, which defines the limits of the cylinder.

In response to subroutine QT421, the computer then compares track RO, which is a copy of 10, to the original count read in subroutine QT165 to make a data integrity comparison.

The comparison results are made available to the higher-level computers 66,67 in the MSC.

In one embodiment, the RO count is simply a batter-up count for the last track 77's data integrity signal.

In another example, the three data integrity signals of tracks 75, 77 and RO would be compared.

Instructions of subroutine QT165 that are relevant to the implementation of the present invention are shown in FIG. 1'3.

The first count is retrieved by instruction A230.

Next, at instruction A2E4, computer 62 determines whether the count is zero.

If it is not zero, the count valid flag is set in instruction A2E8.

This means that a count of all zeros indicates an invalid flag.

The count just read is then stored in register 42A.

Subroutine QT380 is shown in FIG. 14, where it reads 10 from the last track 77 and 1
0'.

Instruction D478 sends the count to three registers GA, GB, GC of microprogram register 87.

The count is 3 bytes long, each register GA.

GB and GC each contain 1 byte.

Instruction D484 retrieves the stored destage count from register 42A.

The two counts are then compared for equality in ALU 82.

If not, a device check or error signal is sent by the computer to MSC 59 in instruction D40C.

Next, in order to take appropriate error recovery procedures to ensure that errors caused by loss of data integrity do not propagate through the data processing system, other host computers receive error indications regarding the data signals just read. The MSC notifies the main host computer so that it can take the action.

If the comparison is successful, computer 62 simply continues with another job.

If track 77 is not properly read, then subroutine QT434, shown in detail in FIG.
is executed.

Instruction B75C prepares a zero, and instruction B724 stores that zero in register 47A for the same invalidation, i.e. all zeros.
transfer to the destage count.

The other track 78 is then read (all zeros) and track RO is read.

Finally, in response to subroutine QT421, the calculator returns the R of the count register 64 of the first count register 42A.
Compare with O count.

Subroutine QT421 of FIG. 16 shows instruction B7C8 which obtains the destage count from registers 42A and 64.

If the count is valid in instruction BOFC, calculator 62 determines whether the RO count (ROK) is equal to the first read count (BSK).

If not, a BOEC command is entered.

If they are equal, instruction BOE4 is executed.

Note that if the count is not favorable, no comparison is made and no loss of data integrity can be indicated.

Since one track is in error, such errors are communicated to the higher-level computer so that appropriate protective actions can be taken.

Although this flowchart illustrates instructions that may be particularly useful in the computer described in FIG. 4A, it is not intended to be limiting.

For example, 'Microprogra-mmin Pr
1nciples and Practices”Pr.
int ice Hal 1, published in 1970, S
Any programmable processor can be used, such as that taught by AmirS, Hassen.

The sub-coding of the flowcharts described is within the skill of the average programmer.

[Brief explanation of the drawing]

Figure 1 is a block diagram illustrating the relationship between the recorded data signal and the data integrity signal and the data integrity confirmation operation;
3 shows a recording member, in which valid data and invalid data lacking data integrity are displayed by data integrity signals; FIG. 3 shows a recording member having an area lacking data integrity; Figure 4 is a block diagram of a preferred embodiment of the present invention and a diagram showing a preferred form of data recording on magnetic tape, and Figure 4A is a block diagram of a programmable computer that can be used in the preferred embodiment of Figure 4. 5 is a process diagram of a computer program explaining the recording operation controlled by the computer of FIG. 4 to implement the present invention, FIG. 6 is a process diagram of a computer program explaining the reading operation, and FIG. 16 through 16 are process diagrams illustrating each subroutine. Kl, 2. 3. 21...Data integrity signal, DATAI, DATA21, etc....Data, 10...Recording member such as tape, 13...
...Using device, 2゜...Recording circuit, 21...
...reading circuit, 22 magnetic tape recording device, 23...
...Destage counter, 26.33, 41.4
6...AND circuit, 27...OR circuit, 42, 47...Register, 50...
Comparison circuit, 54...Error log register.

Claims (1)

[Claims] 1. A method for confirming the integrity of data signals when recording and reproducing data signals on a magnetic recording medium block by block, comprising: First and second predetermined marker signals that are the same are recorded, and a third marker signal that is the same as the first and second marker signals is further recorded a predetermined length backward from the end of the data signal block, and each marker signal is the same as the first and second marker signals. A method for verifying the integrity of a data signal block by checking the identity of at least two of the first, second and third marker signals for the data signal block during reproduction of the data signal block.