JPS583236A - Manufacture of gallium arsenide element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device using gallium arsenide (GaAmlTh), and specifically relates to a method for manufacturing a semiconductor device using gallium arsenide (GaAmlTh).
The present invention relates to a method of doping Kn or p-type impurities in an ion implantation KL-vτGmA-crystal using an aluminum nitride (-AtN) film as S.

When doping a GaAs crystal using a method such as Kn or p-type impurity tube ion implantation, lattice defects are introduced into the GaAs crystal. Heat treatment is performed to remove these crystal defects and electrically activate the implanted impurity tube, but when a GaA-crystal is heated above 630°C, arsenic (A-) scales from the crystal surface. Promotes the generation of crystal defects,
To solve this problem, conventionally, τ5ins and Sin N4 are used as surface protection SS to prevent the dissociation of A- during heat treatment. Since AjNIl has a coefficient of thermal expansion closest to that of GaAs, it is used as a stable retaining film with fewer problems such as peeling. However, even with very high temperature heat treatment, for example, 950°C or higher, AtNjI and G
Since the expansion rate of the aAs crystal is slightly different, the AtN film,
Stress occurs in both G a A and the crystal, resulting in crystal defects that directly affect the crystal, peeling of the AtN film, bits on the crystal surface caused by pinholes, or thematic pits (th@rmal pits). There is a problem.

The purpose of the present invention is to use an AtN film and a GaA film as surface retaining sg.
In order to alleviate the stress on the s crystal, G a A
Before or after implanting impurity ions into the s-crystal,
We decided to add one culm to implant boron (B) ions! v
The present invention aims to provide a method for manufacturing high-quality GaAm elements by reducing the occurrence of defects in GaAs I crystals that are susceptible to high temperatures.

The present invention uses B with a small atomic radius? KL is implanted into the impurity region in the GaAs crystal, and the thermal expansion of QaAs and At
The method is designed to match that of N, and is intended to relieve stress on the AtN film and GaAs crystal. However, the reason why the expansion coefficients match has not yet been clearly elucidated.

However, the thermal expansion coefficient of QaAs (7X10-・dog-1
) Thermal expansion coefficient of AtN barrier film compared to K (6XIO-”d
eg-1) is slightly small, it is inferred that the principle of preventing compressive strain from occurring in the Btff heat-treated product and suppressing lattice defects introduced into the crystal as much as possible is at work. Furthermore, Be! B because it belongs to Ga and cognate element 11
There is no direct effect on the electrical characteristics K [also, B
Since the implantation amount of is extremely small and does not substantially change the GaAs crystal composition and does not affect K, the band structure is not affected and therefore the device properties are not changed.

As an example of the present invention, a manufacturing method in which a GaA crystal is doped by n-shaped selenium (f3ts) f ion implantation will be explained in comparison with a conventional method. FIG. 1 shows a schematic cross-sectional view of a GaAs device at various stages of conventional manufacturing, and FIG. 2 shows a schematic cross-sectional view of GaAs at various stages of manufacturing according to an embodiment of the present invention.

In the conventional method, a GaAs wafer 1 held at 300°C is first injected with 2 ions of Se ions at 125 KsV.
4 cm −', ion implantation (first IQ(a)
).

Next, on the Se injection layer 3, KAtNIII4tP1000A
.

The first layer is formed by a reactive sputtering method at a substrate temperature of 300° C., and then heat treated at 950° C.

In this case, the activation rate of the injection layer is about 20-, and an n+ layer with a carrier concentration of 2.times.IQ"cm-" is formed.

(6) There was a large variation in these values within the wafer surface. This was due to the local occurrence of pinholes in the AtN film 4, which is a protective material. ') The density of the thermal pit formed in the evaporator was about 10'em-''.

In the manufacturing one culm of the embodiment of the present invention, prior to Se ion implantation, Ga
As wafer 6KIX10"eIR-" ions are implanted (Fig. 28!11(c) 1) S ions are implanted from above the KB implantation layer 7 (Fig. 2(d), then , a second AAN film 10′ having a thickness of 1000 is formed on the Se+B injection layer 9 by a reactive sputtering method.
Figure (e)), heat treatment is performed at 950°C, the activation rate of the injection layer is about 50cm, and the n of carrier concentration is 5X10"cm-".
Ten layers are formed and the incidence of thermal bits is 10”cm
− It became smaller. In addition, heat treatment KJC5 is formed
PL of tn-type layer (photo luminesc@n
ce) Measuring tube It was found that the strong luminescence of 1,27 V, which had been observed with only S injection, was significantly reduced by 19 when double injection of B was added. 1.27
Conventionally, it has been interpreted that eV emission is related to a complex defect between Ga vacancies and donors, which is one of the crystal defects. This is considered to be effective in preventing the formation of complex defects.

The activation rate of the implanted layer largely depends on the amount of defects in the crystal, and when the amount of defects is large, the activation rate decreases because the amount of injected impurities that act as carriers decreases. Therefore, when comparing the activation rates of the embodiments of the present invention and the conventional method, the activation rates are larger than those of the conventional method.
Mr. PJ's trial tube for n ions was tried, but it did not make a big improvement, and in particular the I n + A ■ implantation had the opposite effect. If the present invention is applied, the stress applied to the AtN film and crystal during heat treatment can be reduced. It is possible to relax and prevent the occurrence of crystal defects.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a conventional embodiment, and FIG. 2 is a diagram for explaining an embodiment of the present invention. 1.6 GaA Hatake wafer 2.8 Se ion 5 B ion 3 8s injection layer 4.1 OAtN film 7 B injection layer 9 B+S・Injection layer Fig. 1 Ratio Fig. 2 (α) (C) < b) (
tl) (e)

Claims (1)

[Claims] In a device manufacturing method including ion-implanting a gallium arsenide semiconductor Kn or P sculpture, forming an aluminum nitride film on the semiconductor, and heat-treating the semiconductor, boron ions are added to the semiconductor before or after impurity implantation. A method for producing a gallium arsenide stamp comprising the step of implanting ions into an impurity implantation region.