JPS5829897B2 - automatic frequency control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to automatic frequency control circuits (AFC), and more particularly to clock frequency control circuits for time division multiple access (TDMA) equipment for satellite communications.

For the TDMA system, the burst signal of the reference earth station is used as the timing reference.

Therefore, each of the other earth stations detects the burst signal of the reference station from the received wave, and uses this as a reference for the frame pulse (1
The frequency of the local station's Kerok was synchronized with that of the reference station.

Conventional automatic frequency control circuit (rPHASE LOCKED LOOPJDA) in such TDMA system
TA BOOKJ, 1973. s month, MOTOR-O
Published by LA, or “PLL Basics and Practice”, 197
3 November issue "Electronic Science" (see pages 13 to 40)) generally describes an oscillator (VCO) whose output clock frequency changes according to a control signal, and a frequency divider that divides the output frequency of this oscillator by N. a phase comparator that compares the phase of the input signal (the above-mentioned frame pulse) with the output pulse of this frequency divider, and the output of this phase comparator is amplified and processed to generate the above-mentioned control signal. It consists of a means to

This circuit includes a phase-locked loop (CPLL) which varies the output frequency of the oscillator so that the frequency of the output Hals of the frequency divider matches that of the input frame pulse.

However, in this conventional circuit, the frequency is divided by N using a frequency divider, so the DC loop gain of the PLL is 1/NK.

Therefore, especially in the TDMA system, it is necessary to set N very large.

(approximately 20,000), the DC loop gain is too small, making it difficult to perform synchronized bow pull-in, and even if pull-in is possible, N is large, resulting in poor frequency synchronization accuracy.

Furthermore, the phase comparator, DC amplifier, and ρ waveformer are originally analog circuits, and if they are mixed with the digital circuit of the N divider, the circuit configuration becomes complicated.

An object of the present invention is to provide an automatic frequency control circuit that eliminates the above-mentioned defects.

According to the present invention, a voltage controlled oscillator (VCO), a frequency divider that divides the oscillation frequency, a memory that stores the contents of the frequency divider according to an input signal to an automatic frequency control circuit, and the storage contents thereof. There is a detector that detects each of - Means for converting the contents of a down counter into an analog voltage to generate a control signal for an oscillator (VCO) is obtained.

The invention will be explained in more detail below with reference to the drawings.

FIG. 1 is a block diagram of a conventional automatic frequency control circuit, in which reference numeral 1 is an input terminal for inputting a signal having a frequency f8 (for example, a frame synchronization pulse), and 2 is a frequency f.

11 is a voltage controlled oscillator (VCO), 12 is a phase comparator, 13 is a DC amplifier, and 14 is a low frequency filter (LPF).
, and 15 are N frequency dividers that convert the output frequency of the VCOII to 1/NVC.

This circuit constitutes a phase-locked loop, and frequency synchronization is achieved by the synchronization pull-in, and a clock having a frequency N times the input frequency f8 is obtained at the output terminal 2.

For a detailed explanation of the operation of this circuit, please refer to the above-mentioned literature.

This conventional circuit suffers from the drawbacks mentioned above.

FIG. 2 is a block diagram of an automatic frequency control circuit according to the present invention, in which reference numeral 21 denotes Q
.

, Ql, · m frequency divider with two outputs of the song "Ql-t" (where m and t are positive integers 21, <m<2'), 2
2 is a storage circuit consisting of two D-flip-flops that records each output of the m frequency divider 21 at the appearance timing of input 1, and 23 is a storage circuit that records the output 101 of the storage circuit 22 as a threshold
+K (K=Ko+2 to 1+22 to 2+-...+2t-I
A binary comparator that performs direct detection with Kl), 24
A binary comparator with a threshold of -K (but the actual threshold gives +m for -), 25 is a binary comparator with either binary comparator 23 or 24 [when point detection is performed]. , a feedback path for resetting the m frequency divider 21 and setting an initial value, 26 is an up/down counter, and 27 is a D/A converter for converting the contents of the amplifier/down counter 26 into an analog voltage.

Now m is one of the divisors of N, m=8 (t=3).

The operation of the AFC circuit of the present invention when K=2 will be explained.

The third freeze and Figure 4 are the times at this time.

However, f>Nf8. ■Output frequency f of C011 in FIG.

The CO output clocks shown in FIG. 3a are counted by the m frequency divider 21 as shown in FIG. 3, c and d.

The output IQo of this m frequency divider 21, Q1 . Q2. The contents of (
Fig. 3e) is input 1 timing (Fig. 3f frequency f8
) to the D-flip-flop in Figure 3 gp by l'
t respectively.

The contents of the stored output 101 (FIG. 3 i is a binary comparator (
Manufactured by TEXAS INSTRUMENTS 5N548
5,5N7485) is compared with =2 at 23.

4>Q'> At 20:00, a pulse is generated at the output 103 as shown in FIG. 3, and the m frequency divider 21 is reset.

At the same time, this pulse causes the amplifier down counter 26 to count up.

The up-counted output is converted to v by the D/A converter 27.
Generates a CO control voltage 102 and outputs the vCO output frequency f.

in the direction of lowering the frequency by the frequency control unit δf (that is, the frequency error Δf=f).

-Direction to reduce Nf8) VC control.

This completes one cycle of control operation.

This cycle is repeated until the content of 101 reaches the threshold (as shown in Figure 4a).
Due to the integral action of
02 is integrated in units of voltage, and the frequency error Δf is decreased in units of frequency control unit δf as shown in FIG. 4C.

When the frequency error finally becomes smaller than δf, the sign of the frequency error is reversed every time the input/output phase difference exceeds threshold K, and a steady state is reached.

In steady state, the average frequency error is 0 and the instantaneous frequency error is less than or equal to δf.

Next, in the case of Nf8, the binary comparator 24 compares the output 101 with -Km=6.

When 4<Q<6, the m frequency divider 21 is reset and a pulse is generated to count down the up/down counter 26.

Down power! 7/The operation after the counted up/down counter 26 is to set the control voltage opposite to that at the time of amplifier counting to V.
Give COK.

The above description has been made regarding the case where m is a divisor of N and m=80, but in general mtN may be a natural number.

Now, suppose that the content of the m frequency divider 21 is O at the initial time (t = 0) K$-, then after a second time the content of the m frequency divider 21 is changed to the memory 22 by a pulse to the input 10. Therefore, the memory 22 stores foj t (MODm) = △f-t+ -N (MO
Dm) (where Δf=fo−Nf8; frequency error) is described.

Here, fo-t (MODm) is f after t seconds.

This is the content of the m frequency divider that counted . When N is a composite number, if one of the divisors of N is chosen as m, we always get K k N (MO
Din ) = O, and the contents of the memory 22 directly represent Δf - t (MODm), that is, only the frequency error after t seconds.

This is the circuit shown in FIG. 2 mentioned above.

By the way, when N is a prime number, kN (MODm) is 0
Not.

Therefore, kN(MODm)=k(MODm)XN(M
In this way, the embodiment shown in FIG. 5 adds a correction circuit when N is a prime number.

In FIG. 5, 29 is a correction circuit, and 28 is a memory circuit 22.
30 is an m frequency divider for counting the input pulse signal 1, 31 is N(MO
32 is a multiplication circuit that multiplies the output of the circuit 31 and the output of the m frequency divider 30.

Correction output kN (MODm) output from correction circuit 29 = k
(MODm )
That is, only the frequency error after t seconds is output.

Other operations are the same as in FIG. 2.

In addition, in the operations shown in Figs. 2 and 5, △f-t (MO
D, m) = △f-t, l△ft-t<m
I have to run it.

As explained above, according to the present invention, since the in-loop KN frequency divider is not included, the PLL D
C loop gain does not become small.

Therefore, synchronization is ensured even for a large N, and an AFC circuit with high frequency synchronization accuracy can be obtained.

If the minimum frequency control unit δf is selected to be small, the frequency synchronization accuracy can be increased as much as possible within the range allowed by the stability of ■CO.

Furthermore, since the operation is digitalized, an AFC circuit with a simple circuit configuration can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional N-divided automatic frequency control circuit, FIG. 2 is an embodiment of the automatic frequency control circuit of the present invention, and FIG. The chart, FIG. 5, is another embodiment of the invention. In the transposition, 11... voltage ff111m oscillator, 15...N frequency divider, 16......O
R gate, 21゜30...m frequency divider, 22...
...Memory circuit, 23゜24...Shishai detector, 25...Return path, 26...Amplifier Dow 7 counter, 27. River -D /Ai converter, 28・
... Adder, 29 ... Correction circuit, 31.
... Constant generator, 32 ... Multiplier circuit.

Claims (1)

[Claims] 1 Press the button on the automatic frequency control circuit that adjusts the output signal frequency to a frequency that is N (N is a positive integer) times the human input signal frequency.
an oscillator that generates the output signal by changing its frequency according to a control signal; a frequency divider that divides the output signal frequency m (m is a positive integer equal to or less than N); means for sampling and storing an input signal; a detector for generating a frequency deviation signal in response to a comparison output between the output of the storage means and a predetermined threshold of m or less; and a detector for generating a frequency deviation signal in response to the frequency deviation signal; a feedback path for resetting the frequency divider to a predetermined reference state; an amplifier/down counter for integrating the output of the detector so that the automatic frequency control circuit forms a negative feedback loop; An automatic frequency control circuit comprising means for converting into an analog voltage and supplying the analog voltage to the oscillator as the control signal.