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JPS5828365Y2 - integrated circuit device - Google Patents

integrated circuit device

Info

Publication number
JPS5828365Y2
JPS5828365Y2 JP1977043287U JP4328777U JPS5828365Y2 JP S5828365 Y2 JPS5828365 Y2 JP S5828365Y2 JP 1977043287 U JP1977043287 U JP 1977043287U JP 4328777 U JP4328777 U JP 4328777U JP S5828365 Y2 JPS5828365 Y2 JP S5828365Y2
Authority
JP
Japan
Prior art keywords
wiring
functional circuit
area
substrate
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977043287U
Other languages
Japanese (ja)
Other versions
JPS53139284U (en
Inventor
征行 角田
亨 細水
健一 大野
宏史 武田
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1977043287U priority Critical patent/JPS5828365Y2/en
Publication of JPS53139284U publication Critical patent/JPS53139284U/ja
Application granted granted Critical
Publication of JPS5828365Y2 publication Critical patent/JPS5828365Y2/en
Expired legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【考案の詳細な説明】 本考案は半導体基板に複数形成される半導体素子を配線
する集積回路装置に関し、特に配線密度の基板内分布を
均一かつ高密度にして基板サイズを小さくすることがで
きる集積回路装置に係る。
[Detailed description of the invention] The present invention relates to an integrated circuit device that wires a plurality of semiconductor elements formed on a semiconductor substrate, and in particular, an integrated circuit device that can reduce the substrate size by making the distribution of wiring density uniform and high within the substrate. Related to circuit devices.

従来、チップに論理ゲート、フリップフロップ回路等よ
りなる機能ブロックを複数形成した基板所謂、マスクス
ライス基板が知られている。
2. Description of the Related Art Conventionally, a so-called mask sliced substrate is known, which is a substrate in which a plurality of functional blocks including logic gates, flip-flop circuits, etc. are formed on a chip.

第1図は従来提案のマスクスライス基板の正面図である
FIG. 1 is a front view of a conventionally proposed mask sliced substrate.

図中1はSi基板、2は人、出力パッド、3は機能回路
ブロック、4は内部配線領域、5は外部配線領域である
In the figure, 1 is a Si substrate, 2 is a person, an output pad, 3 is a functional circuit block, 4 is an internal wiring area, and 5 is an external wiring area.

このマスクスライス基板はシリコン基板1上に外部端子
に接続するための接続パッド2とトランジスタ、ダイオ
ード等により所定の機能となるよう配線された機能回路
ブロック3とが設けられて構成される。
This mask sliced substrate is constructed by providing on a silicon substrate 1 connection pads 2 for connecting to external terminals and a functional circuit block 3 wired with transistors, diodes, etc. to perform predetermined functions.

こうしたマスタースライス基板を用いて所定の機能を有
する装置、例えば計算装置の計算処理ユニットと同等の
機能を作成する場合、まず種々の機能をもつ機能回路ブ
ロック3を配置し、それら機能回路ブロック間の配線を
内部配線領域4に形成し、外部接続するための接続パッ
ド2には外部接続領域5を使用して接続するようにして
いる。
When using such a master slice board to create a device with a predetermined function, for example, a function equivalent to a calculation processing unit of a calculation device, first arrange functional circuit blocks 3 having various functions, and then Wiring is formed in the internal wiring area 4, and the external connection area 5 is used to connect to the connection pad 2 for external connection.

また、こうした従来のマスクスライス基板では種々の配
線パターンを形成するための機能回路ブロックを基板内
で均一に分布させて形成すると、配線される導体のパタ
ーンが基板の中央付近に集中し、基板中央、イ寸埋での
配線密度が高く、基板周辺部では配線□密度が低くなり
□、配線密度が基板内不均一になっていた。
In addition, in such conventional mask sliced boards, if the functional circuit blocks for forming various wiring patterns are uniformly distributed within the board, the conductor patterns to be wired will be concentrated near the center of the board, , the wiring density was high in the area where the board was buried, and the wiring density was low at the periphery of the board, making the wiring density non-uniform within the board.

そのため各機能回路ブロックあたりの配線領域を基板中
央での配線の導体パターンが占める大きさと同じにして
配線可能にしていたため、全体の基板サイズが大きくな
る欠点を有していた。
Therefore, the wiring area for each functional circuit block was made equal to the size occupied by the conductor pattern of the wiring at the center of the board to enable wiring, which had the disadvantage of increasing the overall board size.

本考案の目的は、上述の如き欠点を取除き、基板中央に
配線が集中するのを防止すると共に、配線密度をチップ
内で均一、かつ高密度にして、基板サイズを小さくし得
る集積回路装置を提供することにある。
The purpose of the present invention is to eliminate the above-mentioned drawbacks, prevent wiring from concentrating in the center of the board, make the wiring density uniform and high within the chip, and reduce the board size in an integrated circuit device. Our goal is to provide the following.

上記目的を遠戚するために本考案では四角形の半導体基
板上に所定の機能を有する素子により構成される複数の
機能回路ブロックを略マトリクス状に配置してなる集積
回路装置において、該基板周囲に設けられた複数の接続
パッドと、該接続パッドの内側に設けられた外部配線領
域と、該外部配線領域の内側で前記機能回路ブロックを
略マトリクス状に配置した機能回路ブロック領域と、該
機能回路ブロック領域の中央部に形成され各機能回路ブ
ロック間に配線を施すための配線専用領域とを具備して
なることを特徴とし、中央部分に機能回路ブロックを形
成せずに配線の分布を分散し得るようにしたものであり
、以下第2図の本考案の実施例正面図を基に詳述する。
In order to achieve the above object, the present invention provides an integrated circuit device in which a plurality of functional circuit blocks constituted by elements having a predetermined function are arranged in a substantially matrix shape on a rectangular semiconductor substrate. a plurality of connection pads provided, an external wiring area provided inside the connection pads, a functional circuit block area in which the functional circuit blocks are arranged in a substantially matrix shape inside the external wiring area, and the functional circuit. It is characterized by having a dedicated wiring area formed in the center of the block area for wiring between each functional circuit block, and dispersing the distribution of wiring without forming functional circuit blocks in the central part. This will be described in detail below based on the front view of the embodiment of the present invention shown in FIG.

なお、図中第1図に用いたものと同じものは同一番号で
示してあり、6は配線専用領域である。
In the figure, the same parts as those used in FIG. 1 are indicated by the same numbers, and 6 is an area dedicated to wiring.

即ち、同図において基板1上に形成された機能回路ブロ
ック3は配線領域6には設けられず、全て配線領域6の
周囲に設けるようにしである。
That is, in the figure, the functional circuit blocks 3 formed on the substrate 1 are not provided in the wiring area 6, but are all provided around the wiring area 6.

つまり、通常配線領域6の配置に設けられる機能回路ブ
ロックによる配線は全て配線領域の周囲で行なわれるか
ら中央部分の配線の密度が低くなるばかりか機能回路ブ
ロックは配線専用領域6以外の個所に均一に高密度に分
布できるから、多種の配線の各々が複雑になる事もない
In other words, all the wiring by the functional circuit blocks provided in the layout of the normal wiring area 6 is done around the wiring area, so not only is the density of wiring in the central part low, but the functional circuit blocks are evenly distributed in areas other than the wiring area 6. Since the wires can be distributed at high density, each of the various types of wiring does not become complicated.

以上、説明した様に本考案によれば、配線密度が基板周
辺部で低くならずチップ内で均一、しかも高密度になる
から基板サイズを小さくすることができる。
As described above, according to the present invention, the wiring density does not decrease at the periphery of the substrate, but is uniform within the chip, and is high in density, so that the substrate size can be reduced.

さらに配線パターンも複雑にならず、しかも基板の中央
部分に配線が集中することもなくなるから、短絡、断線
を防止することもできる。
Further, since the wiring pattern is not complicated and the wiring is not concentrated in the center of the board, short circuits and disconnections can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来提案のマスクスライス基板正面図、第2図
は本考案の実施例を適用したマスクスライス基板正面図
である。 図中、1は基板、2は接続パッド、3は機能回路ブロッ
ク、4,5は配線領域である。
FIG. 1 is a front view of a conventionally proposed mask sliced substrate, and FIG. 2 is a front view of a mask sliced substrate to which an embodiment of the present invention is applied. In the figure, 1 is a substrate, 2 is a connection pad, 3 is a functional circuit block, and 4 and 5 are wiring areas.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 四角形の半導体基板上に所定の機能を有する素子により
構成される複数の機能回路ブロックを略マトリクス状に
配置してなる集積回路装置において、該基板周囲に設け
られた複数の接続パッドと、該接続パッドの内側に設け
られた外部配線領域と、該外部配線領域の内側で前記機
能回路ブロックを略マトリクス状に配置した機能回路ブ
ロック領域と、該機能回路ブロック領域の中央部に形成
され各機能回路ブロック間に配線を施すための配線専用
領域とを具備してなることを特徴とする集積回路装置。
In an integrated circuit device in which a plurality of functional circuit blocks constituted by elements having a predetermined function are arranged approximately in a matrix on a rectangular semiconductor substrate, a plurality of connection pads provided around the substrate and the connection an external wiring area provided inside the pad; a functional circuit block area in which the functional circuit blocks are arranged in a substantially matrix shape inside the external wiring area; and each functional circuit formed in the center of the functional circuit block area. 1. An integrated circuit device comprising a dedicated wiring area for wiring between blocks.
JP1977043287U 1977-04-07 1977-04-07 integrated circuit device Expired JPS5828365Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977043287U JPS5828365Y2 (en) 1977-04-07 1977-04-07 integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977043287U JPS5828365Y2 (en) 1977-04-07 1977-04-07 integrated circuit device

Publications (2)

Publication Number Publication Date
JPS53139284U JPS53139284U (en) 1978-11-04
JPS5828365Y2 true JPS5828365Y2 (en) 1983-06-21

Family

ID=28917424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977043287U Expired JPS5828365Y2 (en) 1977-04-07 1977-04-07 integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5828365Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5578561A (en) * 1978-12-08 1980-06-13 Fujitsu Ltd Master-slice lsi circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4870489A (en) * 1971-12-20 1973-09-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4870489A (en) * 1971-12-20 1973-09-25

Also Published As

Publication number Publication date
JPS53139284U (en) 1978-11-04

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