JPS5827916B2 - Bit line level control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to (1) an unselected bit line control circuit 1 that prevents sink current of unselected cells from flowing through half-selected cells in a 2L memory;

A typical static memory cell occupies a large area because it uses a resistor as a flip-flop load and requires an isolation region between transistors due to its element structure.

Furthermore, in order to achieve a low power consumption ratio, if one high resistance is applied to one load, the area occupied by one cell will further increase.

Therefore, if semiconductor memories are made to have lower power consumption and larger capacity by using ordinary memory cells, the chip yield will decrease and the cost will increase.

This point l2L (Integrated Injecti
The use of memory cells (1) is advantageous in reducing the power consumption and increasing the capacity of semiconductor memories.

(2) Various types of 2L memory cells have been proposed, but basically this is a flip-flop based on a reverse-operating NPN transistor I with a PNP transistor as a load.

An example of this is shown in FIG. FIG. 5A is an equivalent circuit when the device is selected, FIG. 2A is an equivalent circuit when it is not selected, and FIG.

In FIG. 1, Qt and Q2 are PNP type load transistors (injectors), P3+Q4 are reverse operation transistors, and these constitute a flip-flop.

Q5 and Qa are detection transistors for reading and writing, and transistors Q1 to Q6 constitute a memory cell MC.

w+ and w- are word line pair B. , B1 are bit line pairs.

Reading and writing to memory cell MC+ are performed by transistor Q5. This is performed by operating Q6 in the forward direction, but here, the focus will be focused on writing.

Now, assuming that the transistor Q3bs is in the ON memory state in FIG.
There it is.

Therefore, the collector level (2) is lowered (transistor Q4 is off).

In this state, one transistor Q is used to write the opposite information.
A current is drawn from the emitter of 5, and its base current absorbs the collector current of 1 to Randisk Q2, and therefore the base current of transistor Q3, causing transistor Q3 to shift 1 in the non-saturating direction.

As a result, ■2 increases, transistor Q4 turns on, and its collector current ■1 decreases, causing transistor Q4 to turn on.
3 is off 1 (the flip-flop is reversed).

During this write, bit line B is connected through transistor Q5.
.

The write current Iw drawn to the side is a predetermined write threshold current Iw
It must exceed th.

Iwth depends on the current of the transistor Q2, in other words, the injector current l1njl flowing through the common emitter of the transistor Qt and Q2.

In other words, the smaller l1njQK is, the smaller Iwth is required, and high-speed writing is possible with a small Iw.

Figure 2 shows the memory cells MC,..., MCI□...
MC212MC22... is a 2L memory device arranged in a matrix of nXn bits, and each cell receives row selection signals VXI to Xn and column selection signal V.
Selected by combining YI to ■Yn.

TXl-TXn are word drivers, TYI (TY1'
) TYn”, (TYn') is the bit driver, W
1+(W, .=)~Wr1+(Wn is word line pair, B
1 to Bn are bit line pairs, S and -Sn are column sense circuits, and IBO:IBl are bit line currents.

Now, if VXl and vYl are crossed by Hl, cell MC11
i (selected)

At this time, the cells in other rows and columns are in the non-selected state, but the cells MC□2 to MC1n share the selected cell MC1 and the word lines W1+, W, -. There is 1 selection state, and one of the half-selected cells MC11(i
-=2 to n) and the non-selected cell MCji (j=2 to n), which rubs the bit line (unselected) by one, as shown in FIG.

The figure assumes that the transistor Q3 of each cell MC2MCji is on, but in this case, the selected word line W1+.

Since the potentials of W and - are higher than the potentials of unselected word lines Wj+ and Wj-, the detection transistor of semiconductor cell MC11 operates in the forward direction, and one reverse operation transistor of unselected cell MCji operates as shown by the solid arrow in the figure. A sink current begins to flow toward Q51ζ.

Since this current 1 is supplied from the selected word line, it increases the injector current of the selected cell MC1t (FIG. 2) and increases the load current of the word driver TX1.

Particularly, an increase in the injector current in the selected cell MC□11 deteriorates the write characteristics.

On the other hand, in the non-selected cell MC..., the transistor Q4
When b'S is on, the current ■5. flows through the bit clamp transistor Tci side, so the injector current of the selected cell MC11 does not increase.

The transistor Tc1 (Te1-Tcn in FIG. 2) is originally connected to the selected column (bit line pair B1 in FIG. 2) (here, the sink current flowing into the non-selected cells MC21 to MC,1 flows out from the selected cell MC11). This one is provided to avoid changing the write characteristics.

The clamp level Vc will be explained with reference to FIG.

This figure corresponds to Figure 1 a1 and vl. (2) are the base potential and collector potential of the on-side transistor Q3, respectively.

■1 is the value that the collector-emitter voltage VOE (Q2) of transistor Q2 has decreased from W+, and ■2 is W
− to collector-emitter voltage V of transistor Q3
OE (Q3) is the increased potential.

Bit line potential B on the side through which write current Iw flows.

is the word line potential W+ VOE (Q3) VBE (Q5
) or less, and the bit line potential B□ on the side where the write current Iw does not flow is W-+VOE (Q3)
-VBE (Q5) or higher, and based on these relationships, bit line B.

, B1 potential is B in FIG. and B1, for example, B1/ shown by a chain line.

In other words, in order to supply sink current to unselected cells, it is sufficient to clamp the bit line to a sufficiently high level, but on the other hand, in order to sufficiently drain the write current from the selected cell, the bit clamp level must be lowered. It is necessary to set the settings, and for this reason B in Figure 4.

is the upper limit and B1 is the lower limit.

These upper and lower limits B. To clamp the bit line potential to B, / between , B1, the voltage ■c applied to the base of the clamp transistor Tci is set to B1' +V BB (T
c i ).

In principle, by rubbing the bit line once, it is possible to prevent the contents of unselected cells that rub the bit line in common from changing the write characteristics of the selected cell. There is a problem in that the sink current of the selected cell affects the write characteristics of the selected cell.

The sink current flowing through each unselected cell is weak, but in an nXn bit memory array, the sink current as a whole (n-1
) Since there are two non-selected cells, the sum is a dog, and it changes greatly depending on the storage state of the non-selected cells.

This point will be explained with reference to FIG. 5. Figures a and b show typical examples of non-selected columns (bit lines).
1 is a half-selected cell, MC2 to MCn are unselected cells, and TC is a bit clamp circuit.

a is a case where the contents held in the half-selected cell MC1 and the non-selected cells MC2 to MCn are the same; in this case, the sink current is
, 2~' sn flows from the half-selected cell MC0.

b shows a case where the contents held in the half-selected cell MC1 and the non-selected cells MC2 to MCn are different; in this case, the entire current ΣIs flows through the clamp circuit TC.

Such a difference is the potential B shown in FIG. , B1.

Therefore, in the ramp method as shown in Figure 2, the current flowing through the selected word line changes greatly depending on the content held in the unselected cell in one unselected column, and when the word line current is at its maximum (in the unselected column (when the contents held within match)
This increases the injector current of the selected cell by up to 1, which degrades the write characteristics (the write pulse width increases without increasing the write threshold current), and also increases the load current of the word driver. Since the selected word line level is varied in this way, there is a drawback that the bit clamp level margin (BO-Bl') shown in FIG. 4 is reduced.

In order to solve the above-mentioned drawbacks, the present invention provides (1) a bit line level control circuit for a semiconductor memory using 2L memory cells; It is characterized by comprising a clamp level switching circuit that sets the clamp level of the unselected bit line to be higher than the clamp level of the non-selected bit line.
This will be explained in detail below with reference to the illustrated embodiment.

FIG. 6 shows an outline of the present invention, in which B1 is a selected column and Bi (i=2 to n) is a non-selected column (corresponding to FIG. 2).

Bit clamp transistor Tc1. Different clamp levels VO+VOH are supplied to Tc1l.

The voltage Vo determines the clamp level of the selected column, and follows the principle 1 in Figure 4, and vcH (>vO) is set to 1 higher than the base potential v of the transistor Q3 shown in Figure 4 ('=W+). do.

FIG. 7 shows an embodiment of the present invention embodying this, and only one column is shown.

In FIG. 1, MC is a memory cell, Tci is a bit clamp transistor, TYi, TYi/hat driver, and the drivers TYi, TYil are selected by a column selection signal -Y.

To is a transistor constituting the clamp level switching circuit EX, and is similarly controlled by Y.

■Yb'SH becomes B.

, B, 6 (transistors TYi, TYil when selected
and T.

turns on. As a result, a current l06 flows through the resistor R1, lowering the base potential of the transistor Tc1, and is clamped at this level ((c) satisfying the condition in FIG. 4) in the selected column -b≦.

On the other hand, in the case of non-selection, the transistors TYit TYi' and T□ are off at VYbsL, so ■cl is applied to the base of the transistor Tci, and at this level (VOH in Fig. 6). The bit line is clamped.

This VOH can be made to an arbitrarily high level by selecting V c t.

As described above, according to the present invention, a sink current is prevented from flowing from a half-selected cell to an unselected cell, and as a result, the write characteristics of the selected cell are stabilized. This has advantages such as not reducing the margin for bit clamp level setting.

[Brief explanation of drawings]

Figure 1 a, b, and c are an equivalent circuit diagram when 2L memory is selected, an equivalent circuit diagram and a cross-sectional diagram when it is not selected, and Figure 2 is an I2
FIG. 3 is a schematic configuration diagram showing the entire L memory device, FIG. 3 is a circuit diagram of half-selected cells and non-selected cells, FIG. 4 is an explanatory diagram of bit clamp levels, and FIG. 5a. b is an explanatory diagram showing a typical example of a sink current flowing through a non-selected column, FIG. 6 is an explanatory diagram showing an outline of the present invention, and FIG. 7 is a circuit diagram showing an embodiment of the present invention. In the figure, MC, MC1..., MC1,...
・■2L memory cell, B1 is selected bit line, Bi is unselected bit line, TOi is bit clamp transistor,
EX is a clamp level switching circuit.

Claims (1)

[Claims] In the bit line level control circuit 1 of a semiconductor memory using II"L memory cells, when selected, the level of the selected bit line is set to 6 (lower and the clamp level of unselected bit lines is higher than that). An unselected bit line control circuit comprising a clamp level switching circuit that sets the clamp level to 1.