JPS58225672A - Floating gate non-volatile memory - Google Patents
Floating gate non-volatile memoryInfo
- Publication number
- JPS58225672A JPS58225672A JP57108930A JP10893082A JPS58225672A JP S58225672 A JPS58225672 A JP S58225672A JP 57108930 A JP57108930 A JP 57108930A JP 10893082 A JP10893082 A JP 10893082A JP S58225672 A JPS58225672 A JP S58225672A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- floating gate
- volatile memory
- memory
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、半導体基板−第１の絶縁膜−７０−ティング
ゲート−第２の絶＃、膜−制御電極、の構成を有するフ
ローティングゲート型不揮発性メモリに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate nonvolatile memory having a structure of semiconductor substrate-first insulating film-70-ring gate-second insulation film-control electrode.
フローティングゲート型不揮発性メモリの構造上第１図
に示す。同図に於て、（１１は一導電型半導体基板、例
えば４〜８ｒｌ 、 ｔ７ｊＬの比抵抗を有するＮ型の
シリコン基板、 １２Ｈ３１はこの基板（１１にＰ型の
不純物を選択拡散する事に依って形成したソース。The structure of a floating gate type nonvolatile memory is shown in FIG. In the figure, (11 is a semiconductor substrate of one conductivity type, for example, an N-type silicon substrate having a resistivity of 4 to 8 rl, t7jL, and 12H31 is a semiconductor substrate of one conductivity type, for example, an N-type silicon substrate having a specific resistance of t7jL, and 12H31 is a semiconductor substrate of one conductivity type. sauce formed.
トレイン領域、 ＋４１はこのソース、ドレイン領域〕
外周に設けらｔた膜厚大なるフィールド酸化膜、１５１
ハ：／−ス、ドレイン各領域１２１１３１間のチャンネ
ル領域（６）ヲ覆う如く設けら几た第１の絶縁膜で、膜
厚約２０ＯＡの酸化膜にて構成さ扛ている。（７）はこ
のＭｌのＰＪＲ膜１５）上に設けらｎたモリブデン等の
金属材料から成るフローティングゲート、（８）ハ該フ
ローテインググー）ｉ７１ｉ覆って設けらｎた第２の絶
縁膜で、膜厚が８５０Ａ程度の窒化膜にて構成さｎてい
る。＋９１はこの第２の絶縁膜（８）上に被着さ才ｔた
制御ＩＩ］を極、叫１ｕはソース、ドレイン各領域ｉ２
１＋３１ Ｋ逐ったソース、ドレイン各電極である。Train region, +41 is this source and drain region]
Field oxide film with large thickness provided on the outer periphery, 151
A first insulating film is provided to cover the channel region (6) between the base and drain regions 121131, and is made of an oxide film with a film thickness of about 20 OA. (7) is a floating gate made of a metal material such as molybdenum provided on this Ml PJR film 15), and (8) is a second insulating film provided covering the floating gate. It is made of a nitride film with a film thickness of about 850 Å. +91 is the control II layer deposited on this second insulating film (8), and 1u is the source and drain region i2.
The source and drain electrodes are separated by 1+31K.
斯る構造の不揮発性メモリはフローテインダゲ−） １
７１に電荷を注入する事に依って情報を書き込んで記憶
せしめている。ところで断るメモリへのｉｉｉ：ｉ込み
電圧（ＶＶ）及びその書き込んだ内容ケ消去する消去゛
電圧い］）は２０Ｖ前後で１通常の半導体回路で用いる
電圧に比して相当高い。A non-volatile memory with such a structure is a floating memory) 1
By injecting charge into 71, information is written and stored. By the way, the writing voltage (VV) to the memory and the erasing voltage (voltage for erasing the written contents) are around 20V, which is considerably higher than the voltage used in normal semiconductor circuits.
−万、斯る不揮発性メモリに対する情報の瞥き込み方法
としては。- How can I view information on such non-volatile memory?
１）基板（１）と制卸電極（９）との間に高電界を印加
して電子ｔトンネリングに依り強制的にフローティング
ゲート（７）に注入する方法。1) A method of applying a high electric field between the substrate (1) and the control electrode (9) to forcibly inject electrons into the floating gate (7) through electron tunneling.
２）基板（１）とソース、ドレイン各領域１２１ｆ３１
との間のＰＮ接合でアバランシェ破壊奮起し、その時発
生するホントエレクトロン會フローティンクケ−Ｈ７１
に注入する方法。がある。2) Substrate (1) and source and drain regions 121f31
The avalanche breakdown occurs at the PN junction between the
How to inject into. There is.
また消去方法としても、トンネリングに依って強制的に
注入電子？放出せしめるものと、紫外線管照射して注入
電子全活性化して消去する方法がある。Also, as an erasing method, is it possible to forcibly inject electrons through tunneling? There is a method in which the electrons are emitted, and a method in which all the injected electrons are activated and erased by irradiation with an ultraviolet tube.
一般に不揮発性メモリは種々の用途に用いらｎているが
、例えば書き込みのみが行わｔ′Ｌ、１殆ど消去は行わ
れない場合には消去電圧は多少高くても問題はなく、頻
度の高い書き込み電圧が低いものが好ましい。また逆に
消去のみ全目的としての用途に対しては消去電圧の低減
のみｔ考え牡ば艮い０勿論、蕾き込み電圧も消去電圧も
共に低いものが得らｆ’ＬｆＬは良いのであるが、実際
には両者の要望を満す事は出来ない。In general, non-volatile memory is used for a variety of purposes.For example, if only writing is performed, t'L, or 1, there is no problem even if the erase voltage is a little high if there is little erasing; One with a low voltage is preferable. On the other hand, for applications where erasing is the only purpose, it is not acceptable to consider only reducing the erasing voltage.Of course, f'LfL is good since it is possible to obtain low write-in voltage and low erase voltage. In reality, it is not possible to satisfy both demands.
本発明はこのような不揮発性メモリの用途に応じた特性
會得る半合目的としている。The present invention is aimed at achieving a combination of characteristics suitable for the use of such nonvolatile memory.
第２図は第１図に示さ几たような構成の不揮発性メモリ
の製造直後の閾値電圧（Ｖｔｏ）と書き込み及び消去の
為の臨界電圧（Ｖφ）との関係線図であり、実線（〜は
書き込み臨界電圧（ＶＶφ）ｔ、また破線（Ｂ）は消去
臨界′電圧（ｖ［φ）を示している。この第２図は第１
図に示したＰチャンネル型のメモリの特性図であるので
、縦軸も横軸も負の値を示している。尚、＊き込み臨界
電圧（ＶＷφ）とは、メモリの閾値電圧（Ｖｔ）が負に
あるものを書き込み処理する事に依ジ正に移行するが、
閾値電圧（Ｖｔ）￥ｉ−零にする為に必要な電圧の半合
云い、また消去臨界電圧（ｖｉφ）とは。FIG. 2 is a diagram showing the relationship between the threshold voltage (Vto) immediately after manufacturing the nonvolatile memory having the structure shown in FIG. 1 and the critical voltage (Vφ) for writing and erasing, and the solid line (~ indicates the write critical voltage (VVφ) t, and the broken line (B) indicates the erase critical voltage (v[φ).
Since this is a characteristic diagram of the P-channel type memory shown in the figure, both the vertical and horizontal axes indicate negative values. Note that *Writing critical voltage (VWφ) means that the threshold voltage (Vt) of the memory becomes positive depending on the writing process when the threshold voltage (Vt) is negative.
What is the threshold voltage (Vt) ¥i - half of the voltage required to make it zero, and what is the erase critical voltage (viφ)?
消去に依って閑値゛電圧（Ｖｔ）’を負方向に移行ぜｔ
、わ、ヵ１、ヤ□ヶ零。ｆ４Ｋｉ’ｆ４１１ｔ工。事ヶ
ヨ １う。この関係線図が示している事は、
閾値電圧が高く（工９負側に）なルば書き込み電圧（Ｖ
′ｖＩ）は高く（エリ負側に）なり、逆に消去電圧（Ｖ
ＪＩ＋）は低くなる半合示している。従って消去は考え
る必要はなく、書き込みのみに着目丁ｎば良い用途のメ
モリの場合は書き込み電圧（ｖｖ ）ｖｒ低（設定すｎ
は艮い事とな９、その為にはメモリの製造直後の閾値電
圧（ＶｔＯ）？ｒ低くす扛は艮い。By erasing, the idle value 'voltage (Vt)' moves in the negative direction.
, Wow, ka1, ya□karei. f4Ki'f411t engineering. Kotogayo 1. What this relationship diagram shows is that
If the threshold voltage is high (on the negative side), the write voltage (V
'vI) becomes high (toward the negative side), and conversely, the erase voltage (V
JI+) shows a half chance of becoming lower. Therefore, there is no need to think about erasing, and in the case of a memory whose purpose is to focus only on writing, write voltage (vv) vr low (setting n
9.For that reason, what is the threshold voltage (VtO) immediately after the memory is manufactured? r.
また逆に消去のみ？問題にする用途のメモリの場合は製
造直後の閾値電圧（ＶｔＯ）ｉ高く設定イルば艮い事に
なる。Or on the other hand, only deletion? In the case of a memory for the purpose in question, if the threshold voltage (VtO) i is set high immediately after manufacture, it will cause problems.
斯る目的全果すべく本発明に於てはメモリのチャンネル
領域（６）にＰ型、或いはＮ型の不純物全注入して製造
直後の閾値電圧（ｖｔｏ）２任意に設定している。In order to achieve this purpose, in the present invention, all P-type or N-type impurities are implanted into the channel region (6) of the memory, and the threshold voltage (vto) 2 is arbitrarily set immediately after manufacture.
第１図に示した具体的なメモリの製造直後の閾値電圧（
ＶｔＯ）は約−１，８■であったが、チャンネル領域（
６）にＮ型の不純物、具体的には燐會加速電圧６０に６
Ｖ、注入ｔ １．８ Ｘ １０ ／ａｍ テロ５０に
の厚みの酸化膜を介して注入する事に依って（ｖｔｏ）
は約０．４ｖ増大し、−２，２Ｖとなった。更に注入荻
？増す事に依ってエリ負方向へ製造直後の閾値電圧（ｖ
ｔｏ）ｙ移行せしめる事が出来る。またチャンネル領域
（６）にｐｇの不純物であるボロンｆ ３５ Ｋ ｅ
Ｖの加速電圧で１．０ Ｘ １０１１ Ａｇ注入すると
、（Ｖｔｏ）は０゜３Ｖだけ低くｚｐ−−ｉ、ｓｖとな
った。当然ボロンの注入量を増加すると−（Ｖｔｏ）ｉ
ｊ史に低下してＯＶに近ずくであろう。The threshold voltage (
VtO) was about -1.8■, but the channel area (
6) N-type impurity, specifically phosphorus accelerating voltage 60
V, implantation t 1.8 x 10 /am by implanting through an oxide film with a thickness of 50 (vto)
increased by about 0.4V to -2.2V. More injections? By increasing the threshold voltage immediately after manufacturing (v
to)y transition. Also, in the channel region (6), boron f 35 K e which is a pg impurity
When 1.0 x 1011 Ag was implanted at an accelerating voltage of V, (Vto) was lowered by 0°3V to zp--i,sv. Naturally, when increasing the amount of boron implanted, -(Vto)i
It will probably drop to near OV.
従って書き込みが重視さｎる用途のメモリにはチャンネ
ル領域（６）にＰ型の不純物を注入して１Ｆき込み電圧
を下げ、また消去電圧が問題となる場合はチャンネル領
域（６）にＮ型の不純物全注入して消去電圧會下ける事
が好ましい。Therefore, for memory applications where writing is important, P-type impurities are implanted into the channel region (6) to lower the 1F write voltage, and when erasing voltage is a problem, N-type impurities are implanted into the channel region (6). It is preferable to lower the erase voltage by implanting all of the impurities.
本発明は以上の説明から明らかな如く、チャンネル領域
にＰ減成いはＮ型の不純物ケ注入する事に依って書き込
み電圧や消去電圧全変化せしめているので、用途に適し
たメモＩＪ （、得る事が出来ると共に、低い電圧で齋
き込み、或いは消去を行う事が可能となり、使い勝手の
良い不揮発性メモリが得られる。As is clear from the above description, the present invention completely changes the write voltage and erase voltage by implanting P-type impurities or N-type impurities into the channel region. It is possible to obtain a nonvolatile memory that is easy to use, and can be written or erased with a low voltage.
第１図はフローティングゲート型不揮発性メモリの断面
図、第２因は製造直後の閾値電圧と臨界電圧（Ｖφ）と
の関係線図上水しており、＋２１１３１はソース、ドレ
イン領域、ｉ５＋１８１は絶縁膜、（６）はチャンネル
領域、１７）はフローテインググー）、１９１は制ａｆ
ｉｌｆｌ、 （ωは書き込み臨界電圧、（Ｂ）は消去臨
界電圧、葡夫々示している。
出願人三洋電機株式会社
第２図
Ｌｐ
θ −ｚｓｒ −５ＶFigure 1 is a cross-sectional view of a floating gate non-volatile memory.The second factor is the relationship between the threshold voltage and critical voltage (Vφ) immediately after manufacture. membrane, (6) is the channel region, 17) is the floating goo), 191 is the control af
ilfl, (ω is the writing critical voltage, (B) is the erasing critical voltage, respectively. Applicant: Sanyo Electric Co., Ltd. Figure 2 Lp θ -zsr -5V
Claims (1)
基板−第１の絶縁膜＝７０−テイングゲートー第２の絶
縁膜−ｍｌ電極、の構成を有するフローティングゲート
型不揮発性メモリに於て、Ｐ型或いはＮ型の不純物音チ
ャンネル領域に注入して不揮発性メモリの書き込み電圧
、並びに消去電圧を変化ぜしめた半合特徴としたフロー
ティングゲート型不揮発性メモリ。1) In a floating gate nonvolatile memory having the structure of semiconductor substrate-first insulating film=70-tecking gate-second insulating film-ml electrode, the channel region between the source and drain is P-type. Alternatively, a floating gate type non-volatile memory has a half-domain feature in which the write voltage and erase voltage of the non-volatile memory are changed by injecting N-type impurities into the sound channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57108930A JPS58225672A (en) | 1982-06-23 | 1982-06-23 | Floating gate non-volatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57108930A JPS58225672A (en) | 1982-06-23 | 1982-06-23 | Floating gate non-volatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58225672A true JPS58225672A (en) | 1983-12-27 |
Family
ID=14497255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57108930A Pending JPS58225672A (en) | 1982-06-23 | 1982-06-23 | Floating gate non-volatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58225672A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60144976A (en) * | 1984-01-06 | 1985-07-31 | Seiko Instr & Electronics Ltd | Low-voltage programming method for nonvolatile semiconductor memory |
| US6327186B1 (en) | 1998-12-17 | 2001-12-04 | Fujitsu Limited | Non-volatile semiconductor memory including memory cells having different charge exchange capability |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS502873A (en) * | 1973-05-11 | 1975-01-13 |
-
1982
- 1982-06-23 JP JP57108930A patent/JPS58225672A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS502873A (en) * | 1973-05-11 | 1975-01-13 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60144976A (en) * | 1984-01-06 | 1985-07-31 | Seiko Instr & Electronics Ltd | Low-voltage programming method for nonvolatile semiconductor memory |
| US6327186B1 (en) | 1998-12-17 | 2001-12-04 | Fujitsu Limited | Non-volatile semiconductor memory including memory cells having different charge exchange capability |
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