JPS58225671A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION la) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a BP-RO.
This relates to a method for manufacturing M, etc.

(bl Technological background) In semiconductor memory devices such as EP-ILOM, MOS transistors for memory selection have a stacked polycrystalline silicon gate structure with a floating gate, and single-layer polycrystalline silicon gate structures.
Mo5L transistors for peripheral circuits with a gate structure, polycrystalline silicon wiring, etc., and polycrystalline silicon patterns with a laminated structure and a single layer structure are provided on a single conductive substrate.

lcl Prior Art and Problems Conventionally, the above-mentioned EP-ROM has been formed by the following method.

That is, as shown in Fig. 1 (@), a lower polycrystalline silicon layer is entirely formed on a semiconductor substrate l on which a field oxide film 2 and a gate oxide film 3 have been formed, and after complete patterning, a thermal oxidation tube is applied. , 7-transistor formation region 4-top? A first polycrystalline silicon medium pattern 6' having a first oxide film 5Vi on its covering surface, and a polycrystalline silicon single layer gate electrode having a first oxide film 5Vi on its surface, for example on a peripheral transistor formation region 7. Formed 8 meetings.

Next, as shown in Figure 1, an upper polycrystalline silicon layer 9' is formed on the substrate, and the upper polycrystalline silicon layer 9'
a first resist pattern l corresponding to the stacked gate on top;
Oa and, for example, a first resist pattern lOb? corresponding to the upper layer polycrystalline silicon wiring. Form.

Then, the upper polycrystalline silicon layer 9' is patterned by dry etching using the resist patterns 11Ja and 10b as masks to form the polycrystalline silicon contacts in the stacked gate as shown in Figure 1P]. ---
A gate electrode 9a and a polycrystalline silicon electrode 9b'e are formed. Furthermore, due to the dry etching, the upper layer of the registration patterns 10a and 10b has a number of 1.
A resist altered layer 11 having a thickness of about oo (JL) is formed.

Next, as shown in FIG. A second resist film 1 having 12 openings
3(j form.

The second resist film 13 and the first oxide film 5t on the first polycrystalline silicon medium pattern 6' exposed in the opening 12 as a mask are wetted and etched, After removal by the 1,000-inch process, the first polycrystalline silicon pattern 6 is selectively etched by the dry etching process to form a floating gate electrode 6 in a stacked gate as shown in FIG.

Then, the second resist film 13 and the first resist patterns 10a and 10b are removed, and then the /7'-t oxidized V
The first oxide film 5 on the light amount area A3 and the polycrystalline silicon single layer gate electrode 8 is removed by wet etching, and the second oxide film 5 is removed on the separate transistor formation area 4 as shown in FIG. 1(c). , gate oxide film (first gate oxide film)3. Polycrystalline silicon/floating gate electrode6. First oxide film (second gate oxide film) 4-5, and polycrystalline silicon control gate electrode 9
A laminated gate 't' is formed by sequentially laminating a polycrystalline silicon single layer gate electrode 8Yts formed under the gate oxide film 31 on the peripheral transistor formation region 7, and a polycrystalline silicon arrangement 19b is formed on the field oxide film 2. was.

However, in the above conventional method, when etching the upper polycrystalline silicon layer 9 by using the first resist and pattern 1 (1,10 kl'e mask),
As shown in Figure i/) 1, the resist pattern lOa,
A resist altered layer 11 is formed on the upper layer 10b. Since this deteriorated layer jl has the property of repelling resist liquid, it can be applied to areas where the first resist or pattern is disposed close to each other, for example, l! The resist solution is repelled in areas 14 in FIG. When etching the film 5 and the first polycrystalline silicon pattern 6"t, the lower polycrystalline silicon layer, such as the polycrystalline silicon single layer gate electrode 8 of the peripheral transistor exposed in the resist film missing portion of j12, is etched. There is a problem in that the formed electrodes and wiring are etched, causing noise such as disconnection, and resulting in a decrease in manufacturing yield.

The resist deteriorated layer 11 shown in FIG. 1 (-1 to FIG.
In the process, the first polycrystalline silicon medium putter 76'
When the upper first wiring film 5t is wet-etched and washed with water, it is peeled off from above the first resist bone pattern 10a, and is deposited on the first polycrystalline silicon pattern 6'.
The dry etching of the first polycrystalline silicon pattern 6' is inhibited and the polycrystalline silicon pattern 6' is deposited on the transistor formation region 4. Therefore, there is a problem in that the source/drain region is abnormally formed in a subsequent process, impairing the electrical characteristics of the transistor and lowering the manufacturing yield.

(dl) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned problems. 0 tel Structure of the Invention Namely, the present invention provides a method for manufacturing a semiconductor device in which a laminated polycrystalline silicon pattern and a single-layer polycrystalline silicon pattern are provided on a semiconductor substrate. A lower polycrystalline silicon pattern is formed on the semiconductor substrate formed with the polycrystalline silicon pattern, and a lower polycrystalline silicon pattern is formed to selectively cover the conductor region on which the laminated polycrystalline silicon pattern is disposed, and the surface VC of the lower polycrystalline silicon pattern is formed. After forming an oxide film layer 1, an upper polycrystalline silicon layer is formed on the semiconductor substrate, an oxide film @2 is formed on the upper polycrystalline silicon layer, and a lamination pattern is formed on the upper polycrystalline silicon layer. Form a resist medium pattern corresponding to the pattern and a resist layer 1-7Yr corresponding to the single layer pattern,
After selectively removing the second oxidation layer (by using a wet etching method using a full mask of these resist patterns), patterning the upper polycrystalline silicon layer (preferably by a dry etching method); 7- After removing the resist pattern, form a resist film on the substrate that completely covers the openings that fully expose the lower polycrystalline silicon pattern, and remove the resist film and the lower polycrystalline silicon pattern exposed in the openings. A step of selectively etching the lower polycrystalline silicon pattern using a dry etching method using the second oxide film on the upper polycrystalline silicon pattern formed on the crystalline silicon pattern as a tray mask. thing'! i'' is characterized.

g) Examples of the invention The following is an example of the present invention shown in Figures 1 (a) and 2.
The process cross-sectional diagrams shown in Figures (A) to (C)? This will be explained in detail using

When forming an EP-ROM'i using the method of the present invention, as shown in FIG. Then, a gate oxide film 3t is formed on the exposed cell transistor formation region 4 and peripheral transistor formation region 7 by thermal oxidation. Then, a lower polycrystalline silicon layer with a thickness of, for example, 14,000 to 5,000 Å is deposited on the substrate by chemical vapor deposition (CVI). A first polycrystalline silicon pattern 61'Ik1 is formed on the cell/transistor formation region 4 and covers the transistor formation region 4 or on the peripheral transistor formation region 7. A polycrystalline silicon single layer gate electrode 8 is formed on the polycrystalline silicon single layer gate electrode 8, and then thermal oxidation is performed to form a first polycrystalline silicon pattern 6'.
and a thickness 70 at the fitting opening of the polycrystalline silicon single layer gate electrode 8.
0 to 1ooo (Xll variation) First oxide film 5 is formed.

Next, as shown in FIG. 2(A), an upper polycrystalline silicon layer 9' is formed on the substrate using a KCVD method to a thickness of, for example, about 4000 to 5000 [λ], and then a thermal oxidation method is used to form an upper polycrystalline silicon layer 9'. On the upper polycrystalline silicon layer, a layer with a thickness of, for example, 70 mm is applied.
After forming the second oxide film 15 with a thickness of about 0 to 1000, a first resist pattern lOa corresponding to the laminated gate and, for example, corresponding to the upper polycrystalline silicon wiring is formed on the upper polycrystalline silicon layer. The lth resist pattern lO
bl (to form)

In the figure, a semiconductor substrate, a two-layer oxide film,
3 is a gate oxide film, 4 is a secondary transistor formation region, 5 is a first oxide film, 6' is a first polycrystalline silicon pattern, 7 is a peripheral transistor formation region, 8 is a single layer gate 1- Show the extreme.

Next, using the first resist pattern 10a and a job mask, the entire exposed area of the second oxide film 15 is selectively removed by wet etching using a hydrofluoric acid (HF) solution, and then the exposed area of the second oxide film 15 is removed using the same method. Resist pattern lOa
The T-layer polycrystalline silicon layer 9 is exposed by ordinary plasma etching using an etching gas such as carbon tetrabutyrate (OF) decaate (02) using a 10b2 mask.
' is selectively etched away, and then the exposed first oxide film 5 and gate oxide film 3 are completely etched away by wet etching using an HF-based solution. As shown in FIG. 2 (9), a second oxide film 15t'' is laminated on the first oxide film (second gate oxide film) 5 on the first polycrystalline silicon pattern 6'. Control I, gate electrode 9a, and yield oxide film 2
A polycrystalline silicon film b' having a second oxide film 15 thereon is formed thereon. Numbers 10a and 10b are patterns in the resist, and the above-mentioned resist altered layer 11 is formed in the upper layer of the cyst pattern 9 during the plasma treatment. A polycrystalline silicon single layer gate electrode 8 having a gate oxide film 3 underneath is formed on the peripheral transistor formation region 7 exposed by the father layer process.

Next, the first resist pattern loa and the first resist pattern are removed together with the 1ob deformed layer 11. This state is shown in Figure 2H, in which 6' is the first polycrystalline silicon pattern, 5 is the first oxide film (second gate oxide film), and 9a is the polycrystalline silicon pattern. 9b is a polycrystalline silicon layer, and 15 is a second oxide film.

(2) In the resist removal and water washing, the altered layer 11 is removed together with the resist pattern, so that it does not remain on the substrate. As shown in □ (then shown in FIG. 2), a resist film 13 of j1!2 is coated on the substrate, and a first multilayer MJ&11- silicon film is applied to the resist film 13 using a normal 7-way process. A polycrystalline silicon film is formed by forming 12t of openings exposing a pattern of 6"k, and then using a CF4+02k etching gas as an etching gas.
Control I/Second oxide film 15 on gate electrode 9a
The first polycrystalline silicon pattern 6' is selectively etched away using a T mask.

5 turns (of the stacked gate as shown in FIG. 2) are then completed. In the figure, 6 is a polycrystalline silicon floating gate electrode.

In addition, in applying the second resist film 13 during the etching, in the method of the present invention, the second resist film 13
is formed directly in contact with the second oxide y&15 on the polycrystalline silicon layer 9b. Therefore, the resist film 13 is not repelled.

Therefore, unlike in the conventional method, a cutout portion of the resist film 13 is not formed above the region where the lower polycrystalline silicon pattern such as the peripheral transistor formation region 7 is formed, and these lower polycrystalline silicon patterns are no longer formed. Missing,
Failures such as wire breakage may occur.Also, as mentioned above, during the etching, the IjK layer may
Since the first resist pattern 10a on the upper part of the resist pattern 10a does not exist, patterning defects of the first polycrystalline silicon Φ pad 6' due to peeling off and adhesion of the altered layer, which occur in the conventional method, are completely avoided. do.

Next, after removing the second resist film 13i, the entire surface was etched with an HF thread solution, and as shown in FIG.
A gate insulating film 3.
Polycrystalline silicon floating gate electrode 6゜first oxide film (second
(gate oxide film) a+polycrystalline silicon 9 controller I, stacked gate t1 consisting of middle gate electrode 9a, polycrystalline silicon single phase gate electrode 8 field insulation with gate oxide film 3 below on peripheral transistor formation region 7 Polycrystalline silicon layer consisting of upper polycrystalline silicon layer on film 2 @9b
Form a meeting.

Although not shown in the drawings, source/drain regions are formed in the star formation region using the usual method using the above-mentioned Goot electrode mask and ion implantation, formation of an insulating film, opening of electrode windows, and formation of aluminum wiring. etc. are done, F3P
- ROM is provided.

(gl) As described in detail, according to the method of the present invention, no polycrystalline silicon layer remains on the tooth 1 drain forming region of the memory cell transistor.
A drain region can be formed.

In addition, when forming a stacked gate, there is no need to damage the electrodes and interconnections made of lower polycrystalline silicon that are disposed outside the memory cell I9 transistor formation region, so there is no need to damage the missing wR lines of these electrodes, interconnections, etc. etc. are prevented.

Therefore, according to the present invention, the manufacturing yield of a semiconductor device having a structure in which an MO8) transistor with a stacked gate structure such as EP-4LOM and a MOS transistor with a single layer gate structure are arranged on one semiconductor substrate is improved.

[Brief explanation of the drawing]

1A to 1C are cross-sectional views of the process in the conventional method, and FIGS. 2A to 2C are cross-sectional views of the process in an embodiment of the present invention. In the figure, l is the semiconductor substrate, 2 is the field oxide film, and 3 is the semiconductor substrate.
4 is a gate oxide film, 4 is a transistor formation region,
5 is #! 1 oxide film (second gate oxide 1[), 6' is the first polycrystalline silicon threat pattern, 6 is the polycrystalline silicon floating gate electrode, 7 is the peripheral transistor formation region, 8 is the polycrystalline silicon single layer gate 9' is the upper polycrystalline silicon layer, 9m is the polycrystalline silicon control I/gate electrode, 9b is the polycrystalline silicon wiring, 1Oa+10b is the first resist Q pattern, 11 is the resist altered layer, 1
2 indicates an opening, 13 indicates a second resist film, and 15ij indicates a second oxide film.

Claims (1)

[Claims] +11 When sequentially patterning all of the upper and lower conductor layers laminated with the first insulating film on the substrate, the second insulating film is completely formed on the upper conductor layer, and then the second insulating film is patterned. A mask film pattern of Nl is entirely formed on the top, the second insulating film and the upper conductor layer in the portions not covered with the first mask film are all sequentially etched and patterned, and then at least a portion of the second insulating film is etched. A process of forming the entire exposed second mask film pattern and then etching and patterning the lower conductor layer in the portion not covered by either the second insulating film or the second mask film? A method of manufacturing a semiconductor device, comprising: (4) When a laminated polycrystalline silicon pattern and a single-layer polycrystalline silicon pattern are both provided on a semiconductor substrate, an element in which at least a laminated polycrystalline silicon pattern is disposed on a semiconductor substrate on which an insulating film is formed. After forming a lower polycrystalline silicon layer selectively covering the area and forming an oxide film of Nl on the surface of the lower polycrystalline silicon layer, an upper polycrystalline silicon layer is formed on the semiconductor substrate. forming a second oxide film on the upper polycrystalline silicon layer; forming a resist curved pattern corresponding to the stacked layer pattern and a resist middle pattern corresponding to the single layer pattern on the upper polycrystalline silicon layer; After selectively removing the second oxide film using these resist fist pattern masks, the upper polycrystalline silicon layer is patterned, and the resist +-
- After removing the pattern, form a resist film having the lower polycrystalline silicon pattern V and openings on the substrate, and form a resist film having the lower polycrystalline silicon pattern V and the lower polycrystalline silicon 9 patterns exposed in the resist film and the openings. Using the second oxide film on the pattern in the upper polycrystalline silicon formed thereon as a mask, selectively etching the pattern of the lower polycrystalline silicon by a drying process (9 steps) and a etching method (7). A method for manufacturing a featured semiconductor device.