JPS58224500A - Intermittent memory failure relief method - Google Patents

Abstract

PURPOSE:To prevent a normal main memory device from being mistaken as a defective one by the trouble of an I/O system by preparing a means to rewrite data read out from the main memory device when a central controller detects an error in the data and then read out the data again to check the error. CONSTITUTION:Parity data pd' including an error are written from defective I/O system device IO and subchannel device SCH in the address (a) of the main memory device MM0. When the central controller CC reads out the data pd' and a parity check circuit PC detects the error, a data correcting means DC reads out the data pd' from the address (a) of the MM0, a parity code generating circuit PG rewrites the data pd' to pd'' and then the means DC reads out the data pd'' again from the address (a) to check the error by the circuit PC. When no error is detected in the data pd'', it is discriminated that the main memory device MM0 is normal.

Description

[Detailed Description of the Invention] +8+ Technical Field of the Invention The present invention relates to an intermittent memory fault relief method, particularly an intermittent memory fault relief method for an electronic exchange having a function of directly transferring data between an input/output system device and a main storage device. Regarding.

(bl) Prior Art and Problems Figure 1 is a diagram showing an example of a conventional electronic exchange of this type.
and MMl, subchannel device S CH1 input/output control device and input/output device (hereinafter collectively referred to as input/output device IO) are shown, and other parts unrelated to the present invention are omitted. Note that the main memory device MMO is currently used as the active system, and the main memory device MMI is used as the backup system. Further, the subchannel device SCH has a function of directly transferring data between the input/output device IO and the main a device MM based on a command from the central control device CC. Furthermore, the central control unit CC and the male channel unit SCH each include a parity code generation circuit PC and a parity check circuit PC, and add a parity check code to the data d stored in the main memory MMO to generate parity data p (l). Create and write,
Further, a parity check is performed on the parity data pa read from the main memory device MM to determine whether there is an error. In this state, input/output device ■0 and subchannel device SCH
Suppose that the parity data pd' containing an error is written to address a of the main memory MMO. If the central controller CC does not read the parity data pd' from the address a of the main memory MMO, the parity check circuit PC detects an error and activates the fault handling mechanism ER. The failure processing mechanism ER determines that the main memory device MMO is affected and disconnects it from the active system, and uses the main memory device MMI, which was in a standby state, as the active system. However, if the input/output system device IO and the subchannel device SCH are still affected, the same process is repeated again, and even the main memory device MMI is determined to be affected and is separated from the active system. As a result, main memory MMO
and MMI will experience a double failure, and the electronic exchange in question will have no choice but to stop operating.

As is clear from the above explanation, in a conventional electronic exchange, the input/output system device 10 and the subchannel device SC
Due to the failure of H, the normal main memories MMO and M
There was a drawback that MI was determined to be affected and the electronic exchange concerned was shut down.

tc+ Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of conventional electronic exchanges as described above, and to prevent a normal main storage device from being determined to be damaged due to a failure in an input/output system device. The object of the present invention is to realize a means for maintaining the operation of the electronic exchange.

(di) Structure of the Invention The object of the present invention is to, in an electronic exchange having a function of directly transferring data between an input/output system device and a main memory device, when a central control device detects an error in data read from the main memory device; This is achieved by providing a means in the central control unit for rewriting the data in the 1a device and then reading it again for error checking, and determining whether or not the main storage device is affected by the error check result of the means. .

(e+　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing an intermittent memory fault relief system according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, a data correction mechanism DC is provided in the central control unit CC. In the same process as shown in FIG. 1, parity data pd' containing errors is written from the affected input/output system device IO and subchannel device SCI to address 1-a of the main memory device MMO. Suppose that In this state, the central controller CC successively outputs the parity data pd' from address a of the main memory MMO, and when an error is detected by the parity check circuit PC, the data correction mechanism DC is activated. The data modification mechanism DC reads the parity data p (1' again from address a of the main memory device MMO and extracts data d'), and then generates a parity check code by the parity code generation circuit PG in the central control unit CC. After rewriting the address a of the main memory MMO with the added parity data pd'', the parity data pd'' is rewritten from the address a.
The error check is performed by the parity check circuit pc. As a result, if the parity check circuit PC does not detect any error in the parity data pd, the main memory device MMO is determined to be normal and continues to operate as the active system.If the parity check circuit PC detects no error in the parity data pd ”
If the problem is detected, the data correction mechanism DC determines that the main memory MMo is affected for the first time, activates the failure handling mechanism ER, and restores the main memory MMo as in FIG.
The MO is separated from the current thread, and the main memory device MMI is operated as the current thread.

As is clear from the above description, according to the present embodiment, the central control unit CC continuously outputs parity data pd' containing errors caused by failures in the input/output system device IO and the subchannel device SCH from the main memory device MMO. Even in this case, do not disconnect from the active system immediately, but rewrite it using the data d' extracted from the corresponding address a, and then perform an error check again using the parity data pd'' read from the address a, and check the result. The normality of the main memory MMO is determined based on the normality of the main memory MMO or MMI.
This prevents the electronic exchange from being stopped due to being mistakenly recognized as abnormal and being disconnected from the active system.

Note that FIG. 2 is only one embodiment of the present invention; for example, the central control unit CC is not limited to one that immediately starts the data correction mechanism DC after detecting a single error; Many other modifications may be considered, such as eliminating intermittent faults by starting when an error is detected even after multiple readings, but the effects of the present invention do not change in any case. Furthermore, the configuration of the central control unit CC is not limited to that shown in the figure, and many modifications can be made to the communication realized by a program, for example. i! :However, the effect of the present invention remains the same in either case. Furthermore, it goes without saying that the configuration of the electronic exchange to which the present invention is applied is not limited to that shown in the drawings.

ffl Effects of the Invention As described above, according to the present invention, in the electronic exchange, the compressed main storage device is prevented from being mistakenly recognized as being affected due to a failure in the input/output system device, and the main storage device is redundant. The danger of causing a failure or the like and causing the electronic exchange to stop operating is eliminated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional electronic exchange, and FIG. 2 is a diagram showing an intermittent memory fault relief system according to an embodiment of the present invention. . In the figure, CC is the central control unit, MMO and MM
I is the main storage device, SCH is the subchannel device, IO is the input/output system device, PG is the parity code generation circuit, pc is the parity check circuit, ER is the error handling mechanism, DC is the data correction mechanism, d and d' are data, pd, pd' and p
d" indicates parity data. Figure 1 Early Figure 2

Claims (1)

[Claims] In an electronic exchange having a function of transferring 1H connection data between an input/output system device and a main memory device, when the central control device detects an error in the data successively sent from the main memory device, the data in the main memory device 1. A memory intermittent fault relief system, characterized in that the central control unit is provided with means for reading out again after rewriting and checking for errors, and a fault in the Mi+ memory storage device is determined based on the error check results of the means.