JPS58214922A - Overvoltage output prevention device in stabilized power supply - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for preventing overvoltage output from being output from a stabilized N source, even temporarily.

FIG. 1 is a block diagram showing a conventional overvoltage output prevention method in a stabilized power supply.

The figure shows an example of a switching regulator as a stabilized power supply. In the figure, 1 is an error amplifier, 2 is a switching control circuit, 3 is an overvoltage monitoring circuit, 4 is a switching transistor, and 5 is an error amplifier. u
1 is the output voltage setting value output, and 6 is the switching stop command output from the overvoltage monitoring circuit 3.

The operation of this circuit as a stabilized power supply is as follows.

When an error occurs in the output voltage Eo with respect to the rated value (in this case, the reference voltage included in the error amplifier 1), that error is amplified by the error amplifier 1, and the output voltage setting value 5 is increased or decreased by a value commensurate with the error. The signal is then input from the error amplifier 1 to the switching control circuit 2. The switching control circuit 2 is
The switching of the switching transistor 4 is controlled according to the input output voltage setting value 5, and the outputs W, FfE
It works to cancel out the error. In this way, a stabilized output voltage Eo is obtained.

Next, the operation for preventing the occurrence of excessive WL1 output will be explained with reference to FIG. A failure occurs in the nursing care difference amplifier 1,
Assume that the output voltage set value 5 has therefore increased (see time TO in FIG. 2). Then, due to the operation of the switching control circuit 2 and the switching transistor 4, the output voltage E□ starts to increase (see time T1 in FIG. 2). The output voltage and pressure EO continue to increase, and when they reach the overvoltage detection level of the overvoltage monitoring circuit 3 (see time T2 in FIG. 2), the overvoltage monitoring circuit 3 issues a switcher stop tI: command 6.
It is output to the switching control circuit 2. The switching control circuit 2 that received this command stops switching the switching transistor 4, and therefore at this point (
From time T3 in FIG. 2, the output voltage Eo begins to drop.

In this way, conventional overvoltage output prevention methods detect overvoltage after it has already occurred at the voltage output terminal and stop switching. , time T2-T in FIG.
In section 4, an overvoltage exceeding the overvoltage level is output to the output terminal, resulting in application of the overvoltage to a load (not shown). Additionally, in general, the overvoltage detection level in the overvoltage monitoring circuit 3 is set to a considerably higher level than the rated output voltage level, taking noise, transient response of the power supply, etc. into consideration, and therefore, even though it is below the overvoltage level, , the overvoltage that occurs in the interval from time T1 to time T5 in FIG. 2 often adds stress to the load.

In this way, in the conventional method, a high voltage exceeding the overvoltage level is applied to the load (between times T2 and T4 in Figure 2), and a time period during which a high voltage higher than the rated level is applied (time T2 in Figure 2).
1 to T5) is also long, which has the disadvantage that the reliability of the subsequent operation of the load (for example, IC, other electronic circuits, etc.) decreases.

The present invention has been made to eliminate the drawbacks of the prior art as described above, and an object of the present invention is to prevent the occurrence of overvoltage exceeding the rated voltage, thereby reducing the reliability of the operation of the load. An object of the present invention is to provide a method for preventing the occurrence of overvoltage output in a stabilized power supply.

The main point of the configuration of the present invention is to provide two sets of error amplifiers in parallel in a stabilized power supply, to clamp the output side potentials of each set mutually, and to detect the potential difference between the outputs of the two sets of error amplifiers. , so as to stop the operation of the switching control circuit when it exceeds a predetermined limit,
The point is that overvoltage output is inherently prevented from occurring.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram showing a main part of an embodiment of the present invention. In the figure, 1o is an error amplifier circuit, 2° is an abnormality detection circuit, 11 is a reference voltage, 12 is a first error amplifier, 13 is a second error amplifier, 21 is an OR gate, 22 is a first comparator, 23 is a second comparator.

In this method, in the error amplifier circuit 1o, the error amplifier 12
By duplicating the error amplifying section by 13 and 13, it is possible to prepare for the occurrence of a failure. Error amplifier 12 and 1
The ten-power and -man-power of 3 are connected respectively, and the ten-man power is connected to the reference voltage 11, and the -man power is connected to the output terminal of the power supply. Therefore, when the power supply output [IE] deviates from the reference voltage 11, the output EI HR2 of the error amplifier 12.13 changes so as to reduce the error, which is the amount of the deviation. Output Elp1・Resistor 111. The average value is input to a switching control circuit (not shown) via 几2 + R3t ``4, and the output voltage value is corrected by controlling the switching of a switching transistor (also not shown). The diode Di * D2 connected in a spiral shape is R'l "" R2e
There is a relationship R'3=R4, and error amplifiers 12 and 1
If each gain of 3 is the same, whether or not it exists is completely irrelevant for normal winning difference amplification operation.

However, during operation of this circuit, one error amplifier, for example 12
Suppose that a failure occurs and its output, the output setting voltage El, becomes abnormally high. When the output setting voltage E1 increases, the voltage at point , to prevent it from being sent to the switching control circuit. On the other hand, if the failure occurs not in the error amplifier 12 but in the error amplifier 13, the voltage at point y, which is the connection point between the resistors R2 and R4, is changed to the output voltage E1 of the first error amplifier 12 by the diode D2. be clamped. In this way, the error amplifiers are duplicated in this method, so even if one error amplifier fails and outputs an abnormal voltage,
The configuration is such that an abnormally high output setting voltage is not sent to the switching control circuit, and therefore the output voltage of the stabilized power supply does not become an overvoltage.

Next, the abnormality detection circuit 20 will be explained. When the voltage difference between the input a and b increases beyond a certain range, the zero abnormality detection circuit 20 sends a switching stop command to a switching control circuit (not shown) through an OR gate. This is a circuit that outputs from 21.

Inputs a and b of the abnormality detection circuit 20 are the output g1 of the error amplifier 12 and the output E2 of the y-difference amplifier 13, respectively. Therefore, if the error amplifier 12 or error amplifier 13 breaks down and the balance between its respective outputs El and R2 is lost, and the absolute value of the difference value IEI-E2+ exceeds a certain limit value, a switching stop command is sent. It is supposed to be done.

The first comparator 22 detects an abnormality in the case of El:)R32, and the second comparator 23 detects an abnormality in the case of El(R2).

If the reference voltage for setting is ), this abnormality detection circuit outputs a switching stop command. Therefore, resistors R5, R,6
The abnormal level can be freely selected and set using the abnormal level setting reference voltage vA.

As mentioned above, in this method, the error amplifier is duplicated,
Clamp abnormal outputs to each other. Then, the balance between the output voltages of the two error amplifiers is monitored, and if the balance is lost, it is determined that a failure has occurred in one of the error amplifiers, and a switching stop command is immediately output. Therefore, as shown in FIG. 4, even if the error amplifier fails, no overvoltage is generated at the power supply output terminal, so the reliability of the load will not be degraded.

According to this invention, the error amplifiers are duplicated, and the configuration is such that mutually abnormal output setting voltages are clamped to the normal setting voltage, and a separately provided abnormality detection circuit checks the balance between the outputs of the two error amplifiers. By determining whether there is a failure in either one of the error amplifiers,
When the error amplifier malfunctions, there is no need to generate any overvoltage at the power supply output terminal.

This invention can be applied not only to the switching regulators described above but also to series regulators. Furthermore, since the abnormality detection circuit detects the imbalance between the two error amplifiers, it is possible to immediately detect abnormalities in the error amplifiers other than the overvoltage mode.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional overvoltage output prevention method in a stabilized power supply, and FIG. 2 shows the output voltage setting value 5 and output voltage E in the circuit of FIG. 3 is a circuit diagram showing the main part of an embodiment of the present invention; FIG. 4 is a timing chart showing the relationship between the output voltage setting value and the output voltage in the circuit of FIG. 3; It is. Description of symbols 1...Error amplifier, 2...Switching control circuit, 3...Overvoltage monitoring circuit, 4...
... Switching transistor, 5 ... Output voltage setting value, 6 ... Switching stop command, 1
0...Error amplifier circuit, 11...Reference voltage, 12.13...Error amplifier, 20...
・・Abnormality detection circuit, 21・・・・−・OR gate, 22
．． 23... Comparator 1, agent patent attorney
Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 1 Figure 4 Figure 2 Figure 3

Claims (1)

[Claims] 1) In a stabilized power supply comprising an error amplifier that detects the difference between an output voltage and a reference voltage and outputs it as an error voltage, and a switching control circuit that controls input-side switching means so that the error voltage becomes zero. , the error intensifier is 2
A pair of error amplifiers are provided in parallel, and includes means for mutually clamping the output side potentials of the respective error amplifiers, and means for detecting a potential difference between the outputs of the two sets of error amplifiers, and when the potential difference exceeds a predetermined limit. 1. A method for preventing the occurrence of overvoltage output in a stabilized power supply, characterized in that the operation of the switching control circuit is stopped when: