JPS5821382A - Manufacture of schottky barrier diode - Google Patents

Abstract

PURPOSE:To obtain the stable Schottky-barrier-diode by a method wherein a window is bored to an oxide film on an N type Si substrate, an N<+> diffusion layer is formed from N type poly Si coating the wndow, a metal is deposited and a silicide is shaped. CONSTITUTION:The window is bored to the SiO2 42 on the N type Si substrate 11, the poly Si 43 is deposited, As ions are implanted, and the N<+> layer 45 with approximately 500Angstrom depth is formed through treatment at 900 deg.C. The poly Si 43 is removed selectively so as to completely coat the window, and Pt 46 is deposited and alloyed in N at 600 deg.C. Accordingly, the poly Si, the Si substrate and an interface are also changed finally into PtSi. The PtSi-Si interface is positioned into the impurity profile of the layer 45 by properly selecting the film thickness of the poly Si and Pt, impurity diffusion from the poly Si, an alloying temperature and time. Lastly, a barrier metal 48 and wiring 49 are stacked, and the diode is completed. Accordingly to this constitution, the characteristics are stabilized, and the diode can be controlled arbitrarily by a forward characteristic and the quantity of the ions doped into the poly Si.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single barrier diode (SBD).
).

A Schottky barrier diode is a Schottky barrier diode that absorbs the energy barrier formed by the contact between the
It is a sexual barrier. Follow me.

Injection of minority carriers hardly occurs, and its forward voltage is smaller than that of a pn diode, so it is often used as a clamp diode for pnli combinations when high performance is required. One example of this is the switch, barrier, diode, clamp, NPN)2 resistor, and the low-voltage switch TTL circuit that uses it is now widely used as a high-speed logic element. ing.

As shown in FIG. 1, this SiC Otky barrier diode is conventionally used as an insulating film 810, II t formed on an N-type silicon substrate (1) or an N-type epitaxial layer.
2) is provided with an opening (3), and has a structure consisting of wiring gold (415) via a gold-silicide layer (4).

As the metal silicide layer (4), silicide with wiring metal AI is most often used, but in this case, λ and 8
The (111) plane of the silicon substrate is mainly used to prevent alloy pits from occurring with 4.

On the other hand, the platinum silicide layer can be used regardless of the substrate surface orientation! It is often used in place of silicide and has excellent reliability. In this case, Ti-? It is necessary to insert W or the like between the PTSI and the MU 4. FIG. 2 shows the cross-sectional structure of a Pt81-Ti-Aj SiC Schottky barrier diode. 840. on N-type Rico/group f91. Opening part (2) of @ is pt
It is converted into silicon, and a barrier metal and wiring AI@ are formed.

The biggest problem with such conventional structures is the low tensile strength of the insulating film. A Ptai layer was formed by opening a hole, depositing Pt, and heat-treating it.

By rounding HF46 field to remove oxide on Ptai layer when depositing barrier metal, wiring metal.

The opening edges (2) and (to) are etched, and Pt5
j The untreated N-type silicon substrate surface (2) is exposed.

A portion where the barrier metal and the N-type silicon substrate are in direct contact appears. As a result, as shown in Fig. 2, a parallel diode is formed with 5BD (end) of ptsi and 5BDc19 of Ti-8i.
The forward voltage vF of the entire 88D varies depending on the area of the exposed S@, and it is not possible to form a stable 98BD. Further, it also causes deterioration of forward characteristics. As a method to solve these problems, a method has been put into practical use in which a pna-matching guard/linda is formed on the S* side of the 8BD aperture to improve the desired direction and reverse direction characteristics, but this causes a drop in the degree of integration. Therefore, they cannot be used as internal elements of highly integrated devices, and are only used as transistors or diodes in input/output sections.

Here, the forward current J of 8BD is.

V is the forward voltage, k is Boltzmann's constant, n is a constant indicating the junction state, M0 is Richard Non's Articles of Incorporation, and q is the electric charge. It is identified from the angle T and barrier hide ΦBK. The saturation current J is influenced by the magnitude of -1; if -8 is large, J becomes small and the forward voltage Vl becomes high. - If φ8 becomes smaller, J will increase and the actual ratio F will decrease.

Depending on how you choose the value of φ8, 8BD
Since the characteristics change, desired characteristics can be obtained. In order to change Φ8, one is to change the ms of the metal that forms 8BD.

In the former case, there is a method of lowering the barrier in the semiconductor fi[ due to the difference in work function K, and lowering the barrier and rear-hyde.
In actual use, freely changing the 8BD metal is not necessarily an appropriate method considering compatibility with other pro-7s.

Currently, the most commonly used metals are An, Pt81. W etc. are ayu, each -8 ha 0.
7 eV, 0.85 eV, 0J11 eV (F
) iEt On the other hand, the latter method of changing the impurity concentration of the conductor layer is used because if the impurity concentration is made very high, it will result in an ohic contact.
You will have to choose more appropriately than IK. Also, increasing the level of impurity in the conductor layer causes a decrease in reverse breakdown voltage at the same time. ~Not a preferred method.

As a way to improve this, IBgg TramsFI
D Vol, nD-27, No, 2. 1980
p, 420°J, B, Bindell at al
As disclosed in K, by implanting ions at a concentration of ^ into the =J& plane of the semiconductor, the electric field strength near the 1 surface □ is significantly increased, the tunnel Linda phenomenon is overcome, and the barrier hide is effectively reduced. A method has been proposed in which the barrier hide is controlled by the amount of ion implantation. For example, O~I
When injecting 35 keV, vl is 0.4~G from K
, 1 eV1. In this case,
It is shown that the reverse voltage VB hardly decreases when vF changes from 0.4 to 0.25 eV.

Rather than controlling the above-mentioned vy by ion implantation, Kameaki Moto sometimes proposes a new method for manufacturing 8BD to obtain a similar effect. Furthermore, it is an object of the present invention to propose a method that can prevent property deterioration at the end of the opening. In other words, an insulating film having holes is selectively formed in the area where 8BD is formed on a conductivity type silicon substrate, and polycrystalline silicon containing one conductivity type impurity is deposited on the entire surface including the openings. , the impurities present in the polycrystalline silicon are diffused into the yycon substrate to form a very thin highly doped layer on the substrate am. Thereafter, the polycrystalline silicon remains so as to cover the pores, and the rest is removed, after which metal is deposited to turn the polycrystalline silicon into metal silinide. Finally, the remaining metal is removed, wiring metal is formed, and 8BD is manufactured.

The manufacturing method of the present invention will be explained in detail using rattan figures 3 (1) to (e). In FIG. 3 (Supplementary), a silicon oxide film is grown on the surface of the N-type silicon substrate or the N-type epitaxial layer 4, and holes are formed in the 8BDll part. 311
In (b), an unbuttoned polycrystalline silicon layer of, for example, 1000 layers is deposited on the entire surface, and A$ ions, for example, are implanted into the polycrystalline silicon by an ion implantation method. Next, for example, at a high temperature of about 900°C, KI91 is activated as shown in Figure 3(c).
The impurity is diffused to the substrate side, and an impurity profile as shown in FIG. 4 is obtained.

At the time of
It is desirable that it be 1 degree. Then, the polycrystalline silicon is left to completely cover the 88Dli hole, and the rest is removed. jIS diagram (d) K As shown in f, for example, platinum is 5
ooi was deposited on the entire surface and heated at 600°C in a N atmosphere for 3
Alloy for 0 minutes. As another method, treatment may be performed by V-ther or Cytoexternal irradiation.

In this case, the conversion of polycrystalline silicon to Pt5l proceeds rapidly mainly along the grain ballast, and the interface between the polycrystalline silicon and the 81 substrate, which is the largest ballast, is also converted to ptst, and the Si substrate is also converted to Pt81. As a result, a PtSi--Si field is formed at the position shown in Fig. 4, and an 8BD barrier is formed there.

The point of the present invention is that it is important that this ptst-sm interface is located within the impurity profile, so that the process conditions, e.g.
[FjIL, platinum film thickness, impurity diffusion from polycrystalline silicon, alloying temperature and time need to be selected.

Finally, as shown in Figure 3 (@), platinum silinide 1-
Barrier metal and wiring metal are deposited on top of the wafer and processed to form 8BD.

By using the present invention, the above-mentioned IBgliTran
s EID-27, Ma2.1980. P420K
The following drawbacks of the disclosed method can be eliminated. According to Imukikai Chiho, ion implantation forms an impurity distribution near the surface, so heat treatment is required to activate it and remove radiation damage. Qin case and condition 1 where redistribution of impurities does not occur
For example, the conditions for maintaining the ion implantation profile of Muhata may not match, and the wiring metal pretreatment at the edge of the opening is likely to cause redistribution to remove irradiation damage. 8jO, there are disadvantages such as instability of forward characteristics due to film etching. The present invention can eliminate these drawbacks and provide stable 8BD
It is possible to obtain @ properties and to arbitrarily control forward characteristics by adjusting the amount of impurities added to polycrystalline silicon.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing a conventional SBD structure. FIG. 2 is a schematic cross-sectional view showing an 8BD structure having a conventional barrier metal. Figure 3 (--1) is a cross-sectional schematic diagram showing the manufacturing process of 8BD of the present invention. Figure 4 is the relative positional relationship between the impurity distribution near the interface between polycrystalline silicon and the 8A substrate and the Pi pull-up image. In the figure, 41... Insulating film. 43... Polycrystalline silicon layer. 44... Impurity ions. 45... Impurity diffusion layer. 46. ... Metal layer. 47 ... Metal silicide layer. 48 ... Barrier metal. 49 ... Wiring metal.

Claims (3)

[Claims] (1)--A step of forming an insulating layer selectively having an opening on a conductive semiconductor substrate, and forming an insulating layer on the insulating film and the opening,
- a step of forming a polycrystalline silicon layer containing a conductivity type impurity; a step of diffusing one conductivity type impurity from the polycrystalline silicon layer to form a diffusion layer having a desired impurity distribution in the semiconductor substrate; It is characterized by comprising a step of selectively removing polycrystalline silicon other than the hole portion, and a step of depositing a metal film on at least the polycrystalline silicon layer and converting the polycrystalline silicon layer into a metal silinide layer. A method for manufacturing a Schottky barrier diode. (2) A patented barrier diode linear velocity method, characterized in that impurities of one conductivity type are introduced into the polycrystalline silicon layer using ion implantation. (3) The interface between the #article crystalline silicon layer and the #generated conductor substrate is characterized by depositing a metal film in an amount necessary for at least metal silicidation - Claim 1 of the Patent
←・Method for manufacturing barrier diodes. t4) Paragraph 1 of the 4I fraudulent claim, characterized in that the interface between the metal silicide layer and the conductor substrate is located within the impurity diffusion layer of one conductivity type. Method of manufacturing Palya diode.