JPS58207666A - Already diffused integrated circuit and method of connecting same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pre-diffused integrated circuit in which a network of all four identical cells is pre-singled.
tegrated circuits), 6[
11i self cell.

They are interconnected in series as required to implement the desired logic function. The present invention also relates to a method for interconnecting cells of an integrated circuit.The initial method for fabricating integrated circuits was to utilize the desired logic circuitry to form a single cell.

It consists in replacing the logic function of said circuit with an array of interconnected transistors. Subsequently.

These cells are interconnected to perform the desired circuit logic function.

This method developed for single gates has been found to be impracticable when the degree of complexity of the logic functions to be integrated becomes excessive. The ultra-large scale integrated circuits currently in use are! J! It actually consists of tens of thousands of transistors. The length of time required to embed this large number of transistors, as well as the corresponding connecting conductors of the transistors, is therefore sufficient to abandon this method altogether.

Therefore, interest has focused on systems based on computer-aided design with the use of standardized cells stored in libraries of computer systems. The interconnection of the cells may be performed with computer aid, ie by computer processed wiring algorithms.

Two methods based on this principle are currently in use. The advantages and disadvantages of these methods are complementary.

The so-called standard cell technology consists in making use of relatively complex logic functions arranged on the available surface of the substrate, taking into account the necessary interconnections between the logic functions. Cell digit positions should take into account interconnections, and interconnections should take cell digit positions into consideration.

In this manner, by arranging the cells and interconnects with maximum packing density, the substrate area available for integration can be maximized. On the other hand, each integrated circuit is quite unique, thus creating the need for a complete set of masks. This need is specific to the circuit to enable fabrication. In this way, any changes that become necessary during the development of the circuit are likely to affect the entire mask. In that case, the entire mask must be made again. Similarly, in order to obtain a modified circuit, the entire fabrication process must be repeated again after changing the mask. In this way, the entire manufacturing process takes a relatively long time! 4. Therefore, increasing the area of the substrate optical surface is offset by a loss in manufacturing time.

Another method, known as diffused network technology, consists in constructing very simple arrays of cells, which are
All are identical to each other and are arranged in a series of columns separated by free spaces ru1 of a predetermined width.

The logic functions to be integrated may be obtained by depositing a network of aluminum connecting conductors through a mask in the final stage of the fabrication process. This mask is specific to the desired logic function.

As is readily understood, this network of interconnections must meet the phase limitations imposed by arranging the diffused cells in columns. Since the clearance space allowed for interconnections is necessarily limited, if the functions to be integrated are of any complexity, the interconnections will fill up the paths provided for the connecting conductors. Under such conditions, one cell remains unconnected and used, ultimately resulting in a loss of useful area of the substrate surface. On the contrary, due to the fact that there is no longer any need to provide more than two or three special masks, and the fabrication of the circuit only requires the deposition of an aluminum interconnection grid on the substrate that encompasses the entire cell. Increases implementation speed. Deposition of this grid is an easy and quick step during the fabrication process. A lengthy and difficult step was taken prior to mass production of diffused networks. This pre-spread network can be obtained from stock.

The present invention seeks to reconcile the advantages of these two methods and avoid the drawbacks of these two methods.

A type of diffused integrated circuit is proposed that includes an array of elementary cells on a substrate. A unique feature of the invention is the fact that said columns are connected in series to each other and cover the entire surface of the substrate.

Other features of the invention will become more apparent upon consideration of the following description and accompanying drawings.

The basic cell of the low diffusion circuit shown in FIG.
S) It consists of transistors, and these transistors are connected in series and in pairs. The two upper MO8) transistors are p-type transistors in series. The drain and source electrodes of these transistors can be accessed at points grouped in pairs. In this way, the source of the right transistor can be accessed via point 101 and the drain of the right transistor, which is common with the source of the left transistor, can be accessed via point 102. The drain of the left transistor can be accessed via point 103. In practice, these transistors are symmetrical, and the electrodes can be either drain or source depending on their use in the final circuit, so when used in such a relationship, the drain Alternatively, the name source is purely formal.

Similarly, the bottom pair of transistors are series n-type transistors, in which case the source of the right transistor can be accessed via point 104, the drain of said transistor and the source of the left transistor (common). ) can be accessed via point 105 and the drain of the left transistor can be accessed via point 106.

Each of these transistors has a gate, and the gate 107 is common to the straight-line transistor on the right p-type transistor electrode side.

And the gates are connected together such that gate 108 is common to the left p-type transistor and the left n-type transistor. The gate 107 can be accessed via two points 109 located at the top and bottom,
Also, gate 108.

It can be accessed via two similarly arranged points 110.

This double wiring for access points to separate transistor electrodes as well as cell interconnections.

The purpose is to facilitate interconnection of the transistors.

The access point to the drain of the p-type transistor and the p-
between the access point to the source of the n-type transistor and the access point to the drain of the n-type transistor and the n
- by means of two busbars extending through the cell, respectively, between the access point to the source of the -type transistor;
A voltage VDD and a voltage VSS are supplied to the p-type transistor and the n-type transistor, respectively.

The interconnection grid required to provide the desired logic functions, i.e. cell columns such as columns 202 and 205, is then shown in FIG. The wafer is deposited on a substrate 201. Cells in these columns are usually separated by spaces 203. This space includes, for example, space 2 that separates column 202 from column 205.
04, and a space 20 disposed between the column 205 and the next column.
A conducting wire for establishing a connection between the terminal and the terminal 6 is passed through. usually,
1 during the stages associated with the fabrication of gates 107 and 108;
The cell is formed, for example, by depositing polycrystalline silicon.

During the same fabrication stage, a series of inter-column connections, such as the inter-column connections designated by reference numeral 207, are also formed, f], on the integrated circuit to be tested as is in preparation for forming the next vertical connection. The corresponding logical function is.

This is accomplished by providing connections between different transistors in different cells. This interconnection operation is performed from one transistor to the next by first interconnecting the transistors in the same cell and then connecting the transistors of several adjacent cells with conductive lines that do not extend beyond the cell column. It is preferable to use a transistor\. There are a certain number of single-logic functions that can be obtained in this way, and one of these functions is shown as an example in FIG. 3, namely a two-way NAND-type gate.

For this purpose, two p-type transistors are fed in parallel from a supply bus VDr) via metallization 301 and 303. These metal processing parts are connected to the drain connection holes 101 of the two transistors.
and 103, respectively. In this case, the electrode common to these two transistors serves as the source and is connected to the metallization 302 via the bottom hole 102. This metallization connects the electrode to the source of the right n-type transistor through a hole 104 in the top.

In this case two n-type transistors are used in series.

These common connections are therefore not connected to any external circuitry. On the other hand, the drain of the left n-type transistor is connected to the supply bus VSg via metallization 306. This metallization connects the hole 106 to the bus bar vSS. A supply circuit for a NAND cell is thus obtained.

Two input logic states are applied to gates 107 and 108 by two connecting conductors A and B through top holes 109 and 110. As can be easily understood, these two logic states are connected to holes 109 and 1 at the bottom of the gate.
It is also present on 40 and can also be used, for example, to apply to another gate by means of other conductors A and B. These conductors are connected to the bottom holes. The output logic state S of the gate is obtained on the connecting conductor 302 and also on the bottom holes 102 and 104. In the illustrated embodiment, this logic state is applied to connecting conductor 304. the conductive wire is adjacent to the cell shown on the right;
It extends through the holes 314 to the cells connected to the vertical connections between the cells.

In particular, considering the disturbances presented by the crossing of the supply buses VDD and VSS, it is clear that a very limited number of logic functions can be performed using connections that are entirely internal to the cell string. In practice, the connections internal to each cell are originally used, thus simply connecting the inverter and the NAND-
It becomes possible to provide gates or N0R-gates.

In order to advance further, in addition to this connection, the inter-column space 204
It is necessary to proceed to However, in such cases, only basic logic circuits are needed! In practice, it can be considered that it also forms part of the general interconnection of the gates of the network.

Of course, just an inverter, a NAND-gate and a NOR-
Although it is possible to perform arbitrary logic functions with gates, the wiring immediately becomes more bulky and takes up more space than would be the case with a relatively complex function such as a basic logic circuit.

To achieve this interconnection of cells in an inter-column space, such as space 204, connections 2 parallel to the busbars VDD and vSS are arranged so as to extend along a certain number of predetermined axes within the inter-column space.
0B is provided. In the case of those connections directly adjacent to the columns, said connections are carried by metal conductors to the output points of the gates such as 109 and 110 and to the output points of the sources and drains such as the sources and drains indicated by reference numbers 101 to 106. Can be connected. This metal conductive wire is essential together with the connection 208. In the case of another connection, the intercolumn connections 207 need to be passed through unless the metal conductors that can separate these connections from the cell rows are interrupted at the point of passage toward the appropriate cell. The inter-column connections are buried beneath an insulating layer that separates the final metallization from the rest of the circuit. Then in the insulating layer in a process step prior to metal processing.

The necessary holes are formed.

Therefore, if another interconnection is decided upon, the fabrication of the integrated circuit accordingly begins with a diffused circuit covered with a protective oxide layer and, in the case of the first operation, drain, source , to drill holes that communicate with gates, buried inter-column connections, and inter-space connections. In a second step, a metallization deposit of aluminum is formed to interconnect these various holes, depending on the desired configuration.

Considering the various limitations already explained, it is clear that increasing the number of cells cannot be effectively applied to anything other than a certain degree of complexity.In this way, interconnections can be constructed in one step. For small size diffused networks, a packing density of 80 inches is considered satisfactory.

Although this value is satisfactory,
This packing density means a 20% loss in substrate surface area. Once it becomes necessary to employ automatic routing devices above a certain size, the packing density decreases substantially, dropping rapidly to 50 inches or even less. This value is a very poor result6 According to the present invention, the first measure to provide sufficient space between cell rows, regardless of the number of connections to be made, is to create a special space between these rows. By arranging these columns consecutively without providing any space, the space between the columns such as reference numeral 204 can be suppressed. To achieve the necessary connection between two cell columns, current is supplied to these two column numbers rather than to the column located between the ties. This 'WL flow non-supply column is covered with an oxide layer\
Keep it. The aluminum connections can be deposited on the oxide layer since they are not disturbed by the non-current carrying cells located below. If the space thus obtained is not sufficient, the second row of cells may also not be supplied with N flow, thus enlarging the space to accommodate all the necessary connections. It becomes possible. If such a need arises, it is still possible to expand the space by further increasing the number of non-current-supplied cells.

This method is important because buried polycrystalline connections, such as connection 207, are no longer available for making conductor crossings, so the method adopted for interconnection involves two aluminum layers separated by one insulating layer. I am sure that it will be necessary to use it.

More specifically, the surface f'i of the diffused circuit of type σ)
lt is shown in Figure 4. In this case, six cell formations are provided for three consecutive columns.

In this structure, in order to facilitate interconnection, the basic cells actually used correspond to half-cells with respect to the basic cells of FIGS. 1 and 3.

In effect, successive columns are alternately p-type and n-type, and the gates of the transistors in the p-column are not connected to the gates of the transistors in the next n-column.

Under these conditions, the block 411 outlined with dashed lines
The two elementary cells enclosed within correspond to the complete cells shown in FIGS. 1 and 3.

Additionally, to allow wires to pass through the cell relatively easily.

Moved the source output point and drain output point to the same level as the gate output point. Therefore, the output points 401, 402 and 403 are located in an additional portion consisting of a region corresponding to the drain and a region corresponding to the source.

With the surface area freed in this way, it is possible not only to run one supply connection 1VDD or VSS in the longitudinal direction between said output points, but also to Furthermore, another 2 (i;;l connections 412 and 413
It becomes possible to pass through. Although these connections are shown as being continuous, it will be appreciated that in practice only the small portions necessary to achieve a connection between two or more consecutive points are deposited.

Furthermore, in this structure, the four rows between the top row and the middle row
A small inter-row space is provided to pass the connections such as 14 or 415 between the middle row and the bottom row. Under these conditions, if power is not supplied to the middle row,
A VSS supply bus arrangement is available for making interconnections. Therefore, considering the other two interconnection lines 4161 and 417 inside the column, we get five lines including lines 414 and 415, which can be used for interconnection. . This corresponds to the most common utility in spread circuits.

If the available space proves to be insufficient, power is not supplied to the bottom row, thus four additional interconnect lines are available, and if the same method is continued Even larger numbers of connecting lines can be used.

In order to make the interconnection in the vertical direction, a method is adopted which requires the use of double metal layers, as mentioned at the beginning. According to this method, once the interconnections have been achieved by the aforementioned lines, an insulating layer, such as silicon oxide, is deposited over the circuit and a series of vertical interconnect lines are then provided. This vertical interconnect line is crossed with the horizontal interconnect to allow the formation of an entire intersection.

In the illustrated embodiment, there is also a space between successive cells in the same column that is substantially equal in width to the space that exists between successive columns. It is therefore possible to place a vertical connection passing between two cells in order to provide an interconnection between a horizontal connection placed above a column and a horizontal connection placed below said column. become.

To make such connections across columns, it is also possible to use cells that are not powered, and these
The electrode has connection points at the top and bottom of the cell.
31 In fact, due to the fact that when no current is supplied to the cell, the connection points are completely isolated from each other, in this case the two gates of the cell as well as the three north or drain It is also possible to use In this case, it is also possible to pass the gold wire from the second aluminum layer vertically above the non-supplied cells. Despite that.

This possibility can be avoided. If the connection is passed above the output point, the difference in thickness will of course be larger, and due to the fact that the aluminum layer will be easier to fracture at these locations, The same idea applies to the possibility that there is a connection 1 above the output point of the cell in the case of supply 1.

By comparing the two cells contained within the dashed rectangle 411 with the electrically corresponding cells of FIG. provides significantly more possibilities for interconnection than identical pairs of elementary cells corresponding to the known cells of . The possibility of the cell in FIG. 1 is once again asserted.

Therefore, in order to embody a library of standard circuits containing much more logic functions than the simple NAND and NOR gates of low diffusion circuits already known in the prior art, these interconnections are used. becomes possible to use. These standard circuits offer an advantage in that they have sizes that are multiples of each other and can be accommodated within pairs of elementary cell columns.

If, under these Articles 1'+, the possibility of making interconnections between the aforementioned columns is further exploited, then the arrangement methods which have already proven their effectiveness in standard circuits may be used. and procedural determination methods may be utilized for diffused circuit structures. exchange'1
=-f, using standard circuits corresponding to the desired logic circuits of the library and placed in the columns, a routing program is used to define the interconnections between these columns. .

The method of fabricating integrated circuits of the present invention has the result that it not only provides the advantage of standardizing low dispersion circuits, but also provides the advantage of being useful both in the construction and utilization of the substrate surface of standard circuits. , these routing programs are 10
It can be seen that 0chi can be valid.

As with standard circuits, libraries can be extremely important. Next, as a specific example, a relatively simple two-person N
The structure of the AND~ type circuit and the more complex circuit of the static D-7 Ritz-Front type will be explained.

FIG. 5 shows a schematic circuit diagram of a two-man powered NAND-gate.

This circuit includes two p-type Mos transistors 501 and 502, which have a source VDD
are also fed in parallel. These two transistors in parallel are composed of two n-type MO8) transistors 503 and 50.
Connected in series with 4. This second transistor is connected to the supply source SS. One input gl is connected in parallel to the gates of transistors 501 and 503, and the other input E2 is connected in parallel to the gates of transistors 502 and 504. The output S of the gate is taken from a common connection between the drains of transistors 501 and 502 and the source of transistor 503.

This extremely simple circuit consists of two circuits of the type shown in FIG.
formed by basic cells. In order to more fully understand the structural arrangement, this circuit will now be described in more detail.

This recirculation is carried out in cells 60 of 2 f1M of p-type and n-type.
1 and 602, respectively, form parts of two consecutive columns, one part being placed above the other part. In FIG. 6, these cells are shown bare. In accordance with normal practice,
Holes formed in the final oxide layer that help protect the circuit and provide access to the drain, source and gate of the transistor are indicated by shaded squares.

In FIG. 7, a system of aluminum connections is shown.

This connection allows the construction of the desired two-person NAND-gate from the cell. In this figure, horizontal connections such as connections VDD and VSS corresponding to the two supply buses are shown within a frame 701 delimiting the area of the two cells. These feed buses are obtained from the initial aluminum evaporation on the oxide layer. The function of this oxide layer is to protect the diffused circuitry. Vertical connections such as El and E2 provided for the two inputs and S for the output are obtained as a result of depositing a second aluminum layer on the intermediate insulating oxide layer. This insulating oxide layer is deposited after the initial deposition of aluminum.

In order to provide connections between the vertical connections of the second layer and a predetermined number of access points for sources, drains and gates, as well as between the horizontal and vertical connections corresponding to these two layers, intersections are An opening is formed in the intermediate oxide layer that is located or located over the access point for the transistor. To distinguish these openings from the holes giving access to the transistor poles, these openings are shown as diamonds in the figures. Both of these indications are used only as symbols.

Figure 7 is easier to read but harder to understand than the combination of Figures 6 and 7. By combining Figures 6 and 7, we can obtain a complete i-search between the gates already explained. For these reasons, FIG. 8 is shown in a relationship where FIGS. 6 and 7 are combined. Therefore, this figure shows a two-person NAND-gate constructed by the method of the present invention.
Fully display f1' ill.

Figure 9 (%5 2-person N0R-gates 901-90
FIG. 5 is a logic diagram of a static single-type flip-flop made from 5 and 3 human-powered N0R-gates. The flip-flop operates on two input signals, a data signal and a time signal H, and provides two complementary output signals Q and Q.

The electrical circuit diagram of one of the 2-manual powered N0R-gates is shown in FIG. This diagram is completely complementary to the one-way diagram of FIG. 5 which represents a NAND-gate. In this figure, 2
p-type transistors 907 and 908 are shown.

These transistors are fed in series from the source VDD and connected in parallel to the n-type transistors 909 and 910 connected in parallel. 61
Transistor 1 is connected p2 to the supply source vSS.

One input signal gl is applied in parallel to the gates of transistors 907 and 909, and the other signal E2 is applied in parallel to the gates of transistors 908 and 910. The gate is
3 p-type transistors in series and 3 n-type transistors in parallel p)
The gate of the p-type transistor is connected to the gate of the n-type transistor and is intended to receive one of the three input signals.

By adopting the drawing conventions described at the beginning for the 2-human NAND gate,
The layout diagram, which is decomposed into diagrams 11a, 11h, and 331ic, and combined as shown in FIG. to be fully displayed. Figure 11nl shows part 11a and Figure 11b shows part 1.
l b'? , 11c show portions 11c, respectively.

This figure utilizes seven pairs of consecutive p-type and n-type elementary cells forming part of a column of consecutive p-type and n-type σ) 2 %q. Gogate 902 for the first pair
configure and accept the signal. The second pair is gate 90
1. The third pair constitutes gate 903 and receives the signal H. Gate 906 with three inputs is
a fourth pair and a tenth in the fifth pair two transistors of p-type and one type. The sixth pair constitutes gate 905. The seventh pair is gate 904
and sends out signals Q and Q.

The two transistors in the fifth pair that were not fixed were used to implement the inverter.

This inverter receives signal E and sends out signal I.

It is virtually always useful to provide inverters in logic circuits, and it is preferable to mount these inverters directly within the library circuits to ensure effective isolation between programs. These programs are useful for wiring circuits from inverters, and inverters are useful for wiring circuits.

A complete free lag-flop wiring system is contained within the rectangle defined by the seven pairs of elementary cells, thus providing inter-circuit interconnection.

It easily turns out to leave completely free external space. Furthermore, six vertical connections are provided between the basic cells of the flip-flop for the same circuitry wiring system.

It can therefore be concluded that the method of the present invention effectively achieves an integration between diffused circuit technology and standard circuit technology.

In this way, the standard circuits recalled from the library can be distributed on the diffused substrate at will, with wiring between the circuits being done as in the standard circuits.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a diagram showing a basic cell of the prior art, Fig. 2 is a diagram showing a low diffusion circuit according to the prior art, and Fig. 3 is a diagram showing a logic gate. FIG. 4 shows six adjacent basic cells according to the invention, FIG. 5 shows a NAND-gate, and FIG. 6 shows the cells of FIG. FIG. 7 is a diagram showing two low-diffusion basic cells according to the invention for constructing the gate of FIG. 5; FIG. 7 shows a connection with the cell shown in FIG. 6 for constructing the gate of FIG. 8 are general layout diagrams according to the present invention, illustrating the gate of FIG. 5, FIG. 9 is a schematic diagram of a D-type flip-flop, and FIG. The circuit diagrams of the N0R-gate used in the layout diagram of FIG. , 12th
The figure is an explanatory diagram showing a combination of FIG. 11a, FIG. 11b, and FIG. 1ie. 201...Substrate, 202.205...Column of basic cells, 203.204...Space. Fig, 8 J ■ ■ ■ oJ w w

Claims (1)

[Claims] (Claim 1 of the claim 1, which has 11 rows of basic cells, and the rows of basic cells are successively connected to each other to form a substrate machine. Integrated circuit. (3) A patent claim characterized in that each elementary cell includes two MOS transistors connected in series via a common drain pole, each having a separate gate. Claim 3 Vr- characterized in that the gate of the second connection point is arranged in a straight line with the first point so as to provide at least three connection lines.
Integrated circuit as described. (5) The space between the columns and the space between basic cells. 5. An integrated circuit as claimed in claim 4, characterized in that it does not allow the connection line to pass through. (6) The space between the rows and the space between the basic cells further allows the passage of a longitudinal connection line and a lateral connection line, respectively. integrated circuit. (7) A method of interconnecting a low dispersion integrated circuit comprising nine columns of elementary cells following each other in series, the surface of at least one column of elementary cells supplying power to the column of elementary cells. The method for interconnecting integrated circuits is used to pass interconnections between cells. (8) The surface of at least one basic cell is used for passing lateral connections without supplying power to the basic cell. Method. (9) A standard circuit library consisting of two consecutive columns of n-type and p-type basic cells is used, and the two columns have a predetermined size specific to the standard circuit. A claim characterized in that the connections between basic cells in the standard circuit for determining the logical function of the standard circuit are contained within a rectangle that defines the range of the standard circuit. The method described in item 8. 01 For integrated circuits without pre-diffusion of standard cells,
10. A method according to claim 9, characterized in that known placement and routing methods are used.