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JPS58203563A - System for controlling assignment of priority of right - Google Patents

System for controlling assignment of priority of right

Info

Publication number
JPS58203563A
JPS58203563A JP8687582A JP8687582A JPS58203563A JP S58203563 A JPS58203563 A JP S58203563A JP 8687582 A JP8687582 A JP 8687582A JP 8687582 A JP8687582 A JP 8687582A JP S58203563 A JPS58203563 A JP S58203563A
Authority
JP
Japan
Prior art keywords
request
resource
circuit
order allocation
permission signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8687582A
Other languages
Japanese (ja)
Inventor
Kenji Hasegawa
賢治 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8687582A priority Critical patent/JPS58203563A/en
Publication of JPS58203563A publication Critical patent/JPS58203563A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE:To assign one resource to each requesting source uniformly in a system using the resource by plural requesting sources by providing the system with a right priority assigning circuit to process data. CONSTITUTION:The CPUs 2-5 can use a memory circuit 1 in common through a data bus 7. Memory utilization requesting signal lines 12-15 and memory utilization permission signal lines 8-11 are connected between respective CPUs and a rihgt priority circuit 6. When the CPUs 2, 3 send requests for using the memory 1 to the circuit 6, the circuit 6 accepts the CPU2 using the memory 1 with priority out of the CPUs 2, 3 in accordance with least recently used algorithm and sends a permission signal through a permission signal line 8. Receiving the permission signal, the CPU2 can used the bus 7.

Description

【発明の詳細な説明】 発明の分野 本発明は、メモリ回路のような1個のリソース利用数の
マイクロコンピュータのような要求元が共用するシステ
ムの権利順序割当制御方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a rights order allocation control method for a system such as a memory circuit that is shared by a requestor such as a microcomputer that uses one resource.

従来技術 1個のリソースを複数の要求元が共用するシステムにお
いて、各要求元から発生される要求信号が重複する場合
、その利用順序を定めることによってリソースの均等な
利用が計られることが必要となる。従来では、リソース
に要求信号が到来すると、予め物理的配置等によって定
められた固定的優先順位に従った要求元に対して応答す
るようにしていた。
Prior Art In a system in which one resource is shared by multiple requesters, if the request signals generated from each requester overlap, it is necessary to ensure equal use of the resource by determining the order of use. Become. Conventionally, when a request signal arrives at a resource, a response is made to the request source according to a fixed priority order determined in advance based on physical arrangement or the like.

従来技術の問題点 従来の方式では、優先順位が一定であるため、低い優先
順位にある要求元は常に長時間待九されることになり、
不都合な問題を引き起す原因となっていた。
Problems with the conventional technology In the conventional method, since the priority order is constant, request sources with lower priority are always kept waiting for a long time.
This caused an inconvenient problem.

発明の目的 本発明の目的は、権利順序割当回路を設けることによっ
て、各要求元に対してリソースの均等な利用を計れるよ
うにすることにある。
OBJECTS OF THE INVENTION It is an object of the present invention to provide a rights order allocation circuit to ensure equal use of resources for each request source.

発明の要点 本発明の権利till序割当方式によれば、リソースと
、このリソースを共用するように配置された複数の要求
元と、これら複数の要求元による前記リソース利用が競
合する場合に権利+1ii1序の割当制御を行う権利順
序割当回路と、前記要求元のそれぞれと前記権利順序割
当回路の間に設けられ前記要求元が前記リソースを利用
する時セットされる要求信号線と、前記要求元のそれぞ
れと前記権利順序割当回路の間に設けられ前記権利II
序割当回路が前記要求元からの要求を許可する時にセッ
トされる許可信号線とを備えている。そして、前記要求
元からの前記リソース利用が唯一の時には前記権利順序
割当回路が当該唯一の要求元に対してのみ所定の前記許
可(8号線をセットし、また前記要求元からのリソース
利用要求が複数個競合する時には前記権利順序割当回路
が前記複数の要求元の中から最先の1つの要求元に対し
てのみ許可信号線をセットすることを特徴としている。
Summary of the Invention According to the rights till order allocation method of the present invention, when there is a conflict between a resource, a plurality of request sources arranged to share this resource, and the use of the resource by these plural request sources, the right +1ii1 a right order allocation circuit that performs order allocation control; a request signal line provided between each of the request sources and the right order allocation circuit and set when the request source uses the resource; and a request signal line that is set when the request source uses the resource; the right II and the right order allocation circuit;
and a permission signal line that is set when the order allocation circuit grants a request from the request source. When the resource usage from the request source is the only one, the rights order allocation circuit grants the predetermined permission (line 8) only to the unique request source, and when the resource usage request from the request source is The present invention is characterized in that when a plurality of request sources conflict, the right order allocation circuit sets a permission signal line only for the first request source from among the plurality of request sources.

発明の実施例 第1図は本発明の一実施例を示すブロック回路図である
。lはリソースとしてのメモリ回路で、2〜5はいずれ
も要求元を示すマイクロコンピュータあるいは中央情報
処理装置(以下CPUと称する)である。CPU2〜5
はリソース1を共用で睡る関係にあり、両者間は情報を
伝達させるデータバス7で結はれている。6は権利順序
割当回路で、CPU2〜5のそれぞれとの間に2種類の
信号線をそれぞれ持つ。その一方8〜11は権利順序割
当回路6がC1’LI2〜5のいずれかにメモリ1の利
用を許可する信号を送出する許可信号線である。また他
方12〜15は、CPU2〜5がメモリ1を利用したい
ときに、回路6に要求したい旨の信号を送るようセット
される要求信号線である。
Embodiment of the Invention FIG. 1 is a block circuit diagram showing an embodiment of the invention. 1 is a memory circuit as a resource, and 2 to 5 are microcomputers or central information processing units (hereinafter referred to as CPUs) indicating request sources. CPU2~5
are in a relationship where they share the resource 1, and are connected by a data bus 7 for transmitting information. Reference numeral 6 denotes a rights order allocation circuit, which has two types of signal lines between each of the CPUs 2 to 5. On the other hand, 8 to 11 are permission signal lines through which the right order allocation circuit 6 sends a signal for permission to use the memory 1 to any one of C1'LIs 2 to 5. On the other hand, 12 to 15 are request signal lines that are set to send a signal to the circuit 6 when the CPUs 2 to 5 want to use the memory 1.

第1図において、CPU2がメモリ1をアクセスし、そ
の後CPU3,4.5がこの順序でアク路6に送出する
と5回路6はLRU (LeloRecently  
Used )アルゴリズムに従って出力を出す。すなわ
ち、メモリ1を利用する要求があったにPU2,3の中
から最先にメモリを利用したCPひ、ここではCPU2
からの要求を受は付け、許可信号l518によって許可
信号を送出する。
In FIG. 1, when the CPU 2 accesses the memory 1, and then the CPUs 3 and 4.5 send data to the access path 6 in this order, the 5th circuit 6 becomes LRU (LeloRecently).
Used) Output according to the algorithm. In other words, when there was a request to use memory 1, the CPU that used the memory first from PU2 and PU3, in this case, CPU2.
It accepts the request from and sends out a permission signal using permission signal l518.

これを受信したCPO2は、データバス7を使用するこ
とが可能となる。
The CPO 2 that receives this becomes able to use the data bus 7.

第2図は、権利順序割当回路6を更に詳しく示すブロッ
ク回路図である0図中、16はI、RUアルゴリズム回
路で、イネーブル端子がセットされると起動し、入力端
子A、B、C,Dの中からセットされている端子で最先
に出力されたもの1個だけを出力端子にセットするもの
である。上記例では、A端子がにあるいは8に結び付く
ことになる。
FIG. 2 is a block circuit diagram showing the rights order allocation circuit 6 in more detail. In FIG. 2, 16 is an I, RU algorithm circuit which is activated when the enable terminal is set, Among the terminals set in D, only the one that is output first is set as the output terminal. In the above example, the A terminal would be tied to or 8.

発明の効果 本発明は、以上説明したように、要求元である複数のC
PUがリソースであるメモリを共用する関係にある場合
に、要求元が競合してリソースを利用するとき、LR,
Uアルゴリズムによって最先の要求元に対して優先権を
与えることができ、各要求元に対して特定されることな
く均等な優先利用機会を与えることができるものである
Effects of the Invention As explained above, the present invention provides
When PUs share memory, which is a resource, when request sources compete to use the resource, LR,
By using the U algorithm, priority can be given to the earliest requester, and equal priority usage opportunities can be given to each requester without being specified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図eま本発明の一実施例を示すブロック回路図、第
2図は第1図の回路の要部を示すブロック回路図である
。 1・・・・・・リソースであ4メモリ回路、2〜5・・
川・要求元であるCPU、5・・・・・・権利順序割当
回路、7・・・・・・データバス、8〜11・・・・・
・許可信号線、12〜15・・・・・・要求信号線、1
6・・・・・・I4Uアルゴリズム回路。 代理人 弁理士  栗 1)春 雄
FIG. 1e is a block circuit diagram showing one embodiment of the present invention, and FIG. 2 is a block circuit diagram showing essential parts of the circuit of FIG. 1. 1...4 memory circuits as resources, 2 to 5...
River/CPU that is the request source, 5... Rights order allocation circuit, 7... Data bus, 8 to 11...
・Permission signal line, 12 to 15...Request signal line, 1
6...I4U algorithm circuit. Agent Patent Attorney Kuri 1) Yu Haru

Claims (1)

【特許請求の範囲】[Claims] リソース1と、このリソースを共用するように配置され
た複数の要求元2〜5と、これら複数の要求元による前
記リソース利用が競合する場合に権利順序の割当制御を
行う権利順序割当回路6と、前記要求元のそれぞれと前
記権利順序割当回路の間に設けられ前記要求元が前記リ
ソースを利用する時セットされる要求信号線12〜15
と、前記要求元のそれぞれと前記権利順序割当回路の間
に設けられ前記権利順序割当回路が前記要求元からの要
求を許可する時にセットされる許可信号線8〜11とを
備え、前記要求元からの前記リソース利用が唯一の時に
は前記権利順序割当回路が当該唯一の要求元に対しての
み所定の前記許可信号線をセットし、前記要求元からの
リソース利用簀求が複数個競合する時には前記権利順序
割当回路が前記複数の要求元の中から最先の1つの要求
元に対してのみ所定の前記許可信号線をセットすること
を%鎗とする権利順序割当制御方式。
A resource 1, a plurality of request sources 2 to 5 arranged to share this resource, and a rights order allocation circuit 6 that performs rights order allocation control when there is a conflict in the use of the resource by the plurality of request sources. , request signal lines 12 to 15 provided between each of the request sources and the right order allocation circuit and set when the request source uses the resource.
and permission signal lines 8 to 11 provided between each of the request sources and the right order allocation circuit and set when the right order allocation circuit grants a request from the request source; When the resource usage from the request source is unique, the rights order allocation circuit sets the predetermined permission signal line only for the unique request source, and when there is a conflict of resource utilization requests from the request source, A rights order allocation control method in which a rights order allocation circuit sets a predetermined permission signal line only for the first one of the plurality of request sources.
JP8687582A 1982-05-22 1982-05-22 System for controlling assignment of priority of right Pending JPS58203563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8687582A JPS58203563A (en) 1982-05-22 1982-05-22 System for controlling assignment of priority of right

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8687582A JPS58203563A (en) 1982-05-22 1982-05-22 System for controlling assignment of priority of right

Publications (1)

Publication Number Publication Date
JPS58203563A true JPS58203563A (en) 1983-11-28

Family

ID=13898996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8687582A Pending JPS58203563A (en) 1982-05-22 1982-05-22 System for controlling assignment of priority of right

Country Status (1)

Country Link
JP (1) JPS58203563A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859614B1 (en) 1996-06-24 2005-02-22 Samsung Electronics Co., Ltd. Apparatus and method for controlling priority order of access to memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150054A (en) * 1979-05-11 1980-11-21 Nissin Electric Co Ltd Multi-computer system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150054A (en) * 1979-05-11 1980-11-21 Nissin Electric Co Ltd Multi-computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859614B1 (en) 1996-06-24 2005-02-22 Samsung Electronics Co., Ltd. Apparatus and method for controlling priority order of access to memory

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