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JPS5820052A - Abnormal traffic ontrolling system - Google Patents

Abnormal traffic ontrolling system

Info

Publication number
JPS5820052A
JPS5820052A JP11815081A JP11815081A JPS5820052A JP S5820052 A JPS5820052 A JP S5820052A JP 11815081 A JP11815081 A JP 11815081A JP 11815081 A JP11815081 A JP 11815081A JP S5820052 A JPS5820052 A JP S5820052A
Authority
JP
Japan
Prior art keywords
processor
control
processors
congestion state
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11815081A
Other languages
Japanese (ja)
Inventor
Kazunari Haruta
一成 春田
Mamoru Sugawara
菅原 護
Hisashi Takayama
高山 壽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11815081A priority Critical patent/JPS5820052A/en
Publication of JPS5820052A publication Critical patent/JPS5820052A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/22Arrangements for supervision, monitoring or testing
    • H04M3/36Statistical metering, e.g. recording occasions when traffic exceeds capacity of trunks
    • H04M3/365Load metering of control unit

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To quickly retire from a congestion state of processors for an electronic switchboard of multiprocessor system, by controlling a control load to the processor in a congestion state for each processor under control. CONSTITUTION:The function of an electronic switchboard of multiprocessor system is shared by plural processors LPR, CPR and MPR. A means HT is provided to the switchboard to monitor an abnormal congestion state for the above- mentioned processors and then transmits the control command of the control load to these processors which are in the ongestion state via an exclusive command line L2 reaching each processor. As a result, each processor under control command can control the control load to the processor in the congestion state. In such way, the processor can quickly be retired from the congestion state.

Description

【発明の詳細な説明】 事理91iは異常トラヒック規制方式、41KII数の
プロセッサに機能を分担−TM姥るマルチプロ七ツナ方
式電子交換機における異常トラとツク規制方式に関す。
DETAILED DESCRIPTION OF THE INVENTION Fact 91i relates to an abnormal traffic regulation system, an abnormal traffic regulation system in a multi-pro seven-tuna type electronic switching system including TM-TM, in which functions are shared among 41KII processors.

従来ある電子交換機におtn′Cは、収容端末の監視制
御、交換処IIOためO呼情報管理制御、画線電子交換
機全体の監視運用制御等の諸機#!は、総べて単一〇1
0セッナに具備されてい良OこO種エニプロセッサ方式
電子交換機においては、異常負荷によ)発生する輻穣状
簡の検出およびその^當負荷O規制は、総べて前記単一
プロセッサ内で46!1可能であった。
In conventional electronic exchanges, tn'C has various functions such as supervisory control of accommodating terminals, O-call information management control for exchange IIO, and supervisory operation control of the entire electronic exchange. are all single 〇1
In the any-processor type electronic exchange equipped in the zero processor, the detection of congestion signals caused by abnormal loads and the regulation of the load are all carried out within the single processor. 46!1 was possible.

一方近都マイクロプロセッサ等の半導体技術の進歩等に
立脚して、電子交換機の前記論制御機能taaoプロセ
ッサに分担させるマルテプロセツt7j式が注[1され
つ\ある。この穏マルチプセセッを方式電子交換機にお
いであるプ關(ツサに輻−状態が発生した場合に、前記
ユニプロセッサ方式におけるが如く輻−状態にあるプロ
セッサ自体が異常負荷の規制を実施すると、該プロセッ
サに負荷を加える他のプロセッサ並びに誼プロセッサに
無効地層を行わせること\なるO鷹た複数のプロセッサ
相互が他Oプpセツナの輻輪状態な誼プロセッナ椙亙関
に設けられている通信路を用いて監視を賦与る場合には
、各プロセッサが関連する複数のプーセッナO輻−状m
を職別する機能な^偏する必要があシ、更に前記1wx
*ツナ間過信路に障害が発生した場合には輻−11視機
能が麻痺すること\な)、迅速適確に輻輪状態から離属
する仁とが出来なくなる。
On the other hand, based on advances in semiconductor technology such as microprocessors, there is a multiprocessor T7J system in which the control function of an electronic exchange is shared by a TAAO processor. If a congestion state occurs in a certain processor in the electronic switching system, if the processor in the congestion state itself regulates the abnormal load, as in the uniprocessor system, the processor In order to make other processors that add a load as well as other processors to perform an invalid layer, multiple processors can use communication channels provided in a state of communication between other processors. If each processor provides monitoring by
It is necessary to bias the function by job, and furthermore, the above 1wx
*If a disorder occurs in the inter-tuna hypersensitivity path, the convergence-11 visual function will be paralyzed (), making it impossible to quickly and accurately separate from the convergence state.

本発明の目的は、前述O加電従来ある異常トラヒック規
制方式の欠点を除去し、轟該電子交換機のプロセッサに
無効処理を行わせること無<、 またm誼電子交換機の
具備するプロセッサ間通信路に障害が発生した場合にも
迅速適確に輻輪状態から離属可能な手段を実現する仁と
Kある。
It is an object of the present invention to eliminate the drawbacks of the conventional abnormal traffic control system using the above-mentioned power supply, to eliminate the need to cause the processor of the electronic exchange to perform invalid processing, and to eliminate the need for the inter-processor communication path provided in the electronic exchange. There are two ways to realize a means to quickly and accurately separate from a state of convergence even when a failure occurs.

この目的社、複数oyvx*ツナに機能を分担させるマ
ルチプロセッサ方式電子交換機において、前記各プロセ
ッサの異常輻−状態を監視し、輻−状態となったプロセ
ッサに対する制御負荷の規制指令を前記各グ四セッナK
N!為専用の指令線を介して伝達する手段を設け、腋嘱
制指令を受領した各プロセッサは前記輻−状態となった
プロセッサに対する制御負荷を規制することによル達成
されるO 以下本発明の一実施例を図によ)説明する。図Wは事理
−の一実施例による異常トラヒック規制方式を示す図で
ある。図に示されるマルチプロセッサ方式電子交換機は
三−類の1關セツサ、即ち端末監視制御プロセッtLP
R,呼情報管場制御グロ七ツナCP几およびシステム監
視運用制御グロセッtMPR&使用する0端末監視制御
グロセツナLPRはライン回路L Cs  ) 5 y
り回路TRKに収容される加入者線、中継線等の端末S
UBの発呼検出、状膳監視、着信制御を行い、呼情報管
層制御プロセッサCPRは端末監視制御グロセッtLP
Rあるいは(I!IO呼情報管履制管層ロセッサCPR
から伝遁畜れる呼情報に基づき対応するネットワークN
W上KPMを設定し、システム監視運用制御グロセッナ
MPRは総べて0収審端末SUBの空塞状態の管層等の
画線電子交換機全体の運用管11に轟る・端末監視制御
プUセッtLPRと呼情報管1制御ブーセツサCPRと
の間の通信は、ライン回路LC壜えはトランク回路TR
KとネットワークNWとを結ぶハイウェイHWに含すれ
る図示されぬ信号通信路にょp行われ、また呼情報管理
制御プロセッサCPRIIXM)よび呼情報管理制御プ
ロセッサCPRとシステム監視連用制御プ四セッナMP
Rとの間の過儒轄、過信パスCBKより行われる。また
前1le−車監視制御プロ七ツサLPR,呼情報管理制
御プロセッナCPB、システム監視運用制御プロセッナ
MPRの各々はそれぞれ輻−検出部HTを具備する◎該
輻−検出部HTはユニプロセッサ方式電子交換機と同様
の公知の方法で、各プロセッサO無負荷時間を計測して
使用率を算定し、該使用率が定められえ規準値を越える
と該プロセッサが輻−状態に在ると見做す。更Kall
1mマルチプロセッを方式電子交換機は前記各種プロセ
ッサLPR,CPRおよび組1とは独立に輻輪状態監視
装置8が設けられ、前記各種プロセッサLPR%CPR
およびMPRO各々との間を前記ハイウェイMWおよび
通信パスCBと独立の通知l5L1.および指令線L!
によ)接続されている・輻輪状態監視装置8は通知−L
l會介して各プロセッサLPR,CPRおよびMPRO
輻−状態を定常的に監視しているの今何れかの10セツ
ナ(例えば呼情報管層制御プロセッサCPR,v一つ)
0111+1検出部HTが輻−状態の発生を検出すると
、輻−状態am鋏装8に通知線Llを介して輻−状態情
報を伝達する◎腋輻−状態情報を受領した輻―状m監視
装置8Fi内蔵する図示されぬグロセッナ関逼−から、
輻−状態となった呼情報管理制御プロセッサCPRK呼
情報等の制御負荷を加える端末監視制御1m竜ツナLP
’R,他の呼情報管理制御プロセッサCPR等を抽出し
、抽出しえ各プロセッサに至る指令線L2に対し、輻棲
状態に在る呼情報管1制御ブーセッサCPHに対する制
御負荷の規制指令を送出する◎該規制指令を受領し九各
グーセッナは以後輻輪状態に在る呼情報管理制御プロセ
ッサCPRに対し制御負荷を加えることt中止する。例
えば端末監視制御プロセッサLPRは管理下の端末8U
BからO発呼は検出せず、従つて発呼に関する呼情報を
輻−状態に在る呼情報管層制御プロ七ツナCPBK伝達
することは−い・七〇1114%−−状態に在る呼情報
管理制御プ四セ、tcphの制御負荷は処理の進行に伴
い減少し、輻輪状態から速やかに離脱社来る。
This purpose company, in a multiprocessor type electronic switching system in which functions are shared among multiple oyvx Senna K
N! This is achieved by providing means for transmitting the command through a dedicated command line, and each processor that receives the armpit control command restricts the control load on the processor in the congestion state. An example will be explained with reference to the drawings. FIG. W is a diagram showing an abnormal traffic regulation method according to an embodiment of the present invention. The multiprocessor type electronic switching system shown in the figure is a type 3 type 1 setter, namely, a terminal monitoring control processor tLP.
R, call information management center control system control system 7 Tuna CP 几 and system monitoring operation control system tMPR & 0 terminal monitoring and control system LPR is line circuit L Cs ) 5 y
Terminals S such as subscriber lines and trunk lines accommodated in the circuit TRK
The call information management layer control processor CPR performs UB call detection, status monitoring, and call reception control.
R or (I!IO call information control layer processor CPR
The corresponding network N based on the call information transmitted from
Setting the KPM on W, the system monitoring and operation control Grossena MPR is all zero. Communication between the tLPR and the call information tube 1 control booth CPR is carried out by the line circuit LC and the trunk circuit TR.
A signal communication path (not shown) included in the highway HW that connects K and the network NW is carried out, and a call information management control processor CPRIIXM), a call information management control processor CPR, and a system monitoring and communication control processor MP are carried out.
This is done through the over-confucian control and over-confidence path CBK between R and R. In addition, each of the front 1le-car monitoring control processor LPR, call information management control processor CPB, and system monitoring and operation control processor MPR is equipped with a congestion detection section HT.◎The congestion detection section HT is a uniprocessor type electronic switching system. Using a known method similar to that described above, the unloaded time of each processor O is measured to calculate the usage rate, and when the usage rate exceeds a predetermined standard value, the processor is considered to be in a busy state. Further Call
The 1m multi-processor type electronic exchange is provided with a ring status monitoring device 8 independent of the various processors LPR, CPR and group 1, and the various processors LPR%CPR
and MPRO, the highway MW and the communication path CB and independent notification l5L1. and command line L!
) Connected/convergence status monitoring device 8 is notified -L
Each processor LPR, CPR and MPRO
Any of the 10 sets that are constantly monitoring the congestion status (for example, one call information management layer control processor CPR, v)
When the 0111+1 detection unit HT detects the occurrence of the congestion condition, it transmits the congestion condition information to the congestion condition am scissors 8 via the notification line Ll. From the unillustrated Grossenna interface with 8Fi built-in,
Call information management control processor CPRK in a congestion state Terminal monitoring control 1m Ryu Tuna LP that adds control load such as call information
'R, extracts other call information management control processors CPR, etc., and sends a control load regulation command to the call information pipe 1 control processor CPH, which is in a congestion state, to the command line L2 leading to each extracted processor. After receiving the regulation command, each controller stops applying a control load to the call information management control processor CPR which is in a congested state. For example, the terminal monitoring control processor LPR is the terminal 8U under management.
B to O call origination is not detected, therefore, it is not possible to transmit the call information regarding the call origination to the call information management layer control professional 7Tuna CPBK which is in the congestion state. The control load of the call information management control process and TCPH decreases as the processing progresses, and the congested state quickly breaks away.

以上のl!−から明らかな如く、本爽施例によれば尚鋏
マルチプ四セッを方式電子交換機Kt箇れ為任意のグb
セッサLPR,JO’P6猿8MII冗に抛生す為魯鱗
状1IIK対−輻−状態監視装置8が最4規制に有効な
関連プロセッナに規制指令を与えるので、当該電子交換
機に含まれ為プロセッサの無効処mFi肪止される・箇
た輻輸状態監視装置Sと各プロセラtLPR,CPRお
よびMPRとOMK授受される輻−状態情報および規制
指令は専用の通知@L1および指令線L2を介して伝達
されるので、当該電子交換機が交換処理に使用するハイ
ク、イHWあるiは通償パスCBK障害が発生して4、
何等支障無く規制が実施出来る・ なお、lIlはあく迄本*@〇−與施例に過ぎず、例え
け輻輪状態O発生する1w−kyすは呼情報管理制御プ
ロセッサCPRKII定することは無く、他の任意のプ
―セッtall生し1#−場合にも本発明の効果は変ら
ない・壇た事理aCt対象となるマルチ1**yす方式
電子交換機0@成に、図示嘔れるものに限定されること
はなく、他に幾多OgR形が考慮されるが、何れO場合
に4h本発明の効果は変らない。
More than that! - As is clear from this example, the four sets of scissors multipliers are connected to the electronic switching system Kt, so any group b
The processor LPR, JO'P6 is included in the electronic exchange and the processor is included in the electronic exchange, since the control device 8 gives control commands to the associated processors valid for up to 4 controls. Invalid processing mFi is stopped and the flow state monitoring device S and each processor tLPR, CPR, and MPR and OMK exchange state information and regulation commands are transmitted via dedicated notification @L1 and command line L2. Therefore, the electronic exchange used for exchange processing, i HW, has a compensation path CBK failure and 4,
Regulations can be implemented without any problems. Note that IIl is just an example, and for example, the 1w-ky that occurs in the convergence state O is not determined by the call information management control processor CPRKII. , the effect of the present invention does not change even in the case of any other set of computers. The present invention is not limited to 4h, and many other OgR types may be considered, but the effect of the present invention remains the same in any case.

以上、本発明によれば、!ルテプロセッ賃方式電子交換
機に含まれる任意のプロセッサに輻−状IIlが発生し
た場合にも、無効#!&珊を伴わず、また当該電子交換
機の有すゐ通信路に生ずる障害に影響されること無く制
御負荷の規制が可能となり、当該プロセッサを輻−状態
から速やかに離脱壜せることが出来る。
As described above, according to the present invention! If a congestion condition occurs in any processor included in the electronic switching system, invalid #! It becomes possible to regulate the control load without causing disturbances and without being affected by disturbances occurring in the communication path of the electronic exchange, and it is possible to quickly remove the processor from a congested state.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の一奥施例による異常トラヒック規制方式
を示す図である0 図において、SUBは端末、LCはライン回路、TRK
 Fl;t トjンク回路、LPRは端末監視制@1四
セッサ、HWはハイウメイ、NWはネットワーク、CP
Rは呼情報管理制御プ■セッナ、CBt1通信パス、M
PRはシステム監視運用制御プロセッサ、I(Tは輻棲
検出部、8は輻魯状態監視装置、LIF1通知着、L2
は指令線、を示す。
The drawing is a diagram showing an abnormal traffic regulation system according to the most advanced embodiment of the present invention. In the drawing, SUB is a terminal, LC is a line circuit, and TRK
Fl;t Tonk circuit, LPR is terminal monitoring system @14 processors, HW is high power, NW is network, CP
R is call information management control path, CBt1 communication path, M
PR is the system monitoring operation control processor, I (T is the congestion detection unit, 8 is the congestion status monitoring device, LIF1 notification arrival, L2
indicates a command line.

Claims (1)

【特許請求の範囲】[Claims] 複数Oプロセラ1#″に機能を分!lさせるマルチプロ
セラを方式電子交換機KsIPいて、前記各プaセッt
O異常輻−状態を監視し、輻−状態とな−)九プ霞七ツ
サに対する制御負荷の規制指令を前記各プロセッサに至
る専用O指令−を介して伝達する手段を設け、該規制指
令を受領した各プロセッサは前1elllll状態と1
につ喪プロセνすに対する制御負荷を規制することを善
黴とする異常トラヒック規制方式@
A multi-processor electronic exchange system KsIP has functions divided into multiple O processors 1#'', and each of the above-mentioned processors
A means is provided for monitoring an abnormal congestion state and transmitting a control load regulation command for the nine-pull Kasumi Nanatsusa via a dedicated O command to each of the processors, and transmitting the regulation command. Each received processor is in the previous 1ellllll state and 1
Abnormal traffic regulation method whose purpose is to regulate the control load on the mourning process
JP11815081A 1981-07-28 1981-07-28 Abnormal traffic ontrolling system Pending JPS5820052A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11815081A JPS5820052A (en) 1981-07-28 1981-07-28 Abnormal traffic ontrolling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11815081A JPS5820052A (en) 1981-07-28 1981-07-28 Abnormal traffic ontrolling system

Publications (1)

Publication Number Publication Date
JPS5820052A true JPS5820052A (en) 1983-02-05

Family

ID=14729319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11815081A Pending JPS5820052A (en) 1981-07-28 1981-07-28 Abnormal traffic ontrolling system

Country Status (1)

Country Link
JP (1) JPS5820052A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0121865A2 (en) * 1983-03-31 1984-10-17 Siemens Aktiengesellschaft Circuit arrangement for telecommunication installations, especially for telephone exchanges comprising information processors and devices for overload control
JPS61128696A (en) * 1984-11-28 1986-06-16 Hitachi Ltd Control system of dispersion control type electronic exchanger
JPS6211355A (en) * 1985-07-09 1987-01-20 Fujitsu Ltd Congestion control system
JPH01318343A (en) * 1988-06-17 1989-12-22 Fujitsu Ltd Outgoing call restriction system
JPH0577508A (en) * 1991-09-21 1993-03-30 Sumitomo Rubber Ind Ltd Elastomer roller

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0121865A2 (en) * 1983-03-31 1984-10-17 Siemens Aktiengesellschaft Circuit arrangement for telecommunication installations, especially for telephone exchanges comprising information processors and devices for overload control
JPS61128696A (en) * 1984-11-28 1986-06-16 Hitachi Ltd Control system of dispersion control type electronic exchanger
JPS6211355A (en) * 1985-07-09 1987-01-20 Fujitsu Ltd Congestion control system
JPH01318343A (en) * 1988-06-17 1989-12-22 Fujitsu Ltd Outgoing call restriction system
JPH0577508A (en) * 1991-09-21 1993-03-30 Sumitomo Rubber Ind Ltd Elastomer roller

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