JPS58197739A - Manufacture of substrate for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain buried regions insulatingly isolated by a dielectric by a method wherein grooves of the plural number are dug in a semiconductor substrate, and after the top parts of the grooves are covered with oxide films, epitaxial growth is performed to make single crystal layers to grow only on the bases of the grooves, and the buried regions are formed thereon by diffusion. CONSTITUTION:A P<+> type layer 11 is made to grow epitaxially on the P type Si substrate 10 having the (100) face, masks 12 of the plural pieces are provided on the surface, and anisotropic etching is performed to dig the V-shaped grooves 13 in the substrate 10. Then the parts other than the wall faces of the grooves 13 are covered with masks 14, P<+> type buried layers 15 are formed by diffusion in the exposed wall faces to be connected to the P<+> type layers 11, the masks 14 are removed, and the SiO2 films 16 are adhered on the surfaces forming mountain type by the layer 11 and the layers 15. After then, the N type layer is made to grow epitaxially on the whole surface to generate the single crystal layers 17 on the bases of the grooves 13, and polycrystalline layers 18 on the films 16, the layers 18 are etched to be removed, and the N<+> type layers 19 to act as the collector buried layers of the NPN transistors are formed by diffusion on the surfaces of the layers 17. Then a polycrystalline Si layer 21 is deposited through an SiO2 film 20, and the back of the substrate 10 is polished to obtain the buried layers isolated by the dielectric.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for fabricating a semiconductor integrated circuit substrate using dielectric insulation separation, and particularly relates to a method for forming a substrate for a semiconductor integrated circuit using dielectric isolation. The present invention relates to a method for manufacturing a nine-conductor integrated circuit substrate comprising islands of monocrystalline silicon of conductivity types IIi and H, respectively.

Dielectric insulation separation technology is suitable for high-speed integrated circuits because the volume can be made small; one voltage is large, so it is suitable for voltage integrated circuits or power ICs; It has many advantages, such as the ease of urification, the possibility of partial metal diffusion, and the ability to obtain both prefecture accumulation rates, and so on, and so on.

Utilizing the #4 Loquat separation technique as described above, the C, a complementary form of the Nyuhiro system is generated, even +i'P M)') F/
JISTA) JPN) U/JISTA t1-Autumn's 11 rounds are each equipped with islands of early Tsumugi crystal silicon with P 臘 and N-Rikihiro Kamieon, and Q using friend A board 4c. Must be. Regarding the system including all of these 4PM P) transistors and NPN) transistors and their manufacturing method, please refer to Japanese Patent Application Laid-Open No. F@5.
Although it is written in the specification of Publication No. 6-42352, etc.,
Regardless of which method is used, the etching of JIM crystal silicon requires repeated formation of the Evita-Sial layer, which increases the number of manufacturing steps, and the characteristics of the formed transistor. There is a problem in that it is difficult to form the conduction layer necessary to improve the process, or it is difficult to control the rounding impurities.

Therefore, the object of the present invention 1/) is to provide a method for fabricating a semiconductor layer using the $11 insulator outer edge technology, which can easily form an embedding layer.
Method of manufacturing road board @f: The purpose is to provide flame.

9. The purpose of this work is to attend the 4th time of the 4th year of the 4th year of the year of the year of the year.

In history, it is one aspect that the comparative efficiency of 1 duck V is the result of fJj key's 14 # books 4 Ik ual Fujo Nao.

Hereinafter, examples of the present invention will be explained with reference to the drawings. ,
Figure 1181 (MU-K) μ is a front cross-sectional view 2 showing the one-fall side floor of the 44Iit for the cow conductor Rakushu-ro according to the present invention.

The surface of the single-crystal silicon bonded plate 10 is polished to form a surface rIIi.
(too)d77i. In this case ^
Resistor; /J P # Silicon substrate is used, but
Even if the impurity is different in MW, #deka and #deka are formed in the same way as #so (mu).

A 9R type epitaxial layer 11 is formed on the surface of the PM silicon substrate 10 by doping impurities at a high concentration. The thickness of this A-type epitaxial layer is usually 6 μm to 5 μm. Of course, this epitaxial layer 11 (1o
o) Orient to ffi. This cypress is not necessary if a Pfi buried layer is not required (B).

Next, masks 1 and 1 for the epitaxial layer 11 are formed, and the substrate 10 is etched. Since the substrate 10 and the epitaxy aluminum 11 are (ILlO) circles, anisotropic etching is performed and a V-shaped hole 16 is gradually formed. +11 side dish is 2U~
When the scales reach 60μ, perform etching 'kmr (
C, D).

In order to form a digging layer not only on the surface reduction of the Pfi monocrystalline silicon 1 silicon island but also on the 1lli1, it is necessary to appear at Yasukuni in 11115 and form a part B'c mask 14 other than the Pfi monocrystalline silicon 10. Diffuse disk impurities (such as boron) through this window. Even if the filling layer 15 on the 911th side is not completely connected to the filling layer 11 of the bottom cylinder, it will still be difficult (I
li).

Next, 8io214 is formed in all areas other than the bottom of the groove 15. That is, the single crystal silicon substrate 10 is exposed only at the bottom of the groove (1).

In this way, BbOz 16 is partially formed on the surface of the nine substrate 10. Arnaud but 8
One surface of 40116 is made up of polycrystalline silicon 1B (
G).

While etching the crystalline silicon with a warm solution of 100Hz and 100Hz or hot phosphoric acid, the Mfi impurity was further enlarged on one side of the M1M single crystal silicon 17, and the impurity was thoroughly etched. A highly conductive layer 19 is formed. MPM in which this highly conductive layer 19 is formed on black of M-thickness crystalline silicon.
) Njista's attempt to dig in becomes no (H).

An 8AOs film 2o is also formed on the surface of the MiJIi single crystal silicon layer 17. This allows the surface of the single crystal 7977 layer (
The entire area (branch) is covered by 8LOm, making it 9 (I).

When silicon is deposited on the crystalline silicon covered with 8↓Ox flies, polycrystalline silicon 21 grows. Deposit polycrystalline silicon to a sufficient thickness to support the substrate (J).

Finally, polish the back side of the 1#III silicon substrate and
When LNG 16.20 appears on the surface, P-type and Mmu-) single crystal silicon ()) are insulated and separated by an 11-body film of 13 and 04, and are formed in multilevel silicon. (IC).

Above, we have explained how to make a P-type silicon substrate using a 4-piece C-type circuit board.You can also start with M-type silicon. Rin, and: A, etc. r 44) J, υ shrimp 7'f
The material is doped with the material and doped with boron, etc. during epitaxial growth. Others yc:) #tThe factory will be built and manufactured in the same camphor. It should be noted that the substrate is not limited to (10v) as in the above example, but may be any other type, although recesses may be selectively formed.

In addition, for Saigo that does not require the formation of horikomime, a part of the above-mentioned one unit may be omitted.

No. 2m is a front cross-sectional view of an example of an integrated circuit solder using a nine-conductor integrated circuit board manufactured according to the present invention.
Islands of single-crystal silicon (J) and Mli are formed by conventional enlarging techniques. Since the collector layer is formed in advance, it is easy to manufacture and the characteristics can be easily achieved.
It is also possible to use it for MO8) transistors, etc.

According to the present invention, P temperature and Jl of single crystal silicon of 111
If & can be formed easily, the necessary Hatokura Yuko will be able to form a 1-layer with only 1 addition. Afterwards, when Akinari becomes rLel element 1! ! It is also possible to improve By using epitaxial growth and diffusion in forming the eluted layer, it becomes easy to control the true impurity concentration of the p-diffusion coefficient.

Since trench nine and anisotropic etching only need to be performed once,
It also has the advantage of preventing a decrease in yield and a decrease in the degree of integration caused by under-etching.

[Brief explanation of the drawing]

1 (capital) is a front sectional view explaining the present invention in detail;
The figure shows a front view of an example of an integrated circuit manufactured in accordance with the present invention and formed on nine substrates. 10... Single crystal silicon substrate (1'fJIi)
. 11...Ffi epitaxial layer. 12.14...Mask. 14.20...Oxide film. 17...Ma epitaxial layer. 1d, 21... Polycrystalline silicon. 19...M 臘expanded ridge layer. 61...PIP) transistor. 52...MPM) Tsu/Jista 4 Koyama-hito IIWb Harine Technology Research Association Representative Tsuhito No. 1 Figure n yPJt Note

Claims (1)

[Claims] A recess is formed by selectively etching the surface of the conductive conductive crystal semiconductor substrate, and a single crystal semiconductor layer of opposite conductivity is epitaxially grown on the bottom of the recess. After forming a temporary single crystal semiconductor layer and an insulating film on the surface of the single crystal semiconductor layer, polycrystalline silicon is deposited on the insulating layer, and the semi-crystalline P4I bonding plate is covered with an insulating film. by grinding with a horse's shovel to form at least two islands of monocrystalline silicon supported by the polycrystalline silicon and separated by the loquats; ! 21 road board manufacturing method.