JPS58194356A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain favorable multilayer structure, and to make dielectric breakdown hardly generate between a first and a second polycrystalline silicon layers according to pin holes by a method wherein a silicon nitride film is provided under the substantially whole base of the second polycrystalline silicon layer on the first polycrystalline silicon layer. CONSTITUTION:After an oxide film is provided on the surface of a P type silicon substrate 11, the field oxide films 12 of the regions other than an active region of normal transistor, etc., are left. After gate oxide films 13 are formed, the first polycrystalline silicon layers are formed according to vapor phase growth, etc. Phosphorus is diffused into the substrate 11 and the first polycrystalline silicon layers 14 to form N type regions 15 in the substrate 11, while the polycrystalline silicon layers 14 are converted into the N type, and moreover the field oxide films 12 are converted into phosphorus glass. A silicon oxide film 16 is provided, the second polycrystalline silicon layer 18 to be adhered with a silicon nitride film 17 for protection is formed thereon, and the pattern is formed. Then phosphorus is diffused into the second polycrystalline silicon layer 18 and the silicon nitride film 17. Silicon oxide films 20 are provided again according to thermal oxidation, and by providing aluminum wirings 21, the three layer N channel MOS integrated circuit device is completed.

Description

[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

In semiconductor integrated circuit devices, there is a big demand for increasing the degree of integration, and one way to meet this demand is multilayer i! The wiring usually has a 2/i! structure of a polycrystalline silicon layer and an aluminum layer, but multilayer wiring can be realized by forming one or more polycrystalline silicon layers between these two layers.

FIG. 1 is a cross-sectional view of an example of a conventional semiconductor integrated circuit device with multilayer wiring.

After providing a field oxide film 2 on a P-type silicon substrate l,
A hole is opened and a gate oxide film 3 is provided. After a first polycrystalline silicon layer 4 is provided on the oxide films 2 and 3, a region to become an active region is opened and phosphorus is diffused to form an N-type region 5. A silicon oxide film 6 is formed by oxidation again, a second polycrystalline silicon layer is provided thereon, and selectively etched by photolithography to form a second polycrystalline silicon pattern 17. Since a hydrofluoric acid-nitric acid solution is usually used for this selective etching, the silicon dioxide film 6 is also attacked during etching and etching, and the silicon oxide film below the edge of the second polycrystalline silicon layer 7 is removed. Sometimes. On the other hand, if a silicon nitride film is provided around the second polycrystalline silicon layer for this purpose, this silicon nitride film is provided between the first polycrystalline silicon layer and the second polycrystalline silicon layer. Surface irregularities occur. Further, the capacitor between the first and second polycrystalline silicon layers is not constant in each part.

An object of the present invention is to provide a semiconductor integrated circuit device having first and second polycrystalline silicon layers.
An object of the present invention is to provide a semiconductor integrated circuit device in which a polycrystalline silicon layer has a constant interval in each part and a constant capacitor between each part.

The present invention is characterized by a first polycrystalline silicon layer selectively provided on a semiconductor substrate, and a second polycrystalline silicon layer selectively provided on the first polycrystalline silicon layer with an insulating layer interposed therebetween. In a semiconductor integrated circuit device having a crystalline silicon layer, the insulating layer includes a silicon oxide film, and the insulating layer is provided on the silicon oxide film and is provided under substantially the entire bottom surface of the second polycrystalline silicon layer. A semiconductor integrated circuit device includes a silicon nitride film.

In this way, in the present invention, the WJ on the first polycrystalline silicon layer
Since a silicon nitride film is provided under substantially the entire bottom surface of the polycrystalline silicon layer No. 2, a preferable multilayer structure is obtained, with constant intervals between the two layers without unevenness in each part.
Since each part has a certain capacitor, when this layer is used as a wiring, the capacitor at the part where each wiring crosses three-dimensionally has a certain value, so it is easy to design the IC to a predetermined value, and both Since a multilayer insulating film is present in any part between the layers, dielectric breakdown between the two layers due to pinholes, which would occur in the case of a single film, is less likely to occur.

Next, the present invention will be explained by examples.

2 to 6 are process cross-sectional views when the method of the present invention is applied to a three-layer N-channel silicon gate M08 type integrated circuit device.

After forming an oxide film with a thickness of about 1 μm on the surface of the P-type silicon substrate 11, a field oxide film 12 is formed in areas other than active areas such as transistors by ordinary photolithography.
(Figure 2).

Subsequently, after forming a gate oxide film 13 with a thickness of about 100 OA, a first polycrystalline silicon layer with a thickness of about 500 OA is formed by vapor phase growth, etc., leaving the gate electrode part 14, wiring part 14, etc. of the transistor. The first polycrystalline silicon layer is etched as shown in FIG.

Subsequently, after removing the gate oxide film 13 in the portion of the substrate 11 where the diffusion layer is to be formed by etching, phosphorus is diffused at 100 Or into the substrate 11 and the first polycrystalline silicon layer 14 to form the substrate 1.
An N-type region 15 is formed in the polycrystalline silicon layer 1.
4 is changed to N type, and the field oxide film 12 is changed to phosphorus glass. A silicon oxide film 16 with a thickness of about 500 OA is provided again by M& process, and a silicon nitride film 17 with a thickness of several hundred Å is deposited thereon as a preservative (FIG. 4).

Next, a second polycrystalline silicon layer 18 having a thickness of about 500 OA is formed, and this layer 18 is etched using a hydrofluoric acid-nitric acid solution using a photolithography method to form a pattern. Since the silicon nitride film 17 is not attacked by the hydrofluoric acid-nitric acid type etching solution, it protects the underlying silicon oxide film 16. Subsequently, phosphorus is diffused into the second polycrystalline silicon layer 18 and the silicon 9ide film 17.

The exposed portion of the silicon nitride group 17 changes into phosphorus glass 19 due to phosphorus diffusion. Therefore, the step of removing the silicon nitride film 17 is unnecessary (FIG. 5).

A silicon oxide film 20 is formed again by thermal oxidation, holes are formed by photolithography, and a 3NIIN channel MO8 type integrated circuit device is completed (FIG. 6).

Furthermore, according to this embodiment, there are no disconnections or short circuits due to steps, and no parasitic MO8FET is generated (*), since a semiconductor integrated circuit with multilayer wiring can be obtained.

[Brief explanation of the drawing]

The fla1 diagram is one of a conventional multilayer wiring semiconductor integrated circuit device.
FIGS. 2 to 6 are cross-sectional views showing the manufacturing process of a three-layer N-channel silicon gate MO8 type integrated circuit device according to an embodiment of the present invention. 1.11...P-type silicon substrate, 2.12...
...Field oxide film, 3,13...Gate oxide film, Fig. 3 Fig. 4 Fig. 1 Fig. 3 // Fig. Otsu 2

Claims (1)

[Claims] A first polycrystalline silicon layer selectively provided on a semiconductor substrate, and a second polycrystalline silicon layer selectively provided on the first polycrystalline silicon layer with an insulating layer interposed therebetween. In the semiconductor integrated circuit device, the layer includes a silicon oxide film and the second layer provided on the silicon oxide film.
a silicon imaging film provided under substantially the entire bottom surface of a polycrystalline silicon layer.