JPS58191450A - Multilayer wiring structure - Google Patents
Multilayer wiring structureInfo
- Publication number
- JPS58191450A JPS58191450A JP7401882A JP7401882A JPS58191450A JP S58191450 A JPS58191450 A JP S58191450A JP 7401882 A JP7401882 A JP 7401882A JP 7401882 A JP7401882 A JP 7401882A JP S58191450 A JPS58191450 A JP S58191450A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- conductive material
- wiring layer
- wiring structure
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims description 21
- 239000004020 conductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明は多層配線構造に関する。[Detailed description of the invention] The present invention relates to a multilayer wiring structure.
従来、多層配線構造は第１図に示す如く、絶縁基板１上
に第１の導電体である多結晶８１等の配線層２を形成し
、その上に形成されたＳ１０．膜等からなる層間絶縁膜
５を介して、コンタクト穴４を通して、第２の導電材料
であるＡｔ等の配線層５が形成されて成っている。Conventionally, in a multilayer wiring structure, as shown in FIG. 1, a wiring layer 2 such as a polycrystalline 81 which is a first conductor is formed on an insulating substrate 1, and S10. A wiring layer 5 made of a second conductive material such as At or the like is formed through the contact hole 4 via an interlayer insulating film 5 made of a film or the like.
しかし、上記従来技術では、例えばコンタクト部の寸法
が２μ賜×２μ集の場合、２５０程度の接触抵抗であっ
たものが１μ愼×１μ集のコンタクト穴にした場合には
１０００程度もの高抵抗となり、配線の微小化による大
集積化と、それに伴う電子回路の高速化に向かないとい
う欠点があった。However, with the above-mentioned conventional technology, for example, when the contact hole has dimensions of 2 μm x 2 μm, the contact resistance is about 250, but when the contact hole is 1 μm x 1 μm, the contact resistance becomes as high as about 1000. However, it has the disadvantage that it is not suitable for large-scale integration due to miniaturization of wiring and the accompanying speed-up of electronic circuits.
本発明は、かかる従来技術の欠点をなくし、大集積で高
速化に向いた多層配線構造を提供することを目的とする
。It is an object of the present invention to eliminate the drawbacks of the prior art and to provide a multilayer wiring structure suitable for large scale integration and high speed.
上記目的を達成するための本発明の基本的な構成は、多
層配線構造において、基板上には第１の導電材料からな
る配線層が形成され、層間絶縁膜を介して、コンタクト
穴部を通して第２の導電材料からなる配線層を形成する
多層配線において、第１の導電材料の少なくとも下部ま
たはその一部に第２の導電材料層が形成されて成る事を
特徴とする。The basic configuration of the present invention for achieving the above object is that in a multilayer wiring structure, a wiring layer made of a first conductive material is formed on a substrate, and a wiring layer made of a first conductive material is passed through a contact hole through an interlayer insulating film. In the multilayer wiring forming wiring layers made of two conductive materials, the second conductive material layer is formed at least under or in part of the first conductive material.
以下、実施例により本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.
第２図は本発明による多層配線構造の一実施例を示す断
面図である。FIG. 2 is a sectional view showing an embodiment of a multilayer wiring structure according to the present invention.
絶縁基板１１上には第１の導電材料からなる多結晶８１
等の配線層が形成され、その下部の一部または全部には
第２のｋｔ等の導電材料層部１４が形成されている。層
間絶縁膜１３をはさんで、層間絶縁膜１３の部を穴開け
したコンタクト穴部１５を介して、第２のムを等の絶縁
材料からなる配線層１６が形成されて成る。On the insulating substrate 11 is a polycrystalline 81 made of a first conductive material.
A wiring layer such as KT is formed, and a second conductive material layer 14 such as KT is formed in part or all of the lower part thereof. A wiring layer 16 made of an insulating material such as a second layer is formed with the interlayer insulating film 13 in between and through a contact hole 15 made in the interlayer insulating film 13.
上記の如く、第１の配線層１２の下部又は一部に第２の
配線層１６と同一材料のｌｌＸ１４を形成して、コンタ
クトをとることにより、第１の配線層１２と第２の配線
層１６のコンタクト部における実質的な接触面積が増大
し、′小面積のコンタクト部寸法にもかかわらず低接触
抵抗接続が可能となり、大集積で高速の電子回路用の配
線が行なえる効果がある。As described above, by forming llX 14 of the same material as the second wiring layer 16 under or in part of the first wiring layer 12 and making contact, the first wiring layer 12 and the second wiring layer The substantial contact area of the 16 contact portions is increased, and a low contact resistance connection is possible despite the small contact portion size, which has the effect of enabling wiring for highly integrated, high-speed electronic circuits.
本発明は絶縁基板のみならず、半導体基板上の多Ｉ−配
線にも適用できる。The present invention can be applied not only to insulating substrates but also to multi-I interconnects on semiconductor substrates.
第１図は従来技術の多層配線構造、第２図は本発明によ
る多層配線構造を示す断面図である。
１．１１・・・・・・基 板
２．１２・・・・・・第１の配線層
３．１３・・・・・・層間絶縁膜
４．１５・・・・・・コンタクト穴部
５．１６・・・・・・第２の配線層
１４・・・・・・・・・・・・第１の配線層下の第２の
配線材料層
以 上
出願人 株式会社靜訪精工舎
代理人 弁理士 最上 務FIG. 1 is a cross-sectional view showing a conventional multilayer wiring structure, and FIG. 2 is a cross-sectional view showing a multilayer wiring structure according to the present invention. 1.11...Substrate 2.12...First wiring layer 3.13...Interlayer insulating film 4.15...Contact hole portion 5 .16...Second wiring layer 14...Second wiring material layer below the first wiring layer Applicant: Seiwa Seikosha Co., Ltd. Person Patent Attorney Tsutomu Mogami
Claims (1)
層間絶縁膜を介して、コンタクト穴部を通して第２の導
電材料からなる配線層を形成する多層配線において、第
１の導電材料の少なくとも下部又はその一部に、第２の
導電材料層が形成されて成る事を特徴とする多層配線構
造。A wiring layer made of a first conductive material is formed on the substrate,
In a multilayer wiring in which a wiring layer made of a second conductive material is formed through a contact hole through an interlayer insulating film, a second conductive material layer is formed at least under or in a part of the first conductive material. A multilayer wiring structure characterized by consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7401882A JPS58191450A (en) | 1982-04-30 | 1982-04-30 | Multilayer wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7401882A JPS58191450A (en) | 1982-04-30 | 1982-04-30 | Multilayer wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58191450A true JPS58191450A (en) | 1983-11-08 |
Family
ID=13534945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7401882A Pending JPS58191450A (en) | 1982-04-30 | 1982-04-30 | Multilayer wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58191450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4855014A (en) * | 1986-01-24 | 1989-08-08 | Sharp Kabushiki Kaisha | Method for manufacturing semiconductor devices |
| US5294821A (en) * | 1990-10-09 | 1994-03-15 | Seiko Epson Corporation | Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors |
-
1982
- 1982-04-30 JP JP7401882A patent/JPS58191450A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4855014A (en) * | 1986-01-24 | 1989-08-08 | Sharp Kabushiki Kaisha | Method for manufacturing semiconductor devices |
| US5294821A (en) * | 1990-10-09 | 1994-03-15 | Seiko Epson Corporation | Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors |
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