JPS5819065A - Mn modulator - Google Patents

Abstract

PURPOSE:To decrease the frequency band of a transmission signal, by providing an inverting section check circuit and a DC average value inspection circuit consisting of a code converting circuit converting bits, a minimum section detecting circuit for codes, a maximum inverting section detection circuit and a pseudo synchronizing signal check circuit. CONSTITUTION:When a DC average value is positive and an NRIZ signal (e) designates the count-up, and output (h) of an FF534 is at logical ''0'', the signal (e) passes through an exclusive logical operation circuit 532 and is applied to a counter 533 as a signal (f) instructing the count-up of the up-down counter 533. Next, the signal (e) is inverted and the signal (f) is applied to the counter 533, then the counter starts count-down. When the counter value goes to ''0'', a borrow signal (g) is outputted and the FF534 is inverted and it is indicated that the DC average value is negative. As a result, since the signal through the circuit 532 is inverted, even if the signal (e) indicates the count-down succeedingly, the counter starts the count-up. In this case, the counter value represents the absolute value of the average DC and the code is provided in the FF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention converts a code in which one word is represented by M bits into a code of one word with N bits, and further adds a code of P bits to form one word with a total of N0P bits. The present invention relates to a modulation device based on a code modulation method (hereinafter abbreviated as MN modulation) that constructs a code, converts the code into an NRZI code, and sends it out.

In general, when transmitting and receiving digital signals, the transmission line generally exhibits the characteristics of a low-pass filter, so when the frequency spectrum of the signal has fewer high-frequency components, that is, the longer the minimum inversion period of the signal, the more likely there will be code amount interference. It is difficult to accept. Furthermore, in order to stably perform clock recovery from the received signal, it is preferable that the maximum inversion period of the signal be as small as possible. Furthermore, in order to ensure stable waveform reproduction, it is desirable that the DC average value of the signal be constant. One of the modulation methods that satisfies these requirements is the MN modulation method.

Next, MN modulation method 1 will be explained. In the MN modulation method, data in which one word consists of M bits is converted into a pattern of N bits (N>M), and a code of P bits is added (P(N)), resulting in a total of N+P bits. This is converted into the NRZ I signal I (converted and transmitted. Since the M-bit sign is converted into N-bit f,
It seems that the transmission frequency band increases, but the minimum inversion interval of the signal converted to NRZIi is Tm1n (≧P)
Then, the maximum code inversion period is Tmax + N
Since the bit code and the additional code of P bits are selected, the result is simply (N0P/M)/To-tin times. For example, when M=8, N=14, P=8°Tm1n=8, the value of the above equation is about 07. Therefore, by performing MN modulation, it is possible to reduce the transmission band.

To define the sign reversal interval to satisfy the above conditions,
A conversion table for converting an M-bit code into an N-bit code may be determined so as to satisfy the above conditions. This condition is satisfied if N is set appropriately. In this way, 1
Although the above condition is satisfied within the word code, there is a possibility that the condition is no longer satisfied at the connected portion of each word. Therefore, the above condition can be satisfied by adding a P-bit code to the connected portion of each word and adjusting the P-bit pattern according to the word pattern of Ryugo.

Furthermore, by appropriately selecting this P bit pattern, NRZI
By minimizing the difference between the number of 1° bits and the number of 0 bits of the i number (this is called the DC average value), it is possible to transmit with less waveform distortion on a transmission line that does not pass DC components. becomes possible. Furthermore, in order to achieve word synchronization during demodulation, a synchronization signal is inserted every several words.

An example of a specific MN gray adjustment device that implements the MN modulation method of the present invention will be described below. FIG. 1 shows a block diagram of the MN modulation device. The M-bit input signal (E) is a read-only memo containing a conversion table! j (RO
M ) (1) into N bits. The r data (n) converted into N bits is output in series, branched by the number of all additional patterns composed of P bits, and each additional pattern inspection circuit <5) (6) to (7)
An additional pattern is added by Tmin,
It is checked whether conditions such as Tmax* are satisfied. For example, in the additional pattern inspection circuit (5) in Figure @2, the pattern P1 is determined by the preset shift register value M.
The N+P bit data (0) to which is added is further branched into two circuits and inputted to a sign inversion section test circuit 4 and a DC average value test circuit, respectively.

As shown in FIG. 8, the sign inversion section checking circuit hn is
A counter that is cleared by N+P bit data (0) (
521), a minimum reversal section test circuit (522) that manually inputs the output signal (q), and a maximum reversal section test circuit (Fa
fl), a pseudo synchronous signal test circuit (524) inputting data (o), and an OR circuit (52) for their test outputs.
5) and 1.

Next, before describing the operation of each test circuit, the NRZI signal will be explained. As shown in FIG. 4, the NRZI signal is a signal that is inverted when the input signal (0) is at logic 1". Therefore, Cζ, which is used to check the inversion section, is the logic 1" of input signal (o). All you need to do is measure the interval between the input signal (0
) can be checked by checking the output signal 6) of the counter (521).

First, the minimum inversion interval test circuit (522), as shown in FIG.
21) from the output signal (q) to the swelling reversal section Tm1n-1
is decoded and its output (C) is sent to a flip-flop (5
222) Gate circuit added to the glue cent terminal (5221
), and a logic type circuit (5228) that performs the logical product of the output (r) of the flip-flop (5222) and the human input signal (0) and outputs the output (s). The operation of this circuit is as shown in Fig. 4. When the logical interval of the input signal 1' is less than the minimum inversion interval Tan in, the output (r) of the flip-flop (5222) is set. The input signal (0) remains as it is, and the minimum inversion interval violation signal is output (S) by ANDing it with the next logic °1". In this example, Tm1n = 8. Since the counter counts from 0, , if the counter value becomes 2, the minimum inversion interval f will not be violated.

The maximum inversion section inspection circuit (528) is a counter (521)
This is a gate circuit that decodes the maximum inversion period Tmax from the output (q) of and outputs it. As shown in Figure 4, Tm
If ax = 6, output (1) is obtained. In this case, if the counter value reaches 6, the maximum inversion interval is violated.

As shown in FIG. 6, the pseudo synchronous signal inspection circuit (524) has a shift register (52) that shifts the input signal (0).
41) and a gate circuit (5242) that detects that the parallel cover turn (v) matches the synchronization signal. In the example shown in FIG. 4, the synchronization pattern is 100100". At the position of the regular synchronization signal, the gate circuit (5242) is activated to stop the output of the pseudo synchronization signal inspection circuit (524). The signal (y) is input, and even if a synchronization pattern is detected at that time, the output (U
) will not appear.

Each signal detected in this way (Sl) (t) (u)
is a logical sum circuit (525
) I enter. The output 0) of the OR circuit (525) prohibits DC average value comparison described in the next section when the input signal (0) violates the minimum inversion interval or maximum inversion interval, or when a pseudo synchronization signal is detected. Output as a signal. OR circuit (525) consisting of this flip-flop
As shown in Figure 7, the code DC average value test circuit, which is reset for each word, is as shown in Figure 7.
The logic of the input signal (0) is inverted at 1" and becomes the NRZI signal (
A flip-flop (581) that generates e) and an exclusive OR circuit (582) that uses its output (e) as one input.
, an up/down counter (58B) that counts up or down according to its output (f), and a flip-flop (58B) that inverts according to its borrowed output (ω).
4). flip flop (584)
The output (h) is configured to be the other input of the exclusive OR circuit (582).

The operation of the DC average value test circuit is as shown in NRZI in Figure 4.
The difference between the logic "1" section of the signal and the logic "0" section is counted and used as the DC average value.In the transmission line, a logic "1 degree signal means an outflow of direct current, and the logic "O" ” signal means inflow of current. If the outflow and inflow of this current are equal in the long run, there is no direct current component, and signals can be transmitted even through a transmission path that does not pass blood flow components. Therefore, in this MN modulation method, the additional bit pattern l) is determined so that this DC average value always approaches zero.

For this purpose, first, in this circuit, the DC average value is counted by an up/down counter (53B). The counting method is to divide the DC average value into an absolute value and a positive/negative sign. This is because whether the DC average value is positive or negative does not matter; it is important to control the DC average value so that the absolute value is small. Furthermore, in a counter that represents a negative number as a two's complement number, in order to compare the magnitude of the absolute value, it must be converted into an absolute value. requires one circuit to take two's complement numbers, which has the disadvantage of increasing the circuit scale. According to this circuit system, an absolute value counter can also be realized with a simple circuit configuration.

The operation will be described below. Figure 7 Furi, Pflop (5
84) represents a sign bit representing the sign of the DC average value. Assuming that the DC average value is initially positive and the NRZI signal (e) specifies count up, the output (11) of the flop (584) is logic 0, and the NRZ I signal (e) is Exclusive logic circuit (5
82) and is applied to the up/down counter (58B) as a signal (f) instructing the up/down counter (588) to count up. Next, the NRZI signal (e
) is inverted and thus the down signal (f) is applied to the amplifier down counter (1,188), the counter starts counting down. When the counter value reaches 0, the borrow signal (g) is output, and the flip-flop (584) is inverted, indicating that the DC average value has become negative t.As a result, the exclusive OR circuit ( 582) is inverted so that the counter begins counting up even though NR7, lt. (e) continues to indicate a countdown.

At this time, the counter value represents the absolute value of the DC average value, and its sign is in the flip-flop (584). The absolute value of the DC average value counted in this manner is output as an output signal (d) of the counter (588).

Similar tests are performed for all combinations of the additional bit pattern P at each test time [(5) (
8) to (7), and each test output (i) ω
).

(ge(d7~(ge(dT enters the comparator circuit (4) in Fig. 1. The comparator circuit (4) consists of two number comparison circuits 1-')-structure as shown in Fig. 8. The magnitude comparison circuit θη on the leftmost stage is the set of DC average value test signals (d) mentioned above.
Input (dy and each comparison prohibition signal (i) (iy), compare the magnitude of two numbers (d) (dy), and output the smaller value to the next stage.

The comparison prohibition signal (i) is input as the most significant bit of each input (d) (dy. Therefore, for example, if the comparison prohibition signal (i) is a logic degree of 1 degree, the value of d+j is the value of d'. Regardless of the value, if it is greater than d'+i', the magnitude comparison circuit (4◇ outputs the smaller signal (d)', (iy) to the next stage.Similarly, magnitude comparison is performed at each stage, and the final The minimum DC average value is obtained as the output (a) of the stage size comparison circuit θHinoki.This value is used as the initial value for each additional pattern inspection circuit (5) (6) to determine the next additional bit.
) to (7) are preset in the up/down counter (538) in the DC average value inspection circuit.

On the other hand, the comparison result signal (b
) is added to the additional pattern determining circuit (2).

The additional pattern determining circuit (2), as shown in FIG. 9, has a shift register 30 and a shift register with preset (a) connected in series. The three shift registers are necessary to secure the testing time for each additional pattern testing circuit (5), (6) and (7) until the time when the comparison result signal (b) is applied to the additional pattern determining circuit (2). , holds the signal (n). For the shift register with preset), determine the optimal addition pattern according to the comparison result signal color),
Add to signal (n).

In this way, the optimal addition pattern is added to the signal U)
is added to the flip-flop (3) and the NRZI signal (
2) and output.

It should be noted that in this embodiment, the demodulator was not described.
The demodulation method is similar to the conventional method, after passing the NRZI signal through an NRZI conversion circuit consisting of a flip-flop and an exclusive logic circuit, detecting a synchronizing signal to establish word synchronization, skipping the additional pattern, and transmitting the n-bit pattern to a ROM circuit or It can be converted to m bits using a similar circuit.

Furthermore, in this embodiment, a shift register and a gate circuit are used as the pseudo synchronous signal inspection circuit, but the counter (521)
It is also possible to decode and use the output of

In the case of this embodiment, the counter force 1. l, 2,
If it changes to 0°1.2”, it means that a pseudo synchronous pattern has been detected.

As described above, by using the MN modulation device according to the present invention, it is possible to lower the frequency band of the transmission signal, and moreover, the clock can be regenerated stably from the signal itself, and even in transmission lines where direct current components cannot be transmitted. It can transmit signals, and has great effects when used for data transmission, recording and reproducing digital data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the M N father adjustment device according to the present invention, FIG. 2 is a block diagram of an additional pattern inspection circuit, and FIG. 8 is a block diagram of a code minimum inversion section, maximum inversion section, and pseudo synchronous signal inspection circuit. , FIG. 4 is a timing diagram for explaining the operation of the additional pattern test circuit, FIG. 5 is a code minimum inversion interval test circuit diagram, and FIG. 6 is a pseudo synchronization signal test circuit diagram.
FIG. 7 is a block diagram of the DC average value inspection circuit, FIG. 8 is a block diagram of the magnitude comparison circuit, and FIG. 9 is a block diagram of the additional pattern determination circuit. (1)...MN code converter, (2)...Additional pattern determination circuit, (3)...NRZ I conversion flip-flop, (5) (6)-(7)...Additional pattern Inspection circuit, wa】)...Shift register with preset, (
5 No... Sign inversion section inspection circuit, (-... DC average value inspection circuit, (521)... Counter % (522
)...Minimum inversion section inspection circuit, (528)...
Maximum inversion section test circuit, (524)...Pseudo synchronous signal test circuit, (5221)...Gate circuit, (52
22)...Flip-flop, (5228)...
・AND circuit, (6241)...shift register, (
5242)...Gate circuit, (581)...Flip-flop, (582)...Exclusive logic circuit, (5
88)...up/down counter, (584)...
Flip-flop, GIH-U...size comparison circuit, (
c)...shift register, c)...preceratoy size shift register, 6nl...M-bit input signal,
(n)...N bit signal, (d)...DC average value,
0)... Comparison prohibition signal, (Z)... NRZI output signal agent Yoshihiro Morimoto Figure 5 Figure 7 Figure 3 Figure D

Claims (1)

[Claims] 1. A modulation device using a code modulation method (MN modulation) that converts a one-word M-bit code to N bits, adds an E-P bit code, and then converts it to an NRZ I signal,
It has a code conversion circuit for converting an M-bit sign into N bits, a code minimum inversion period test circuit, a maximum code inversion period test circuit, and a pseudo synchronization signal test circuit. MN modulation characterized by determining the P bit pattern to be added so that the DC average value, which is the difference between the number of "1°" and the number of "0" of the NRZI signal bits, is minimized by the outputs of these test circuits. Device. 2. The minimum inversion interval checking circuit and the maximum inversion interval checking circuit of the code detect the code by the count value of the counter that is cleared by the logic “】” of the signal in which the sign of P bits is added to the code converted to N bits. 2. The MN modulation device according to claim 1, wherein the minimum inversion interval and the -maximum inversion interval are checked. 8. The DC average value inspection circuit includes an up-down counter, a flip-flop that is inverted by the output of the up-down counter, and an NRZ signal between the output of the flip-flop and the flip-flop.
Consists of an exclusive OR circuit that performs an exclusive OR with the I signal,
2. The MN modulation device according to claim 1, wherein the count up or count down of said up/down counter is determined by said exclusive OR output. 4. For all the allowed patterns of the added P-bit code, a code inversion interval testing circuit and a DC average, each consisting of a minimum inversion interval testing circuit, a maximum inversion interval testing circuit, and a pseudo synchronization signal testing circuit, are provided. The P bit pattern to be added is determined by a size comparison circuit which has a value verification circuit and selects from each P bit pattern the one that does not violate any of the above inspections and has the smallest absolute value of one DC average. 2. The MN modulation device according to claim 1, wherein the MN modulation device determines . 5. The M N modulation device according to claim 1, wherein the pseudo synchronous signal inspection circuit detects the pseudo synchronous signal from a shift register and a gate circuit f which duplicates its parallel output.