JPS58190058A - Method for manufacturing thin film field effect transistors - Google Patents

Abstract

PURPOSE:To contrive the improvement of operation speed of a TFT circuit and thus enable to form elements into fine structure and high integration, by having the forming process for a gate electrode, exposing process for a semiconductor film surface, and forming process for a contact electrode. CONSTITUTION:An undoped a-Si film 12 of thickness 1500Angstrom is deposited on a glass substrate 11 by the glow discharge of SiH4, then a Si oxide film 13 of thickness 3000Angstrom serving as a gate insulation film is deposited thereon, and next the gate electrode 14 is formed by pattern formation after evaporating a Cr/ Au film of 1000Angstrom . A P doped a-Si film is deposited to the thickness of 1000Angstrom , then the contact electrodes 151 and 152 of source and drain self-aligned to the gate electrode 14 by utilizing step cuts at edges of the gate electrode 14 are formed, and the P doped a-Si film of unnecessary parts is etching-removed. Finally, an Mo/Al film is evaporated in 5000Angstrom , and formed into patterns resulting in the formation of each take-out electrodes 161-163 for the source, drain, and gate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a thin film field effect transistor using a semiconductor film such as amorphous silicon.

[Technical background of the invention and its problems]

is attracting attention. In particular, since the semiconductor thin film described above can be formed at low temperatures, there are no particular restrictions on the substrate that constitutes the thin film semiconductor device, and conventional pattern forming methods such as exposure technology and etching technology can be used as is, making it possible to form large-area substrates. Since it has advantages such as being able to be integrated, semiconductor devices with a wide variety of structures can be realized depending on the purpose. In order to fully utilize the functions of semiconductor devices using these semiconductor thin films, TF'Ts are often provided as switching elements or active circuit elements within the same substrate. This makes it possible to functionally integrate semiconductor devices using semiconductor thin films, and its applications become extremely wide-ranging.

1 to 3 are diagrams schematically showing the basic structure of a conventional TPT. In these figures, 1 is an insulating substrate, 2
is a-81 or polycrystalline silicon y (Poly-St
), 3 is a date insulating film, 4 is an r-to electrode, 5 and 6 are source and drain electrodes, and 7.
8 is an impurity-doped semiconductor film for obtaining good ohmic contact. An r-) electrode, a source electrode 5, and a drain electrode 6 are provided on the same side of the mononoke semiconductor film 2 in FIGS. 1 and 2, and the semiconductor thin film 2 in FIG.
A date electrode 4 is provided on the lower surface side, and a source electrode 5 and a drain electrode 6 are provided on the upper surface side. These TPTs exhibit electrical characteristics similar to so-called MOS FETs using single-crystal silicon, but the fundamental difference in operating principle from MOS FgTs is that the transistor channel renewal conditions are different from the PN junction in MOS FETs. In contrast, TPT utilizes the high resistance of the semiconductor thin film 2. Both channel conduction states utilize inversion or carrier accumulation on the semiconductor surface due to field effects. Therefore, in order to construct these TPTs, it is necessary that the resistance of the semiconductor thin film 2 in the non-conducting state be sufficiently higher than the resistance when the channel is formed. Note that when the substrate 1 is made of a conductive material as a starting substrate, an insulating film is provided on its surface and used as an insulating substrate.

Now, these TFTs are a-St or Poly-S
Since a semiconductor film such as T is used, the mobility of electrons and holes serving as carriers is lower than that of a single crystal semiconductor.

In particular, the decrease is remarkable for a-81. For this reason,
Compared to MOS FET using crystal conductor material, TPT
The operating frequency limit is quite low. Also,
When a plurality of such TPTs are integrated on a substrate, the operating speed thereof is generally much slower than the above-mentioned operating frequency limit.

This is mainly caused by a time delay due to parasitic capacitance based on wiring and transistor structure. In TPT, an insulating substrate can be used, so it is easy to avoid parasitic capacitance between the wiring and the substrate. However, in the conventional structure shown in Figs.・The influence of parasitic capacitance due to the overlap of electrodes between darts is large. Generally, in order to increase the operating speed of a circuit including a TF'Ti that has parasitic capacitance, it is sufficient to lower the resistance in the ON state of the TPT, but to do this, the width of the current path (channel width) of the TPT must be increased. There is a need.

In this case, in the conventional TPT structure, the parasitic capacitance also increases in proportion to the channel width, so that the operating speed is not essentially improved.

[Purpose of the invention]

In view of the above points, the present invention aims to improve the operating speed of the TPT circuit by self-aligning the gate electrode and the source/drain, and provides a TPT manufacturing method that enables miniaturization and high integration of the device. It provides:

5- [Summary of the Invention] In the present invention, a semiconductor film is first deposited on an insulating substrate, its surface is covered with an insulating film, and a gate electrode is formed thereon. Using this dirt electrode as a mask, the insulating film is etched to expose the surface of the semiconductor film in the source and drain regions. After this, a conductive film is applied to the case so that a break occurs at the edge of the r-toe electrode.
Form source and drain contact electrodes that are self-aligned with the gate electrode. Note that the source and drain contact electrodes are patterned so as to remain only in necessary regions. This flat turning can be performed after or before providing the source and drain extraction electrodes.

[Effects of the Invention] Therefore, according to the present invention, since a source/drain that is self-aligned to the date can be formed, the parasitic capacitance between the dirt electrode and the source/drain electrode is small, and high-speed operation is possible. Moreover, the TPT circuit can be miniaturized and highly integrated.

[Embodiments of the invention]

Examples of the present invention will be described below with reference to FIGS. 4(a) to 4(,). First, an AND-PRO-3i film 12 with a thickness of 1500X is deposited on a glass substrate 1 by glow discharge of 5IH4, and then a silicon oxide film 13 with a thickness of 3000X, which will become a keto insulating film, is deposited on this by plasma CVr). After depositing Cr/Au film of 100QX,
! Turns are formed to form the gate electrode I4 (a).

Next, a Lennost pattern having an opening is formed in the region including the dirt electrode 14, and the silicon oxide film 13 is removed by etching with ammonium fluoride to expose the a-St film 12 in the source/drain region (b). At this time, C
Since the c/Au film is not easily attacked by ammonium fluoride, the underlying silicon oxide film remains. Next, P-doped a
- Deposit the Sl film to a thickness of 1000X and use the dirt electrode 1
The source and drain contact electrodes 1s are self-aligned to the date electrode 14 using the step break at the edge of 4.
I, 152 c), P doping in unnecessary parts a
-81 film is removed by etching (d). Finally Mo/
Deposit 50 At films and form a pattern on all of them to form source, 1" rain and dirt extraction electrodes 16.
Form 163 (,).

According to this embodiment, since the overlap υ between the source/drain electrode and the gate electrode can be made zero, the parasitic capacitance between these electrodes can be minimized and the operating speed of the TPT circuit can be significantly improved. I can do it.

In addition, the source/drain contact electrodes can be easily self-aligned with the dirt electrodes by cutting the impurity-doped a-81 film, thereby making it possible to miniaturize and highly integrate the elements of the TPT circuit.

Note that the present invention is not limited to the above embodiments.

For example, instead of the a-81 film 12, Go+GexS11
-X.

It may be a compound such as S I z C1~X, and furthermore, Cd8, Cd's, Zn having a high specific resistance.
A semiconductor film such as S, Zn5e, etc., or a polycrystalline film such as Poty-St may be used. Further, the method for forming these semiconductor films may be any method such as suction, vapor deposition, or thermal decomposition. Further, the Y-to-electrode may be made of any conductive material as long as it can be used as a mask when removing the gate insulating film. The r-to insulating film is not limited to Sto2, but also 8
13N4 etc. may also be used.

The f-turning of the impurity-doped film 81 is caused by the source
It may be performed not only before but also after the drain and gate lead electrode wiring. In addition to the impurity-doped Me-81 film, other conductive films such as metal films can be used as the source and drain contact electrode materials. Furthermore,
After deposition, the *-81 film that forms the device may be turned so that it remains only in the device region. In that case, the final structure will be as shown in FIG. 5 compared to FIG. 4(e). Become.

[Brief explanation of the drawing]

Figures 1 to 3 are cross-sectional views of TPT with conventional structure, and Figure 4 (
a) to (a) are cross-sectional views showing the manufacturing process of a TPT according to one embodiment of the present invention, and FIG. 5 is a cross-sectional view of a 9-TPT according to another embodiment. 11...Glass, 12...Undoped a-Si film,
, 13...Silicon oxide film (insulating film), 14...Date electrode (Cr/Au film), 151.152-=source.
Drain contact electrode (P-dofa-Si film),
lJ, 16B... Extraction electrode (Mo/At film). Applicant's agent Patent attorney Takehiko Suzue 10- Figure 4 If 2 earthquake If! 31i'F (C)

Claims (4)

[Claims] (1) A process of depositing a semiconductor film on an insulating substrate, a process of covering the surface of this semiconductor film with an insulating film and forming a y-upper electrode thereon, and using this y-upper electrode as a mask to insulate the semiconductor film. A step of etching the film to expose the surface of the semiconductor film in the source and drain regions, and then depositing a conductive film to a thickness that creates a break at the edge of the r-to-electrode to form the source and drain contact electrodes. 1. A method of manufacturing a thin film field effect transistor, comprising a step of forming a thin film field effect transistor. (2) The method for manufacturing a thin film field effect transistor according to claim 1, wherein the semiconductor film is amorphous silicon or polycrystalline silicon. (3) The method for manufacturing a thin film field effect transistor according to claim 1, wherein the conductor film is a semiconductor film or a metal film doped with impurities. (4) The method for manufacturing a thin film field effect transistor according to claim 1, wherein the thickness of the conductive film is 1/2 or less of that of the insulating film.