JPS58186968A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing an f-to-MO8 type semiconductor device.

A conventional ssr-FMO8 type semiconductor device is shown in FIG. 1, taking an NMO8 structure as an example. In this figure, 1#'iP
type silicon substrate, 2 is the channel strug layer, 3 is the field 510m1! -4 is a source/drain diffusion layer, 5 is a dirt oxide film made of 5kis, 6 is an f-) electrode layer made of raised silicon, 7 is a PEG film, 8 is an At electrode layer, 9
is the source/drain contact portion.

FIG. 2 shows the dirt electrode layer 6° source of such a device.
FIG. 2 is a plan view showing the relationship between the drain diffusion layer 4 and the contact portion 9. FIG. In this figure, a is the contact margin with the field part (Feel PS 10ml [3 parts formed, 9 parts)], for example, if explained using the 3μ level design rule (the number #LFi shown below, all according to this design rule), it is 1~ It is 2μ. Maku, b is r-)
The contact margin with the part (r-toe electrode layer 6) is 2 to 4μ,
C contact size is 2~4J%d is f-) width (f-
(the width of the electrode layer 6) is 3J.

As is clear from this FIG. 2 and the above-mentioned FIG. 1, in the conventional device, the contact portion 9 is formed within the region of the source-drain diffusion layer 4. It was necessary to provide contact margins a in three directions with the field section. Therefore, the device area becomes large, which has the drawback of making it unsuitable for higher density. for example,
The dimensions e and f shown in Figure 2 are: e==d+2 (b+a+a) =3+2(3+3+1.5) =18μ f=2 m + c = 2 X 1.5 +3 =6μ, and the element area at the 3μ level is At least ・Xf=1
8X6 = 108μ3.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the contact margin with the field part to zero, thereby reducing the element area and increasing the density. With the goal.

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIG.

In FIG. 3(A), 11 is a P-type silicon substrate, and first, 5is for KLOCO8 on the surface of this substrate 110 is
After selectively forming the N4 film 12, ion implantation is performed to selectively form a channel stop layer 13 on the silicon substrate 11, and thermal oxidation is further performed to form a field 5ins film (field 5ins film) on the surface of the silicon substrate 11. Insulating film) 14
selectively formed.

Next, after removing the %811N4 film 12, the exposed surface of the silicon substrate 11 and the channel stop layer 1 are removed.
KSlot as shown in the 3rd H(B)K on the exposed surface of 3
The number of films is 5, and the number of films is 5, and the number of films is 5.
A layer of silicon 11116 is formed on the ns film 14.

Then, the polysilicon layer 16 and the 5ins film 15 are
? Make turns and leave them in f-) section O. The remaining raised silicon layer 16 and 5ill film 15 are the Kf-) bran layer 17 and the dirt oxide film 18, as shown in the third image (C).

Thereafter, ion implantation is performed using the gate electrode layer 17 and the r-) oxide film 18 as a mask.

As a result, the silicon substrate 11 and the channel stock 7
A source/drain diffusion layer 19 is formed in a part of the '1li13 as shown in FIG. 3(C)K.

Next, as shown in Figure 3 (CD), the silicon substrate ll
KPSGII (intermediate insulation II) 20 is formed on the entire surface. Then, on the source/drain diffusion 111e,
In addition, the end of the contact hole is designed to coincide with the boundary between the source/drain ore &1Ile and the field part (the part where field S10 snow l[14 is formed), and the contact hole 21 is formed with the thickness of the PSG film 2 by dry etching. 0 is achieved. The state of formation of this contact hole 21 is shown in the above-mentioned Figure 3 (D). However, [2] In this figure, the contact hole 21 is slightly shifted toward the field side, and therefore, a part of the field Slam film 14 is also etched, and the surface of the channel stop 113 is slightly exposed. .

Next, phosphorus ions are implanted through the contact hole 21. As a result, a diffusion li#22 having the same conductivity type as the source/drain diffusion layer 19 is formed in the source/drain diffusion N119 and the portion of the channel stop layer 13 corresponding to the contact hole 21. Thereafter, heat treatment is performed in N3 at 900° C. or higher. Through this heat treatment, annealing for crystallization of the diffusion layer 22 and its diffusion process are performed.
The junction depth of the source/drain diffusion layer 19 is made deeper (0.4 to 0.6 tones) (0.6 to 1.0 tones) as shown in FIG. 3(E)K. and a contact flow in which the shape of the contact hole 21 is made gentle as shown in FIG. 3(E) are performed simultaneously.

After that, an At electrode layer is formed by a conventional method (not shown).

According to this IIIO embodiment, the following effects can be obtained.

■ Form the contact hole 21, and then press this contact hole 2.
Since the ion implantation was performed through the contact holes 1 and 1, the diffusion layer 22 of the same conductivity type as the source/drain diffusion layer 19 was formed. Even if the source/drain diffusion layer 19 is shifted toward the field side, the source/drain diffusion layer 19 is diffused@
22, the contact hole 21 (contact part) is formed on the region of the source/drain diffusion layer (diffusion layer 2
2 is always located only in the source/drain diffusion layer (which can be considered as part of the source/drain diffusion layer). From this K, the contact margin with the field portion can be reduced to zero, and as a result, the element area can be reduced and higher density can be achieved.

To specifically describe the element area with reference to FIG. 4, e'=
d+2 (d+c) = 3+2 (3+3) = 15 μ f'=e = 3 μ. Therefore, the element area becomes very small as e'X f'==1 5 X 3=452.

(2) Since the contact region diffusion layer 22 can be made deeper than the source/drain diffusion layer 19, the series resistance value of the source/drain diffusion layer can be reduced. Furthermore, since the surface concentration of the diffusion 422 in the contact portion can be increased independently of the source/drain diffusion layer 19, the contact resistance value can be reduced.

■Ion implantation K is used to form the diffusion layer 122 in the contact area, and heat treatment is performed in Nl at a temperature of 900°C or higher. The twin contact and the contact 70-, which softens the shape of the contact hole 21, can be performed at the same time, simplifying the process.

In the first embodiment described above, the contact hole 2 is formed at the boundary between the source/drain diffusion layer 19 and the field part.
However, as shown in the second embodiment shown in FIG. 5, a part of the contact hole 21 may overlap the field portion in terms of design. Even if this is done, the above-mentioned ■, ■OO results are the same as in the first embodiment!
Obtainable. In FIG. 5, h is Fio at the 3j level, which is about 5 to 1 μ.

In addition, in the embodiment, the junction depth of the diffusion 1122 is
The drain diffusion layer 19 is also formed deep, but in cases where it is not possible to incorporate a pack bias generation circuit, or where a minute current generated due to a substantially narrow field area affects the characteristics of the device, the kit, diffusion layer 19, etc.
In order to bring the lateral penetration depth of #22 closer to zero, the junction depth of the O diffusion layer 220 is made shallower than that of the source/drain diffusion #19, as shown in Example 3 of the sixth factor. Good too. For example, source/drain diffusion 41 at 3μ level
The junction depth of 9 is 0.5μ, the junction depth of diffusion $22 is 0,
It is assumed to be 2μ. Note that even when the junction of the diffusion layer 22 is made shallow as described above, it is of course necessary to perform heat treatment after ion implantation. Depending on the a# and time of this heat treatment, or the type of impurity introduced, it is possible to control whether the junction of the diffusion layer 22 is made deep or shallow.

Therefore, in the case of the third embodiment, by making the junction depth of the diffusion layer 220 shallow to about 0.2μ, the diffusion N
The entry of l22 into the field part is 1110.1μ
It is possible to obtain the effect of reducing the size and the effects of (1) and (2) of the first embodiment.

As described in detail above, according to the method of the present invention, after forming a contact hole, ions are implanted through the contact hole. Since the contact margin with the field portion can be reduced to zero, the element area O can be reduced and the density can be increased.

Therefore, this invention is applicable to 81 f-tMO8! IV-
It can be used for LSI II manufacturing method.

[Brief explanation of the drawing]

Figure 1 shows a conventional Siff-)MO8N semiconductor device.
2 is a cross-sectional view showing the O8 structure as an example; FIG. 2 is a plan view showing the relationship among the dirt electrode layer, source/drain diffusion layer, and contact portion of the device shown in FIG. 1; FIG. 3 is a diagram showing the manufacturing of the semiconductor device of the present invention. A cross-sectional view for explaining the 10th example of the method, Figure 4 is a cross-sectional view for specifically explaining the element area.
FIG. 5 is a diagram for explaining a second embodiment of the invention, and FIG. 6 is a sectional view for explaining a third embodiment of the invention. 11... P-type silicon substrate, 14... Field s
iog film, 17...f-) electric II layer, 18... gate oxide film, 19... source/drain diffusion layer, 20...
...PSGI! [, 21... contact hole, 22...
・Diffusion layer. Fig. 1 Fig. 2 Fig. 3 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Procedural amendments September-3, 1980 Arrival of the Commissioner of the Patent Office 1. Display of the case 1972 Tatami H. Application No. 6, I 2, Issuing name: Shizuku et al., OSS construction method 3, person making the amendment Relationship with the case Akira Tatami Applicant (019) Oki Electric Works 1/a Ik Shikinsha 4, Agent 5. Date of amendment order: Showa year, month, day (true date) 6. Subject of amendment - face written by O - O detailed face 1 @IAo column 7, contents of amendment 345

Claims (1)

[Claims] selectively forming a field insulating film on the surface of a silicon substrate;
-) Forming an oxide film and r-) electrode layer, and performing ion implantation using the f-) electrode layer and r-) 11-oxide film as a mask to form a source/drain diffusion layer on the substrate. a step of forming an intermediate insulating film over the entire surface of the substrate; forming a field insulating film and aligning the end of the contact hole with the boundary between the field part and the source/drain diffusion layer by design to form a source/drain region; A step of forming a contact hole in the insulating film on the drain diffusion layer or by overlapping a part of the contact hole with the guard portion due to design, and implanting ions through the contact hole formed by this step. A method for manufacturing a semiconductor device, comprising the steps of: forming a diffusion layer of the same conductivity type as the source/drain diffusion layer on the substrate; and performing heat treatment after this step.