JPS58186963A - Programmable read-only memory and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates generally to semiconductor quadrigrample read-only memories (FROMs), and more particularly, to semiconductor quadrigrample read-only memories (FROMs), in particular, each FROM block has opposing diodes in the cell (one of these diodes can be selectively destroyed). BACKGROUND ART FROM is a row of memory cells that is becoming increasingly important in field-programmable electronic memory applications. and the types of PROs that involve arrays of columns are of great importance. The first of the diodes in each cell acts as an array element to electrically isolate the cells, while the third diode is selected to program logic into the cell. can be destroyed. Several prior art FRs using back-to-back diode structures destroy a programmable diode by passing a sufficiently high reverse current through its Phi junction, permanently shorting this junction.
In OM, electrically insulating materials such as silicon dioxide are used to laterally separate memory cells. British Patent No. 1,100,5079 ``Programmable Read-Only Memory Cell'' discloses a FROM as follows: According to this FROM, each array diode is a vertical diode, and its PM!!! , lying horizontally in a single crystal silicon region of the semiconductor body and completely laterally adjacent to a deep (or recessed) region of silicon dioxide within the semiconductor body. Each programmable diode is a polysyntal diode. The PN junction of each programmable diode is generally perpendicular to the lower surface of the semiconductor body. This FROM is fabricated by forming an N-type epitaxial layer on the upper surface of a P-type substrate and forming a P-type epitaxial layer on the N-type epitaxial layer. Each cell has a PM
An opening is provided through the insulating layer overlying the epitaxial layer. PM for programmable diode
The bond is deposited on the insulating layer and on the portion of the pitaxial layer exposed by the opening. - A relatively small current of about sO is required to program this FROM, which is formed in a layer of polycrystalline silicon;
The horizontal diode increases the cell area.Furthermore, during manufacturing, the properties of PM junctions in polycrystalline silicon are less controllable than those of PN junctions in votive crystalline silicon. etc. is Ta-Matsuba Patent No. 00
No. 18178 Specification 1 "Programmable Read-Only Device" discloses other such FROMs 〇This FR
In each memory cell of the OM, both diodes' P
The N junction is provided in the single crystal silicon region. Isolation regions comprising silicon dioxide immediately adjacent to the single crystal regions separate the cells. Each PN junction is approximately horizontal in the middle of its cell and extends to the upper surface of the single crystal region spaced from the sidewalls of the isolation region. The FROM, which laterally and upwardly surrounds the PM junction of the diode, is formed by selectively forming an N-shaped tube along the upper surface of the P-type silicon substrate, followed by a ◎Therefore, a lateral isolation region is formed, a P-shaded region is formed in the epitaxial layer on the tab, and an N-shaded region is formed in the P-type region. A set of PM junctions is fabricated at 0. In this FROM, a shallow region can be used to form the diode, but incorporating a diode within each cell (n@sting) is difficult due to photolithographic alignment tolerances. , the memory element occupies an area of about 9 square meters, which significantly increases the cell area. This increases the programming current. Additionally, the parasitic transistor operation while programming cells in - tubs increases the programming current. teeth,
Forward biasing a PI junction between a substrate and another tab along the same column to damage programmable diodes in cells along the same column in other tabs 0 Invention Disclosure Semiconductor Oxide A PRON formed in a semiconductor body having a four-shaped electrically insulating region and an adjacent single-crystalline semiconductor region, preferably comprising a four-shaped electrically insulating region and an adjacent single-crystalline semiconductor region, includes portions laterally separated from each other along the upper surface of the semiconductor region. FROM cells each having a substantially horizontal first PN in the semiconductor region.
junction and a corresponding second PN junction. These PM junctions together form a set of PN junction diodes in an opposing structure. Each second PM junction is approximately horizontal and has a corresponding second PN junction. Preferably, each first PM junction is provided in the semiconductor region such that the intermediate cell region between each set of PM junctions is completely adjacent to the insulating region. 1 applied for cell PN junctions
"Subhorizontal" means that each of these PN junctions lies mostly in a plane parallel to the generally planar bottom surface of the semiconductor body; upward (or Thus, each FRO
The diode on the cell side of the M cells is a vertical diode. The lower diode formed by the PM junction is an array element, while the upper diode formed by the first PN junction is a programmable element.0 By having a PM junction completely adjacent to the isolation region in each cell, This PRON will occupy a very small space. The memory elements in each cell are typically about 8.
It measures 85 square meters and occupies the area of Tallinn.

This area is significantly smaller than in comparable prior art devices. The maximum dopant concentration in each intermediate region is at the midpoint between the PM junctions in the set, optimally at the midpoint between the PM junctions in the set. This dopant state, achieved by near zero ion implantation, facilitates FROM fabrication and improves programming operations.

The lower cell region directly below the JPN junction is of a first conductivity type, and the intermediate cell region is of an opposite third conductivity type. The cells are typically formed on the substrate region of the twenty-fourth electric hair. This gives rise to the following potential gap. That is, the substrate region acts as the collector of the parasitic transistor, the lower region of each cell acts as the spacer, and the adjacent intermediate cell acts as the emitter. This cell number! When the PN junction is destroyed,
That first JPN junction becomes forward biased, which turns on the associated parasitic transistor. The current injected into the substrate region by the parasitic transistor creates a significant voltage there, causing the same column to turn on. This causes the PM junction between the substrate region and the lower cell region of other cells along the line to be forward biased. This degrades the zPN junction of these other cells. Proper use of composite buried layers to alleviate this problem and
An intermediate electrical connection to the lower cell area can be provided.

The buried layer has a plurality of highly doped buried regions of a first conductivity type directly below the lower cell region. Each buried region is formed by contacting the insulation region with an adjacent insulation region along the entire lower edge of each of the - or more associated lower cell regions. , the amplification of each parasitic transistor can be reduced considerably, typically by a factor of 1/l 000. As a result, the voltages built up in the substrate region during programming of - cells are considerably reduced and the same The O composite buried layer, which can protect the putagrample diodes in other cells along the column, consists of a highly doped buried web of the second conductivity type (w@
b). This buried web provides a low resistance path to remove charge carriers injected into the substrate region by parasitic transistors during programming, further preventing the substrate potential from building up. This lightly doped region, which is laterally separated from the buried region by a lightly doped region extending partially into the insulating region, serves to increase the breakdown voltage of the substrate PN junction to an acceptable value.

An important advantage of this memory is that it is less susceptible to many material defects and defects that occur during the process; only the area of the actual memory element of the multicell is significantly susceptible to such defects. This region is very small. Connections extending through the insulation layer to the synthetic buried layer are not very susceptible to many of these defects, and many of the PM junctions are insulated, so this PROM is It is very suitable for building large memory arrays.

In the fabrication of a FROM, an insulating region is first formed by forming a monocrystalline portion of a doped region of a first conductivity type spaced apart from each other along the top of the doped region. be completely adjacent to all lateral boundaries of each of the sections. A dopant of the second conductivity type is introduced into the single crystal part through the top surface to form a first PM junction.@By introducing a dopant of the first conductivity type into each single crystal w6 through the top surface in the same manner. , using the insulating region in which the eighth PN junction can be formed as a mask, dopants of 0jlss conductivity type are ion-implanted to control the lateral spread of these dopants in each single crystal part, and PROy Synthetic buried layers and insulation can be annealed at sufficiently low temperatures to repair lattice defects due to the introduction of dopants without significant redistribution of the dopants or other impurities originally introduced into the FROM. The regions refer to impurities in the 0-1 conductive pattern, which are usually formed in the W stage of FROM manufacturing, at a plurality of first positions spaced apart from each other along the surface of the substrate.
an eighth conductive layer laterally surrounding each of the first positions and spaced apart from each of the first positions;
An epitaxial semiconductor layer is then grown on the surface of the substrate, preferably similarly arranging the embedded web by selectively introducing impurities of the first conductivity type into the substrate at the 0 position. A web-like portion of the epitaxial layer is removed along its upper surface to form a groove. The substrate and the remainder of the epitaxial layer are then selectively electrified in a high temperature oxidizing atmosphere. A portion of the epitaxial layer along the trench is oxidized to form an insulating region, and a portion of the impurity introduced into the substrate is diffused upward within the epitaxial layer to form a synthetic buried layer.0 Description of a Preferred Embodiment FIG. 1 shows a cross-sectional arrangement of a preferred embodiment of a FROM containing some identical FROM cells, each consisting of a - pair of back-to-back oxide wall vertical diodes.
8a and 8b are mutually perpendicular cross-sectional views of the embodiment of FIG. 1, showing the structure of PROK in a semiconductor body with a flat bottom lO; As shown in FIG. 1, the cross section in FIG. 1 is a plane 1-1 parallel to the acid part surface 10. The elements indicated by broken lines in FIG. 1 are plane 1-1.
It is below. Terminology ``lower emotion'', ``bottom part'', ``upper ['', ``
Top”.

``Downward'', ``Upward'', ``Mounted'', ``Horizontal'', ``Horizontal''
OFROM cells are arranged in a row and column arrangement, where the 0th row is
It is about 20 ikrons away.

6 PRO1lk l gB, 11D, l m,
, 111B'.

12()', l! y°, is shown in Figure 1 T0 cell x
gB, 11D.

1m is in the -”) line, * k l MB”,
1 gO' +121° is in the adjacent T row 0 Thus, each subscript ``''B'', ``'D'', or @1'' indicates an individual column, and the undashed sign is the sath
wlJ shows T rows, and dashed symbols indicate adjacent rows. 0 middle columns - some of the regions T located in the center on these middle column regions, and the corresponding subscripts. ◇ Subscript “B” is indicated by reference signs including “M1.”’0”, “Excuse”, °G”.

1 mB of cells distinguished by D", t or F",
12D, 1 m, , 11B'', l lD'
, 1 m,' - any one of those elements or separate column elements.

Or the reference sign is the subscript “mu”, ’0”, ’雛”.

For any item in the area containing “G”, the 11th character “M”
The "G" and primed numbers are shown in full in the drawings, but are omitted from this detailed description. Additionally, some elements of cell 111 are not shown or only partially shown to avoid over-representation. For example, only the elements of cell 11p are shown completely in Figures 11114wI and sb. A cell 13 is formed in the doped single crystal silicon region of the body at the upper surface 14 of the single crystal region.

Web-like recesses 11g of silicon dioxide selectively sunk into the body along the surface 14 are laterally separated from each other by adjoining portions of the insulation region 16. . The single crystal region in FIGS. 2a and 2b is an oxide isolation region 16 on the opposite side of cell 1g along row 0, which is the part between surfaces 10 and 14 containing: The center-to-center distance is also approximately 11 microns. The oxide region 16 has a bird's beak-shaped portion 18□. This part goes into the single crystal region, and each cell R11l, about 14! It is narrowed along the surface opening to a cross-sectional area of i square microcircles.

The lowermost surface of the densified material region 16 is separated from the upper surface 14 by 1
It is located at a distance of approximately 1.1 tchron within the main body.

Each cell 13 is composed of a lower array diode and a programmable diode. The O array diode is a vertical PM junction element formed by a lower @N area O and an intermediate P area g3. 0 These common interfaces form a first PN junction 36 with a lateral area of about 4 square meters and a breakdown voltage of about 16 volts.
The O programmable diode is
and an upper I+ region ss. These common interfaces are the first PM junction 80 with a lateral area of about 8 microns squared and a breakdown voltage of about volts. The area of junction s6 greater than 0, which is due to the large penetration of the beak 18, is the O P region which acts to prevent the deterioration of the junction 86 when the programmable diode is programmed. gg is completely adjacent to the recessed sidewall of the insulating region 16, so that PM junction 3 and SO are completely adjacent to that sidewall, as in f4. PN junction 16t or δ0 is horizontal for most of its extent. Yes, but.

Generally, it curves upwardly adjacent to the sidewall of oxide region 16. Since the center of each joint 1611 or 80 is parallel to the lower surface 10, there is very little portion of the joint 36 or 80f) that bends upwards.

Junctions s6 and δO can be assumed to be "subhorizontal", so that the maximum concentration of P-type dopants in the %P range g2 is determined by the junction j! Where the maximum P-type concentration occurring between 6 and 80 (rather than along the junction 80) lies within the intermediate region s8, from the midpoint between the junctions 26 and 80 to the junction s6 and 80. The maximum P-type concentration is at a vertical distance less than 20- of the distance between the junctions s6 and 80! Optimally, it should occur somewhere in the middle. Using such a dont distribution to the extent that regions 110, 131, 318 are considered to be NPN transistors with permanently floating (unconnected) bases makes potential transistor operation very inefficient and T This is because the intermediate region sm is wider than the base of an ordinary transistor, so the current gain is very small (approximately S).
PROMf:I in this Dono-kun F distribution Gt large array
Make it easy to do I*. The reason is that the oxide region 1
This is because there is a high NP-type dopant concentration along the mae of 6 to reduce the possibility of shorting due to reverse, shunting or other defect mechanisms. The lower part of the structure, formed as the upper part of the structure between which electrical connections must be made with the row lines of the FROM, is partially formed by a lightly doped P-type semiconductor substrate. In the absence of a buried layer with very highly doped MW and PMI regions, each P region 3m.

Vertical parasitic PNP) works as a power plant ivy for Tunjista. The base of this transistor is the adjacent y-region go, and its collector is the remaining lightly doped P-type part of the substrate.

When programming a cell, there may be times when a column is accidentally filled with N.
The potential of the + region 8B is increased by increasing the potential of the column line connected to these I+ regions 3s. When any particular cell 1m, such as cell l ID, is programmed, its PN junction 80D avalanches to its p-region s3D, and its PM junction s6D to be forward biased. This forces a current to flow through the parasitic PN associated with that cell 1gD.
P) The transistor can be turned on. The base-collector junction of this S-lateral parasitic transistor is the base-emitter junction of a lateral parasitic NPN transistor. The base-collector junction of this NPN) transistor is connected to the remaining lightly doped P-type substrate portion and to any other cell 13 along the same column, such as cell 11p'.
0 parasitic PNP formed by the N region sO of I)
Once the transistor is saturated, its base-collector junction becomes forward biased, raising the substrate voltage and turning on the lateral NPN transistor. This lowers the voltage in the %N- region 10p' to near the voltage in the N region 110H, and lowers the PN junction 80D'. The reason is that the %M" region g8D' is in the N+ region $
Because it is at the same potential as 8D oW! Then, the action of the parasitic PNP (T) associated with each programmed cell 18 is:

Using a zero composite padding layer with cell 11 that could damage the programmable diodes of other cells 1m along the same column eliminates this problem, providing intermediate electrical connections to the word twins, and reducing electrical connections between rows. Insulated giving.

A portion of this composite buried layer consists of a set of buried C regions ms that lie directly below T of the lower 111M region go and are in contact with the lower surface of the oxide region l. It is particularly preferable that region (or tub) 1 snow is continuous with one of the lower regions sO. However, in order to simplify the drawings, in Figure 1, Figure 3a, and Figure 8b, Each tab is shown so as to be continuous with only the two tabs aS @ and SO below ◎For example, the embedded area 810 is
and l 00 so that 81 mouths are continuous to T 00, so that the insulating area 16 that extends θ to the entire lower edge of the lateral shoulder circumference of each lower 1lIilI region SO continuous with the mercenary tab
The average net dopant degree in the adjacent buried region 8s is.

Approximately 1,6 x 10” atoms/a II ◎Lower region 1
j is.

It has a relatively uniform net dopant concentration of about 8 x 1 G" atoms/ad. This once the layer 181 is in the chemical region 16 and 1.0 microns downward from the surface 14. The concentration of these tabs 82 is the same as that at the point where the tabs 82 descend to the position and touch the area 80.
It extends approximately four arcs downward into the body.

Each tab δ2 extends into a low-doped P substrate habitual region 84 with a lower surface 10 and a normally reverse biased portion M PH7
The OP area 4 where 77 and 86 are formed is about IXI.
It has a relatively uniform net dopant concentration of G atoms/d. This concentration is the same as the N-type dopant concentration at the point where the 1 m thick region 8 descends to the bottom along the minute junction δ6.

The base of the transistor is a parasitic PNP that can be turned on during programming.
This is a collector junction. Each embedded region δ3 is the FfiI! of the associated cell ls! Being completely adjacent to the oxide region 16 at I, the N+ tab δ8 forms the base portion t' of the parasitic PNP transistors. This reduces the II current amplification of those transistors to approximately 1
0 to about 0.1.

When one of the cells 111 is programmed, the reduction in amplification reduces the voltage that can build up during substrate area heating, thereby preventing degradation of the programmable diodes of other cells 13 in the same column. 0 Each embedding area 8m consists of lower M+cover 40 and upper C area 4s
The combination of C regions al and δ8 makes the necessary intermediate connection between the lower cell region 30 and the row twin. The high doping in region δ8 serves to reduce the series resistance between its connection region a8 and its lower cell region SO.
◎The other part of the composite buried layer is placed on each side of the M + surface area g. An embedded P web 44, which surrounds the oxide region 1, adjoins this oxide region 16 along the lower surface of the oxide region 1 and extends upwardly along part of its milliliter. The average net density within the P+ web 44 present is approximately FXIO'' atoms/cII.
is approximately 1
It has a net dopant concentration of 0” atoms/cd.

On the other hand, its P-type dopant concentration is about 8.
A plurality of low resistance P regions 4 extending in columns in the O PROM are reduced to a dopant concentration of 5 microns below the substrate region 84.
6, the P+ web 44 is connected to the surface 14 by the insulating region 16 and the recessed surface 44 is combined with the connecting pin 6 to connect the cells 1m of each tab δ8 to all other tabs δ3. There is an electrical current of 1@T from the cell 11 in the lateral direction.

Therefore, this combination divides the rows horizontally from each other by 11
Tru. The web 44 in combination with the connecting region 46 has t!
Ta. Provides a low resistance path to remove holes filled during programming of the cell by the PNP parasitic collector region δ. This means that programming one cell 1m will cause other cells 1m along the same column to Prevent the programmable diode inside from being damaged.

By means of an enhanced low-doped region consisting of the P substrate region δ group and a corresponding epitaxial NII castle 48 existing between region No. 8 and the lower surface of the fist compound region 16.

Each embedding area 83 is divided into 11 parts in the horizontal direction from the spot ep 44.
TRUON region number 8 is approximately ・XIO” atom/−
oPd having a relatively uniform net dopant of
The low doping combination of Castle B4 and MIll region number-7 has a substrate portion sm of 8° with a sufficiently high breakdown voltage (typically about 8°
The arrangement of conductors in contact with multiple single-crystal regions extending on the upper surface 14 ensures that PROM 5! I'm afraid.

A layer of platinum-nickel silicide (10I) is provided on each surface area 6, and a layer of titanium-tungsten (5 m) is provided on the ml compound. Approximately IIs on I+Koseong s8 and 4s along table 1m14 and on titanium-tungsten region 6s
lead ms4 made of aluminum with silicon
Provide a pattern. Lead @ Is 4B, Is
4p, I 41 HaJll? 4 n”e44
゜The gl that is 1llH in the in which is done with JIIS 4゜
With the exception of 4, all other leads 54D extend across the rows as shown by lead #154D in FIG. hand.

Form row lines to complete the conductor arrangement. This second crossing pattern of the leads is the *0 lead wrapped I! which is not shown in Figure 1 to avoid clutter. When using one pattern, phosphorus doped silicon dioxide (VaPOX) (7
) layer is provided over the lead wire 4 and the portion of the oxide region 16 between the leads 54. The intersecting pattern of leads consists of pure aluminum overlying the vapox layer;
Lead M54 and its counterpart are closely read by an aluminum-filled passage extending through the apox layer.

In order to program the FROM, a reverse current of approximately 0m should be applied to each PM junction 8o to break the current T0, e.g. % junction δoDt, and an appropriate reverse voltage typically 1 micron. Aluminum at about 577° C. is supplied between leads #B40 and s4D for a suitable time period less than 0 to cause avalanche breakdown in the programmed pull diode and generate a specific reverse current. The progeramal diode is heated until the silicon eutectic temperature T is reached. At this point, the aluminum from lead wrap B4D moves through the N+ region s8 and the pH
Since it forms an ohmic contact with the l-region Imp, the program pull diode is shorted. This will depend on the convention used (OOnventiOn).
0, which places a logic “O” or logic “1” in the ID;
The cell 12 whose programmable diode is held constant is in the opposite logic state 8th aPI! J
~An Figure 1171. 1st & lQ, lllMbf
The manufacturing process of ilJ's FROM is shown below. In the manufacturing process, boron is used as a P-type impurity to form a large number of P-conductivity type regions. Unless otherwise required, boron is often ion-implanted into B. Phosphorus.

Arsenic, antimony are selectively used as complementary MH dopants. Unless otherwise requested, these should be P”, A
Ion implantation is performed in the form of 8b+.

Other suitable impurities can also be used in place of these dopants. Many ion implantation processes use various cleaning and photoresist masking techniques to introduce impurities into the wafer and create various isolated P-type and N-type regions. For ease of discussion, the cleaning process,
Steps involved in forming a photoresist mask;
and other such well-known steps in semiconductor technology are omitted from the following description. Unless otherwise required, each silicon dioxide etch is performed with a buffered etch consisting of about 1 part 40147 ammonium fluoride and about 1 part 49-hydrofluoric acid.

The first step of the process is sM” area 8s and P+ web 4
4. locating a composite placement layer consisting of 4 and 4. In Figure 8a, the starting material is 7 to 11 g.
- This wafer is a semiconductor wafer having a P single crystal silicon deposit 6o with a resistivity of about 800 microns and a thickness of about 800 microns. 100% in an oxidizing atmosphere of hydrogen and hydrogen.
Placed at 0°C for 60 minutes, approximately 1.8 micron thick II
A layer 6jlt of silicon dioxide with t is grown along the upper surface of the substrate O. A photoresist film having an opening above the area 8s and the position planned for the web 44.
A film 64 is formed on the six oxide layers. oxide layer 6
Etch the exposed part of 8 for %lI minutes and
After removing the T0 mask 64, leaving a 100-1400 org. thick silicon dioxide in the open area of the
MaOOO has a nominal thickness of ondus seam and #1s3
Non-critical (non,
oritioal) Photoresist mask 66t,j
[Im) Etch the remaining exposed portion of the oxide layer 6g on the top surface of the wafer for 8 minutes as shown at 511 to remove it as appropriate. Antimony is implanted through the mouth area in the remaining part of the oxide layer 63 to form the N++ region 6.

After removing the mask 66, approximately g.
Position the depressed area on the exposed area of the substrate 60 by growing a layer of silicon dioxide having a thickness of ooo angstroms. Form O. The high concentration during this step also pushes the antimony in region 68 further down (
and transversely) into the substrate 60 ◇l, it is a non-critical 7 otregis) with a nominal thickness of 100 μm and a web-like opening on the predetermined position in the inset web 44) - the master 4 is moved into the substrate 60 of the wafer. form on the top surface. The remaining exposed portion of the oxide layer 6s is removed by etching for δ, S minutes into the silicon substrate 60. Mask placed in the correct position? 4, boron is implanted into the substrate 6° at a dose of jiXlG ions/− and an energy of 180 K6V to form a P+ bond region 76.

After removing the mass number, process the wafer for so minutes and #! As shown by δdi, the #-coated initial layer 7B and the remaining portion of the oxide layer 6s are removed.

A bulk doped epitaxial layer γ8t1 with a resistance of about 0.7 Ω-1 is formed by the well-known Siten process.
II. Approximately 1. Then, the oxide region 16 is formed to a thickness of about 800 angstroms. A layer 8o of nnealed silicon is grown along the upper surface of the epitaxial layer 8. This is grown in dry oxygen at 1
This is achieved by holding the wafer for 1 minute. Approximately 111
A layer 8s of silicon nitride having a thickness of 100 Å is then deposited onto the compound layer 80 according to a conventional low pressure chemical vapor deposition process.
110fiW in wafer oxygen and hydrogen at 1000℃
A thin layer 84 of silicon nitride is formed along the upper am plane of the nitride layer 8s. *Layer each positioning subsidence part 0 as shown in 5aritt! 8. - Forming a photoresist mask 86 with web-like openings corresponding to 0° positions on the #I compound initial layer 4; oxide layer 84
The exposed portions are removed by etching for 1.6 minutes.

After removing mask 86, the exposed portion of eighth e layer 78 is etched down approximately 6500 angstroms to form $87 by etching with hot 165 DEG C. phosphoric acid for 50 minutes. This consists of 250 parts of nitric acid, 40 parts of 49% hydrofluoric acid, and 1 saturated with iodine.
000 parts of acetic acid for 5 minutes at 28°C.

By placing the wafer in hydrogen at a depth of 1000" for δ6°, an insulating layer 16 having a depth of about 1.g fi (cm) is deposited at #$87 as shown in FIG. 8f. Since the 0 oxide region 16 that is formed does not extend into the substrate 60, the portion 48 of the H epitaxial layer 78
It is located directly under the lower surface of oxide region 16. During this high-temperature process, boron in the region 1 is diffused downward in the substrate 6G and upward in the epitaxial layer 78, and
Similarly, the antimony in region 68 extends downwardly into the substrate 60 to form a P+ web 44 extending to a length of 6 mm.

Diffuse into and above epitaxial layer 78.

C-buried region 8slf forms 0°, in particular, the part of the lower side of the oxide region 16 above the tab δ8 is approximately 10° lower than the part of the lower side of the area 16 for a 1 positioning depression) 0
00 ounces low. The embedded reef area δg is @ area 16
ms of the lowest axis of T.

The remaining N-type portion of epitaxial layer 78 lateral to oxide region 16 is removed from cell 11 and connection region 88.
and 46. Each of these N-type monocrystalline portions intended for cell 1m has lateral dimensions of about 8 microns×spocrons, similar to the bird's beak portion 1B.

The remaining portion of oxide layer 84 (which grew slightly during the previous high temperature step) is removed by a 1.5 minute etch, as shown in Figure @8g. Similarly, nitride layer 82
The remaining portions are removed by etching with hot am at 165° C. for 86 minutes. The remaining portion of oxide layer 80 is also removed by a 1 minute etch. An electrical@edge layer 88 of silicon dioxide having a thickness of about 1000 angstroms was applied by placing the wafer in #I element and hydrogen at 900° C. for 26 minutes.

Grown along exposed portions of epitaxial layer 78. Since this oxidation is carried out at relatively low temperatures, there is no significant redistribution of impurities in the tab δ8 and web 4. The formation of the embedded region δ2 and the embedded web 44 is very complete.

Next, the connection areas 88 and 46 and the transistor are arranged in one peripheral circuit. Form a non-critical photoresist mask 90 on top of the sea urchin IS with a nominal thickness of approximately 8000 Å and an oven space above the intended location of the connection area δ8. layer 8
Cover the exposed part of 8 with snow.

With the mask 90 in place and removed by etching for 30 minutes, phosphorus is implanted into the exposed portion of the epitaxial layer 8 with a dose of JIXIG ions/C- and an energy of 180 [eT/] to form the C region 98. After removing the mask 90, the web S is annealed in nitrogen at 1000° C. for 120 minutes to repair lattice defects. Next, sea urchin I. was incubated at 90 G°C and in hydrogen at 81
A layer 94 of silicon dioxide having a thickness of about 1400 angstroms is grown on the exposed portion of epitaxial layer 8 as shown in the eighth hFIJ for 1 minute. During this oxidation step, the thickness of oxide layer 88 increases by approximately 1000 Angstroms. The phosphorus in region 92 redistributes, causing them to extend downward, and the boron in web 44 diffuses slightly upward. During these processes, significant redistribution of antimony within tab 83B occurs. A photoresist mask 96 with a nominal thickness of 2 microns and an open space above the location intended for the P+ connection region 46 is formed over the top of the uninot. Boron is implanted eight times into the lower portion of epitaxial layer 78 through the exposed portion of oxide layer 88 with mask 96 positioned at an angle that is non-critical to region 46. .

A P+ region 98 is formed. The first implant was performed with a dose of 1X10" ions/C- and an energy of 180 KeV, and the eighth implant was 1,6 X 10" ions/ci
dose and 7! l KeV energy. These 8 boron implants are also %NPN in the peripheral circuit)
Form the desired impurity distribution for the transistor base and PNP) transistor emitter and collector.

After mask 96 is removed, a photoresist e-mask 10G having a nominal thickness of 500 angstroms and an upper opening at the location intended for connection region 88 is formed on top of the uninot as shown in FIG. mask 100
is non-critical for region 88. 11 compound layer 9
4 is removed by etching for 4 minutes. first l
x 10”” ion/cj dose and 180 [
Arsenic is deeply implanted with an energy of 67, and the mask Root
remove, dose of s×101″ ions/ej and s o
N+ region 43 is formed in the upper portion of region 92 by shallow implantation of arsenic with an energy of
These three arsenic implants also reduce the amount of NPN (npn) in the peripheral circuitry.
A desired impurity distribution is formed for the emitter of the transistor.

The wafer is annealed in nitrogen at 1000° C. for 60 minutes to repair implant lattice defects and redistribute arsenic and boron within regions 48 and 98. As shown in Figure 8j,
Area 481 is moved downward. The boron in the embedded web 44 is spread outward slightly, and the region 98 is moved downwardly into contact with the web 44 to form the P+ connection region 46. The regions δ2 and 9g are also slightly Growing zero order, forming a diode in the cell 12T01.8
A non-critical photoresist mask 10M with a nominal thickness of 100 nm and an opening over the location intended for the cell 1s is formed on the top of the wafer and the exposed portion of the oxide layer 88 is exposed for 5 minutes. The epitaxial layer 78 is etched.
Boron was removed by a mask 1011 arranged at an Oa cutoff of 8.5 X l Oin/cd.
(7) Implant into epitaxial layer 78 with a dose and energy of 110 KeV to form PN junction 86; Next, in the same way, arsenic is added to 6×1O ions/C-
dose and 50KI! implant into the epitaxial layer 8 with an energy of It is also useful as a mask to control the lateral spread of δ0. These two implants form a C region 82 and an N+ region gsf.

After removing the mask 102, the lattice defects caused by the implantation are repaired by annealing in nitrogen at 950° C. for 6 minutes, in oxygen for 25 minutes, and again in nitrogen for 5 minutes, forming regions SS and g8. Tru0 This annealing is area 2! ! and j18f, @8, extending slightly downward to their Il member position, as shown in the figure.
This leaves the regions 1 and 9m as the remaining part of the N epitaxial layer TE8 in the cell ljl, so that the regions 98 contact the buried region s8 with which they are associated.
They extend slightly downward to their final position in region 40. Similarly, regions 46 are moved slightly downward to their final position during the sharpening process by approximately 100 m.
layer 1 of silicon dioxide with a thickness of angstroms
04 is grown in areas s8 and 4m of exposed silicon along the top of the wafer.
Completed production of 8jP and 46.

The fourth surface determines the final dopant concentration in either cell 18.
middle upper surface 14 (located on the lower side of @kayu layer 104)
Shown as a function of depth downward into tab 88 from T o
IN 4 diagrams are, for example, 1. Surface 1b in @sag1
, sb or along a similar plane in the δkFItJ.
0th 4b, which is related to the dopant concentration of the M ll element and the junction position! As shown in A, the maximum hole l/A in each P@region sg is equal to its PH at their final position.
＠＠The one between za and 80 □occurs approximately in the middle 〇Next, the wafer has a region θ at the top of the wafer■.

42.46, a non-critical photoresist mask 106t having an opening over the OP+ region 46 to form a conductive lead in contact with 46, a zero oxide region 88f formed on top of the wafer; * After removing the O-q':AlI O6 by etching for 30 minutes down to region 46, approximately 850 angstroms of platinum with -Vf containing 60% nickel is deposited on top of the wafer by conventional sputtering techniques. (deposit on the surface)
Tru. The wafer is then sintered at -76 DEG C. and the platinum/nickel deposited on the exposed silicon in the connection area 46 is replaced by a layer of platinum-nickel silicide b as shown in FIG.
Convert to o. The platinum/nickel that has not been converted to silicide is removed by etching with aqua regia. A layer of titanium-tungsten approximately 1000 angstroms thick is deposited on the composite top of the wafer. A layer of aluminum is then deposited onto the top of the wafer, which is deposited on titanium-tungsten, to a thickness of approximately 1000 mm. Photoresist+1 mask 1G8t-, where the polymerized photoresist overlaps region 46! Form on the top of the ha. The exposed aluminum is etched away with a conventional aluminum etchant to remove the aluminum region 11O and the resulting exposed titanium-tungsten.

Etch with hydrogen peroxide to leave titanium-tungsten layer 52.

After removing the mask 108, a non-critical photoresist mask l 111 t with polymerized photoresist overlying the composite sandwich structure in the area 50.51° 11O
"b. Form on the top surface of the wafer as shown in FIG.

It was removed by etching for 1.7 minutes with a buffered etchant consisting of 1 part 40% ammonium fluoride and 1 part 49% hydrogen fluoride.

N+ regions 28 and 48 are exposed.

After removing the aluminum layer 110 using mask L12, deposit a layer of aluminum containing 1% silicon on the top of the wafer to a thickness of 7000 angstroms by etching the aluminum layer 110 overlapping the overlying regions 318 and 42. Form a photoresist mask 114f on the aluminum layer with photoresist and then pattern the aluminum layer by removing the exposed aluminum by etching with a semi-aluminum etchant as shown in FIG. l
Form m54. Next, remove mask 1.16 and
Forming the structure shown in Figure 2a (and Figure 2b)
Applying the layer in a conventional manner This is accomplished by depositing a layer of yapox to a thickness of approximately 9000 angstroms on the top of the wafer, using a separate photoresist mask. Etching the passageway to the selected one of the leads $964,
Deposit a layer of pure aluminum over the yapox and selected leads 4I54, and then deposit another layer of photoresist.
The aluminum layer f i is turned using a mask to complete the FROM. Although the present invention has been described with reference to a specific embodiment, it goes without saying that the present invention is not limited to the embodiment. For example, the connection area for the synthetic buried layer could be placed after the cell diodes in the FROM cell are placed. Alternatively, the connection region for the synthetic buried layer and the diode for the FROM cell can be placed by using a similar implantation/extension process instead of the materials and dopants mentioned above. Materials and dopants of opposite conductivity type can be used. Therefore, it is apparent that various changes and modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.

FIG. 1 is a cross-sectional arrangement diagram of one embodiment of the PRON of the present invention, and FIG. ga and FIG.
A line sectional view and a gb-ab line sectional view.

8a to 8n are cross-sectional views showing each step of the manufacturing process of the embodiment of FIG. 1, and correspond to the cross-sectional view of FIG. 2a.

FIG. 4 is a graph showing the dopant concentration of a typical FROM cell of the present invention. 26...1st PM junction '2B...Upper N+ region 0...35th PN junction 8 layers...
・Embedded area δ6...min 111PN junction 88...
・Synthetic C area 40'...lower-N+ area 1t...
Upper fjIAN+ area 44...P Web 5
0...Platinum-nickel silicide 5 layers...Titanium-tungsten layer 54...Lead heel 60...P single [& silicon wafer

Claims (1)

Claims: L A programmable read in a semiconductor body comprising a recessed electrically insulating region and an adjacent single crystal semiconductor region having an upper surface in which a group of programmable read only memory cells is provided laterally separated from each other. a dedicated memory, each programmable read-only memory cell having a first substantially horizontal PM junction in the semiconductor region and a corresponding spN junction;
@4, the PM junctions forming a set of PM junction diodes connected to each other in an opposing configuration, each third PN junction being substantially horizontal; A programmable read-only memory O 1 characterized in that an intermediate region common to each set of diodes above the corresponding JPN junction and between the PM junctions is completely adjacent to the insulating region. The programmable read-only memory according to claim 1, wherein each of the z-th PN junctions is provided in the semiconductor region. A programmable read-only memo 90 table characterized in that the maximum net dopant concentration in each intermediate region occurs below the m-th PN junction in the programmable read-only memory of claim 8. programmable read-only memory in which the maximum net dopant concentration in each intermediate region between the PM junctions of the set is less than 80 degrees of the distance between the PM junctions of the set. A programmable read-only memory characterized in that it occurs at a vertical distance from an intermediate point. 4 Claims 1, 2, 8 or 4
In the programmable read-only memory according to item 1, each of the first PM III groups is an array element, and each of the first PM
Connecting prodara! Programmable read-only memory characterized by having a pull element ◇ a. The programmable read-only memory according to claim 1, wherein the insulating region is made of a semiconductor oxide. 0 - Claim 1, 3, 8 or 4
3. The programmable read-only memory of claim 1, wherein each programmable read-only memory cell tapers laterally toward the upper surface. In the programmable read-only memory according to claim 1, claim 3, or claim 8, the upper boundary of the lower region of the first conductivity type in each programmable read-only memory cell is connected to its JPM junction. forming a plurality of highly doped buried regions of said first conductivity type laterally spaced from one another and each reaching at least one of said lower regions upwardly in each associated lower region; A programmable read-only memory according to claim 8, characterized in that: A programmable read-only memory characterized in that the average net dopant concentration in the buried region is on the order of at least three times greater than the average net dopant concentration in the lower region. A programmable read-only memory according to claim 9, having a plurality of similar connection areas of a first conductivity type, each of which is connected to a separate embedded area of the embedded areas. A programmable read-only memory according to claim 10, characterized in that the programmable read-only memory O IL extends from the upper surface to the upper surface. A programmable read-only memory according to claim 11, characterized in that the embedded web laterally surrounds each embedded region. continuous with the embedded region and the embedded web and extending along their entire lateral circumference to the insulating region, separating the embedded web from the embedded region. A programmable read-only memory O1 according to claim 111, wherein the average net dopant concentration in the embedded web and the buried region is equal to the average net dopant concentration in the lightly doped region. A programmable read-only memory according to claim 18, characterized in that the at least one connection area of the second conductivity type is at least an order of magnitude larger than the A programmable read-only memory extending from an embedded web to the upper surface. 1 & L having a recessed electrically insulating region and a group of programmable read-only memory cells laterally separated from each other. a programmable read-only memory in a semiconductor body comprising: an adjacent single crystal semiconductor region having a side surface;
Each programmable read-only memory cell includes a first substantially horizontal PN junction in the semiconductor region and a corresponding second PN junction in the semiconductor region.
N junctions, the PN junctions forming a set of PN junction diodes connected to each other in an opposing configuration, each second PN junction being substantially horizontal; an intermediate region common to each set of diodes between the corresponding JPN junctions is completely adjacent to the insulating region, and each first PM junction is located in the semiconductor region; introducing a semiconductor dopant into a first region of the semiconductor region through a top surface of the semiconductor region to control the lateral in-extension of the insulating regions; A method for manufacturing a programmable read-only memory, characterized in that the method for manufacturing a programmable read-only memory according to claim 15 is characterized in that the step of introducing the A method of manufacturing a programmable read-only memory comprising the step of implanting a dopant at an energy sufficient to cause the maximum concentration of dopant in each intermediate region to reside halfway between the PN junctions of the set. 1? , Particularly in the method for manufacturing a programmable read-only memory according to item 15, in which the dopant in each intermediate region is
Manufacturing a programmable read-only memory comprising implanting a dopant at an energy sufficient to cause the set of PM junctions to be present at a vertical distance from a midpoint between the junctions that is less than 80 mm of the distance between the junctions. Method O 1Claim 1!1, 16 or 1
In the method for fabricating a programmable read-only memory according to paragraph γ, the step of introducing other semiconductor dopants into the first region through the top surface to form the ff1 PN junction increases their lateral inward extension. A method for manufacturing a programmable read-only memory, characterized in that the insulating region is used as a mask for controlling. The dedicated memory is annealed at a suitable temperature to eliminate lattice defects introduced during the introduction process without causing significant redistribution of semiconductor impurities in the programmable read-only memory that were not introduced during the introduction process. A method for manufacturing a programmable read-only memory, characterized in that the programmable read-only memory is repairable. To S. In manufacturing the programmable read-only memory, a recessed electrically insulating region is provided in the semiconductor body, and this insulating region is connected to the doped region. (a) regions of a first conductivity type laterally spaced apart from each other along the top surface; A semiconductor dopant of the opposite third conductivity type,
introducing a portion of each single crystal section through the top surface to form a generally horizontal JPN junction completely adjacent to the insulating region, and introducing a lower region of the first conductivity type into the single crystal section; , and above each first PN junction, a substantially horizontal first BPM completely adjacent to said insulating region! 1. A method of manufacturing a programmable read-only memory, the method comprising forming an i1 combination. st. In the method for manufacturing a programmable read-only memory according to claim 20, the step of introducing a dopant of a second conductivity type is performed in a second conductivity type in each single crystal part.
A method of manufacturing a programmable read-only memory O'sl, characterized in that it includes the step of using the insulating region as a mask for controlling the lateral in-spreading of conductive type dopants. In the method for fabricating a memory, the step of introducing a dopant of the second conductivity type comprises the step of ion-implanting the dopant into the single crystal portion with sufficient energy to produce a maximum concentration below the 29th N junction. A method for manufacturing a programmable read-only memory characterized by: OS A method for manufacturing a programmable read-only memory, characterized in that the method includes the step of introducing into each single crystal part through the top surface. The step of introducing a dopant of the first conductivity type controls the lateral inward spread of the dopant of the first conductivity type in each single crystal part! A method for manufacturing a programmable read-only memory according to claim 84, characterized in that the method for manufacturing a programmable read-only memory includes the step of using the insulating region as a star. Annealing the dedicated memory at the appropriate temperature,
A programmable read device characterized in that lattice defects generated during the introduction step are repaired without significant redistribution of semiconductor impurities in the programmable read-only memory that were not introduced during the introduction step. Method for manufacturing a dedicated memo 10 ■ In the method for manufacturing a programmable read-only memory according to claim 20, 21 or 34, the lower side forming a plurality of buried regions of a first conductivity type having an average net dopant concentration greater than the dopant concentration of the regions, each buried region associated with at least one of said lower regions; and adjacent said insulating region along the entire lower edge of the lateral shoulder circumference of each associated lower region. 81. The method of manufacturing a programmable read-only memory according to claim 26, wherein the step of forming the buried region and providing the insulating region comprises forming a plurality of identical first memory regions spaced apart from each other along the surface of the substrate. selectively introducing a semiconductor impurity of a first conductivity type into a single crystal semiconductor 1,1° substrate of a second conductivity type at a position, growing an epitaxial semiconductor layer on the surface of the substrate, and forming a web-like shape of the epitaxial layer. forming a groove in the epitaxial layer by removing a portion along an upper surface thereof; selectively placing the substrate and the remaining portion of the epitaxial layer in a high temperature sanitizing atmosphere; The epitaxial layer portion along the groove is oxidized to form an insulating region, and the first
diffusing a portion of a conductive type impurity upward in the epitaxial layer to contact the insulating region to form a buried region;
A programmer characterized by having the steps of: How to make pull read-only memory. A method of manufacturing a programmable read-only memory according to claim 87, wherein the average-net dopant concentration in the remaining portion of the second conductivity type of the substrate laterally surrounding each buried region is Method of manufacturing a programmable read-only memory, characterized in that forming an embedded web of a second conductivity type with a large average net dopant concentration. The step of forming the embedded web, prior to the step of growing the epitaxial layer, includes forming a third S.sub. A method for manufacturing a programmable read-only memory, which comprises the step of selectively introducing a @electrotype semiconductor impurity into the substrate081 Manufacturing a programmable read-only memory according to claim 29 A method of manufacturing a programmable read-only memory, wherein a portion of the second conductivity type impurity diffuses upwardly into the epitaxial layer during the oxidation step to form the buried web. 8L The method of manufacturing a programmable read-only memory according to claim 80, wherein the semiconductor impurity introduced into the substrate at the first and first positions is removed by the embedded region being separated from the embedded web. A method for using programmable read-only memories, characterized in that they are spaced sufficiently apart from each other so that