JPS58182256A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58182256A JPS58182256A JP6432782A JP6432782A JPS58182256A JP S58182256 A JPS58182256 A JP S58182256A JP 6432782 A JP6432782 A JP 6432782A JP 6432782 A JP6432782 A JP 6432782A JP S58182256 A JPS58182256 A JP S58182256A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- semiconductor device
- heat sink
- groove
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関するものであり、特
に半導体収納容器に効率よく放熱板を取付ける方法を提
供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of efficiently attaching a heat sink to a semiconductor storage container.
近年ＬＳＩの高密度化・高集積度化が進めら扛て来た結
果、半導体チップの発熱量が大きくなって来た。例えば
１６ビツト・マイコンをＮＭＯ８で作った場合１〜１・
３Ｗの消費電力となる。こｎらＬＳＩは一般にビン数が
４０ピンと多く、さらには高信頼性が要求さｒるためセ
ラミック・パッケージを使用することが多い。今後さら
に高＠度が進むにつｎてセラミックパッケージの放熱方
法が大きな問題どなってくる。In recent years, as LSIs have become more dense and highly integrated, the amount of heat generated by semiconductor chips has increased. For example, if a 16-bit microcontroller is made with NMO8, 1 to 1.
The power consumption is 3W. These LSIs generally have a large number of pins, 40 pins, and require high reliability, so they often use ceramic packages. As the temperature rises further in the future, the heat dissipation method of ceramic packages will become a major issue.
一方、現在セラミックパッケージは４ｏピンＤＩＬでせ
いぜい熱抵抗は４０ ’Ｃ／Ｗであり、安全係数をかけ
扛ば消費電力１Ｗ以下、できｎばｏ、ｙｓｗ以下位のＬ
ＳＩしか搭載することができない。そこで、セラミック
パッケージにも放熱板を取付ける必要があり、こ扛に関
して多くの技術が公開さｎている。第１図に同技術に関
する従来の半導体装置の断面図を示す。１はセラミック
パッケージ、２はＬＳＩ等の半導体デバイス、３は接着
剤、４は放熱板である。On the other hand, the current ceramic package has a 4o-pin DIL with a thermal resistance of 40'C/W at most, and if you multiply it by a safety factor, the power consumption is less than 1W, which is less than nO, YSW.
Only SI can be installed. Therefore, it is necessary to attach a heat sink to the ceramic package, and many techniques regarding this have been disclosed. FIG. 1 shows a cross-sectional view of a conventional semiconductor device related to the same technology. 1 is a ceramic package, 2 is a semiconductor device such as an LSI, 3 is an adhesive, and 4 is a heat sink.
この構成の半導体装置を製造するには、まず半導体デバ
イス２をセラミックパッケージ１にダイスボンドし、ワ
イヤボンドした後、金属キヤツジで封止する。その後接
着剤３（例えば、エポキシ系接着剤）で放熱板４を接着
・固定する。To manufacture a semiconductor device having this configuration, the semiconductor device 2 is first die-bonded to the ceramic package 1, wire-bonded, and then sealed with a metal cage. Thereafter, the heat dissipation plate 4 is bonded and fixed with an adhesive 3 (for example, an epoxy adhesive).
第１図の従来の半導体装置の製造方法の場合、接着剤は
放熱板４とパンケージ１の周端で止っているように描い
ているが、実際にはセラミックパッケージに塗布して、
上から放熱板を押えるためはみ出しが生じることが多い
。特に熱伝導性を上げるために、接着剤中に金属粒子を
分散させた導電性接着剤を用いる場合は端部からのはみ
出しにより、リードのショートを引き起す等の問題があ
った。In the case of the conventional semiconductor device manufacturing method shown in FIG. 1, the adhesive is depicted as stopping at the peripheral edges of the heat sink 4 and the pan cage 1, but in reality it is applied to the ceramic package.
Protrusion often occurs because the heat sink is pressed down from above. In particular, when using a conductive adhesive in which metal particles are dispersed in the adhesive in order to increase thermal conductivity, there are problems such as short-circuiting of the leads due to protrusion from the ends.
本発明はかかる従来の問題点に関して、接着剤のはみ出
しを防止し、かつ気泡を含まないようにする半導体装置
の製造方法を提供するものである。The present invention addresses these conventional problems and provides a method for manufacturing a semiconductor device that prevents adhesive from extruding and does not contain air bubbles.
本発明の具体的な実施例を図面を用いて説明する。第２
図（ム）、 （Ｂ）は本発明の半導体装置の製造方法で
使用する放熱板の構造を示すものである。第２図（Ａ）
は閉じた周辺を持つ放熱板を示し、適切な深さの溝２２
が形成さｎている。この溝の形状は同図では正方形であ
るが円形でも、さらに変形した形状でも良い。２３は接
着領域である。Specific embodiments of the present invention will be described with reference to the drawings. Second
Figures (M) and (B) show the structure of a heat sink used in the method of manufacturing a semiconductor device of the present invention. Figure 2 (A)
shows a heat sink with a closed periphery, grooves 22 of appropriate depth
is formed. Although the shape of this groove is square in the figure, it may be circular or a further modified shape. 23 is an adhesive area.
同様に第２回申）は放熱板に溝を切った他の実施例を示
しており、放熱板２４の接着領域には複数本の溝２６が
刻ま扛ており、接着領域は島２６が形成さｎる。Similarly, the second paper) shows another embodiment in which grooves are cut in the heat dissipation plate, in which a plurality of grooves 26 are carved in the adhesive area of the heat dissipation plate 24, and islands 26 are formed in the adhesive area. Sanru.
いま第１図（ム）の放熱板２１をパッケージに接着する
には、壕ず、前記放熱板２１の接着領域２３に接着剤を
塗布し、パッケージに接着する。この場合余分の接着剤
は溝２２に流扛込むことになる。Now, in order to adhere the heat sink 21 shown in FIG. 1(m) to the package, an adhesive is applied to the bonding area 23 of the heat sink 21 without trenching, and the heat sink 21 is bonded to the package. In this case, excess adhesive will flow into the groove 22.
壕だ、第１図（ＢＪの放熱板の場合、領域２６に塗布さ
ｎた接着剤のうち、余分のものは溝２６に流扛込む。In the case of the BJ heat sink, the excess adhesive applied to the area 26 flows into the groove 26.
第３図に不発明の半導体装置の製造方法において接着さ
ｎだ放熱板の断面図を示す。同図において３１はセラミ
ックパッケージ、３２は半導体デバイス、３３は放熱板
で溝３４が形成さｎている。FIG. 3 shows a sectional view of a bonded heat sink in the method of manufacturing a semiconductor device according to the invention. In the figure, 31 is a ceramic package, 32 is a semiconductor device, and 33 is a heat sink, in which a groove 34 is formed.
３６は接着剤である。接着時の余分な接着剤は溝３４で
止まり、そｎ以上にははみ出していないことがわかる。36 is an adhesive. It can be seen that the excess adhesive during adhesion stops at the groove 34 and does not protrude beyond the groove 34.
以上のように、本発明の半導体装置の製造方法は放熱板
の接着面側に溝を設け、溝を埋めないように接着剤を塗
布して、パッケージに接着することにより、はみ出しと
、気泡の防止が容易にできる。本発明により、接着時の
工程が簡略化さｎｌまた熱伝導性の良い導電性接着剤を
使用できるだめ、放熱効率を大きく改善することができ
る。As described above, the semiconductor device manufacturing method of the present invention provides a groove on the adhesive side of the heat sink, applies adhesive so as not to fill the groove, and adheres it to the package, thereby preventing protrusion and air bubbles. Prevention is easy. According to the present invention, the bonding process can be simplified and a conductive adhesive with good thermal conductivity can be used, so that heat dissipation efficiency can be greatly improved.
第１図は従来の半導体装置の製造方法で得らｎた放熱板
を有するセラミックパッケージの断面図、第２図（ム）
、 （Ｂ）はそｎぞｎ本発明の半導体装置の製造方法に
使用さｎる放熱板の実施例を示す斜視図、第３図は不発
明の半導体装置の製造方法により得らｎたセラミックパ
ッケージの断面図を示す。
１・・・・・・セラミックパッケージ、２・・・・・・
半導体デバイス、３・・・・・・接着剤、４・・・・・
・放熱板、２２・・・・・・溝、２６・・・・・・溝、
３３・・・・・・放熱板、３５・・・・・・接着剤。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
１
４Figure 1 is a cross-sectional view of a ceramic package with a heat sink obtained by a conventional semiconductor device manufacturing method, and Figure 2 (m).
, (B) is a perspective view showing an embodiment of a heat sink used in the method of manufacturing a semiconductor device of the present invention, and FIG. 3 is a perspective view of a ceramic obtained by the method of manufacturing a semiconductor device of the invention. A cross-sectional view of the package is shown. 1...Ceramic package, 2...
Semiconductor device, 3... Adhesive, 4...
・Radiation plate, 22...groove, 26...groove,
33... Heat sink, 35... Adhesive. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 1 4
Claims (2)
本の溝を設けた放熱板を、接着剤もしくは半田材により
、半導体収納容器の放熱板接着領域に接着固定すること
を特徴とする半導体装置の製造方法。(1) - A heat dissipation plate provided with a plurality of grooves including at least the area to be bonded on the main surface is adhesively fixed to the heat dissipation plate bonding area of the semiconductor storage container using an adhesive or a solder material. A method for manufacturing a semiconductor device.
溝を有する放熱板を、接着剤もしく、は半円材により、
半導体収納容器の放熱板接着領域に接着固定する半導体
装置の製造方法。(2) - Using adhesive or semicircular material, attach a heat dissipation plate having grooves arranged so as to surround the area to be bonded on the main surface.
A method for manufacturing a semiconductor device that is adhesively fixed to a heat sink adhesive area of a semiconductor storage container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6432782A JPS58182256A (en) | 1982-04-16 | 1982-04-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6432782A JPS58182256A (en) | 1982-04-16 | 1982-04-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58182256A true JPS58182256A (en) | 1983-10-25 |
Family
ID=13255024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6432782A Pending JPS58182256A (en) | 1982-04-16 | 1982-04-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182256A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4804600A (en) * | 1984-07-06 | 1989-02-14 | Canon Kabushiki Kaisha | Lithographic mask structure and process for preparing the same |
| US7215020B2 (en) | 2003-10-29 | 2007-05-08 | Denso Corporation | Semiconductor device having metal plates and semiconductor chip |
| JP2017028131A (en) * | 2015-07-23 | 2017-02-02 | 株式会社デンソー | Package mounting body |
-
1982
- 1982-04-16 JP JP6432782A patent/JPS58182256A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4804600A (en) * | 1984-07-06 | 1989-02-14 | Canon Kabushiki Kaisha | Lithographic mask structure and process for preparing the same |
| US7215020B2 (en) | 2003-10-29 | 2007-05-08 | Denso Corporation | Semiconductor device having metal plates and semiconductor chip |
| JP2017028131A (en) * | 2015-07-23 | 2017-02-02 | 株式会社デンソー | Package mounting body |
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