JPS58176921A - Semiconductor substrate and manufacture of the same - Google Patents
Semiconductor substrate and manufacture of the sameInfo
- Publication number
- JPS58176921A JPS58176921A JP5965282A JP5965282A JPS58176921A JP S58176921 A JPS58176921 A JP S58176921A JP 5965282 A JP5965282 A JP 5965282A JP 5965282 A JP5965282 A JP 5965282A JP S58176921 A JPS58176921 A JP S58176921A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- crystal layer
- single crystal
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000013078 crystal Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000010453 quartz Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000012808 vapor phase Substances 0.000 claims description 6
- 238000001947 vapour-phase growth Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 claims description 2
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000005546 reactive sputtering Methods 0.000 abstract description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000005979 thermal decomposition reaction Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 239000011029 spinel Substances 0.000 description 3
- 229910052596 spinel Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000000197 pyrolysis Methods 0.000 description 2
- 208000012468 Ewing sarcoma/peripheral primitive neuroectodermal tumor Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体基体及びその製法に係〕１％に絶縁基
板上に半導体単結晶層が形成されて成る半導体基体及び
その製法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor substrate and a method for manufacturing the same.The present invention relates to a semiconductor substrate comprising a semiconductor single crystal layer formed on a 1% insulating substrate and a method for manufacturing the same.
絶縁基板上に半導体結晶層を形成して成る半導体基体と
しては、従来よシ、単結晶サファイア又は単結晶スピネ
ルを絶縁基板とし、この絶縁基板上に例えばＳム（シリ
コン）単結晶層を気相によυエピタキシャル成長させた
ものが知られておシ。Conventionally, as a semiconductor substrate formed by forming a semiconductor crystal layer on an insulating substrate, a single crystal sapphire or a single crystal spinel is used as an insulating substrate, and a single crystal layer of, for example, SMU (silicon) is formed in a vapor phase on this insulating substrate. However, epitaxial growth is known.
ｎ
一般に８０８（Ｓｉ目ｃｏｎ ５ａｐｐｈｉｒｅ又は３
ｐｉｎｅｌ ）八
と呼ばれている。しかし、単結晶サファイア又は単結晶
スピネルは極めて高価なものであシ、シかも大口径のウ
ェハを成長させることが難かしく。n Generally 808 (Si order con 5apphire or 3
It is called pinel ) eight. However, single crystal sapphire or single crystal spinel are extremely expensive and may be difficult to grow on large diameter wafers.
現在は最大ロ径７５■程度のものしか市販されていない
。Currently, only those with a maximum diameter of 75 cm are commercially available.
このことから、近年、単結晶サファイア又はスピネル以
外の絶縁基板上に半導体単結晶層を形成させた。いわゆ
るｆ３Ｑ 工（５ｉｌｉｃｏｎ Ｑｎ Ｊｎｓｕｌａ−
１ｅｒ）基体の製造方法についての提案がなされている
。For this reason, in recent years, semiconductor single crystal layers have been formed on insulating substrates other than single crystal sapphire or spinel. The so-called f3Q engineering (5ilicon Qn Jnsula-
1er) A proposal has been made regarding a method of manufacturing the substrate.
その−例として１石英板から成る絶縁基板上に多結晶又
は非晶質のＢｔ層を一旦形成させた後、ＣＷ（Ｃｏｎｔ
１ｎｕｏｕａ Ｗａｖｅ ） ｖ−ザ７＝−Ａｆｍし
てそのＢｔ層を単結晶化させる方法によシ製造された。For example, after forming a polycrystalline or amorphous Bt layer on an insulating substrate made of a quartz plate,
The Bt layer was manufactured by a method in which the Bt layer was made into a single crystal by 1nuoua Wave) v-the7=-Afm.
いわゆるグラフオエピタキシ（Ｇｒａｐｈ。So-called graphoepitaxy (Graph.
−Ｅｐｉｔａｘｙ）が知られている。-Epitaxy) is known.
しかしながら、多結晶又は非晶質のＳｉ層を形成させる
工程と、結晶性のよい単結晶層を得るためには同一箇所
に対して１例えば４回以上の０ｗレーザアニール処理を
施す工程が必要であることから製造工程が複雑になって
しまうという欠点を有しておシ、さらに大きな欠点とし
て、レーザアニール処理時ＫＳｉ層にクランクが入って
しまうことが多い丸め、これを適用する半導体装置の歩
留夛が極めて悪くなってしまうということがあった。However, in order to form a polycrystalline or amorphous Si layer and to obtain a single crystal layer with good crystallinity, it is necessary to perform 0W laser annealing treatment on the same location one time, for example, four or more times. This has the drawback of complicating the manufacturing process, and an even bigger drawback is rounding, which often creates cranks in the KSi layer during laser annealing, and the steps of semiconductor devices to which this is applied. There were times when the retention became extremely bad.
また、他の例として、石英板から成る絶縁基板上に非晶
質のＳｉ層を形成させた後、このＢｋ層表面にＳｉＱ、
膜を形成し、とのｓｉｏ、膜を介して周知のストリップ
ヒータ（３ｔｒｉｐ−１（ｅｎｔｅｒ ）によってＢｔ
層を加熱することにより、単結晶化させる方法が提案さ
れている。As another example, after forming an amorphous Si layer on an insulating substrate made of a quartz plate, SiQ,
A film was formed, and Bt was heated through the film by a well-known strip heater (3 trip-1 (enter)
A method has been proposed in which a layer is heated to form a single crystal.
しかしながら、この方法にあって４．非晶質のＢｔ層を
形成させる工程、ＳｔＯ，膜を形成させる工程、及びス
トリップヒータによる単結晶化工程が必要となυ、製造
工程が複雑であるという欠点を有していた。However, in this method, 4. This method has disadvantages in that it requires a step of forming an amorphous Bt layer, a step of forming an StO film, and a single crystallization step using a strip heater, and the manufacturing process is complicated.
本発明の目的は、半導体単結晶層を簡単な工程で形成さ
せることのできる絶縁基板を備えて構成される半導体基
体およびその製法を提供することにある。An object of the present invention is to provide a semiconductor substrate including an insulating substrate on which a semiconductor single crystal layer can be formed in a simple process, and a method for manufacturing the same.
本発明は、所望とする面方位を有する半導体単結晶層を
気相成長によシ形成させる表面が少なくとも絶縁材料か
ら成シ、且つ、皺表面部に前記面方位及び前記気相成長
条件に応じて選択的に定められる所定形状の凹凸部を形
成させ九絶縁基板を用い、該絶縁基板の前記表面に半導
体層を気相成長させることＫよシ、簡単な工程で半導体
単結晶層を形成させようとするものである。The present invention provides that the surface on which a semiconductor single crystal layer having a desired plane orientation is formed by vapor phase growth is made of at least an insulating material, and that the wrinkled surface portion is formed according to the plane orientation and the vapor growth conditions. A semiconductor single-crystal layer is formed in a simple process by using an insulating substrate on which uneven portions of a predetermined shape selectively determined are formed, and a semiconductor layer is vapor-phase grown on the surface of the insulating substrate. This is what we are trying to do.
以下１本発明の原理に係る。絶縁基板上に気相成長され
るＢｔ層の成長機構について第１図及び第２図を用いて
説明する。The following 1 relates to the principle of the present invention. The growth mechanism of a Bt layer grown in a vapor phase on an insulating substrate will be explained with reference to FIGS. 1 and 2.
一般に、第１図に示されるような平坦な石英板１上にＢ
ｔを熱分解法によって、少なくとも９５０Ｃ以上の温度
条件下で沈着させていくと、その初期において、石英板
ｌの表面にはｓｉの液滴集合体２が形成される。この液
滴集合体２の１つの（１００）面＃′ｉ１図示されたよ
うに１石英板１０表面と平行に形成され、他の面方位は
不規則に形成されることが知られている。なお、説明を
簡単にして面方位が明確に判るようにするため、第１図
では液滴集合体２の形状を模式的な直方体にて表わした
が、実際の液滴集合体２の表面は曲面状に形成される。Generally, B is placed on a flat quartz plate 1 as shown in FIG.
When t is deposited by a pyrolysis method under a temperature condition of at least 950 C or higher, an aggregate of Si droplets 2 is formed on the surface of the quartz plate 1 at the initial stage. It is known that one (100) plane #'i1 of this droplet aggregate 2 is formed parallel to the surface of the quartz plate 10 as shown, and the other planes are formed irregularly. In order to simplify the explanation and clearly understand the plane orientation, the shape of the droplet aggregate 2 is shown as a schematic rectangular parallelepiped in FIG. 1, but the actual surface of the droplet aggregate 2 is It is formed into a curved shape.
このような液滴集合体２は石英板１上のいたるところで
形成され、さらにＳｉを沈着させていくと、前記液滴集
合体２を夫々種結晶として８１の結晶領域が成長される
。しかし、前述したように夫々の種結晶の結晶面は一方
向を除いて無秩序であるため、夫々の結晶領域は無秩序
に成長された結晶粒の単なる集合体となってしまい、平
坦な表面を有する石英板１上にＳｉ層を気相成長させる
と多結晶のＳｉ層が形成されてしまうのである。Such droplet aggregates 2 are formed everywhere on the quartz plate 1, and as Si is further deposited, 81 crystal regions are grown using the droplet aggregates 2 as seed crystals. However, as mentioned above, the crystal planes of each seed crystal are disordered except in one direction, so each crystal region becomes a mere collection of crystal grains grown in a disordered manner, resulting in a flat surface. When a Si layer is grown in a vapor phase on the quartz plate 1, a polycrystalline Si layer is formed.
そこで、本発明に係る絶縁基板は第２図に示されたよう
に１例えば絶縁基板として５石英板３の上表面に断面が
矩形状の溝４が所定のピッチでストライブ状に穿設され
たものを用い、少なくとも９５０Ｃ以上の温度条件下で
３ｉを熱分解法にょシ沈着させていくと、液滴集合体５
は、溝４によって形成された石英板３の図示面（→及び
（ｂ）、又は（ｂ）及び（Ｃ）の直角に交わる少なくと
も２つの面によってその結晶面が規定されるため、溝４
に石って沈着される液滴集合体５は規則的に同一面方位
をもったものとして形成される。このようにして形成さ
れた液滴集合体５を種結晶としてさらにＢｉを沈着させ
ると石英板３表面全域に（１００）面方位を有する８１
単結晶層を形成させることができる。Therefore, in the insulating substrate according to the present invention, as shown in FIG. 2, grooves 4 having a rectangular cross section are bored in the upper surface of the quartz plate 5 at a predetermined pitch in the form of stripes. When 3i is deposited using a pyrolysis method under a temperature condition of at least 950C or higher, a droplet aggregate 5 is formed.
is defined by the illustrated plane of the quartz plate 3 formed by the groove 4 (→ and (b), or (b) and (C)), since its crystal plane is defined by at least two planes that intersect at right angles.
The droplet aggregates 5 that are deposited regularly are formed having the same plane orientation regularly. When Bi is further deposited using the droplet aggregate 5 thus formed as a seed crystal, 81
A single crystal layer can be formed.
なお、上述したように単結晶層の成長機構においては成
長初期に半導体の液滴集合体が形成されることと、絶縁
基板上に形成された凹凸部（溝）の形状寸法とが重要な
因子になっているのである。As mentioned above, in the growth mechanism of a single crystal layer, important factors are the formation of semiconductor droplet aggregates in the early stage of growth and the shape and dimensions of the uneven portions (grooves) formed on the insulating substrate. It has become.
まず、液滴集合体が形成される機構は１例えば熱分解に
よりガス化されたＳｉガスが、絶縁基板面に１着されて
液滴が形成されたとき、そのときのガスの拡散条件等に
よシ定まる液滴の持つ運動エネルギーによって液滴が絶
縁基板上を移動し、他の液滴と凝集されて液滴集合体が
形成されるものと考えられる。従って、液滴集合体を形
成させるためには半導体の種類に応じて気相成長処理さ
せる最低温度を設定することが肝要である。First, the mechanism by which a droplet aggregate is formed is 1. For example, when Si gas gasified by thermal decomposition is deposited on the surface of an insulating substrate and a droplet is formed, depending on the gas diffusion conditions at that time, etc. It is considered that the droplet moves on the insulating substrate due to the kinetic energy of the droplet, which is determined by the equation, and aggregates with other droplets to form a droplet aggregate. Therefore, in order to form droplet aggregates, it is important to set the lowest temperature for vapor phase growth depending on the type of semiconductor.
次に、凹凸部の形状寸法が所望とする半導体単結晶層と
どのように係わるかについて説明する。Next, a description will be given of how the shape and dimensions of the uneven portion relate to the desired semiconductor single crystal layer.
前述したように、初期に沈着した液滴集合体が石英板面
の溝の２面によってその集合体結晶面の２つの（１００
）面が規定されるので１石英板全域に沈着される液滴集
合体の面方位が同一になるのである。このことから、初
期に形成される液滴集合体の大きさ、即ち平面的な外形
寸法に対応させて、少なくともその結晶面を規定する２
゜面を、前記外形寸法内に存在させるように溝を穿設す
ることが肝要である。なお％液滴集合体の外形寸法は適
用される半導体の攬類及び気相成長法の種類。As mentioned above, the initially deposited droplet aggregate is separated by two (100
) plane is defined, so that the plane orientation of droplet aggregates deposited over the entire area of one quartz plate is the same. From this, it can be seen that at least the crystal plane is defined by the size of the initially formed droplet aggregate, that is, the planar external dimension.
It is important to drill the groove so that the .degree. surface lies within the above-mentioned outer dimensions. The external dimensions of the droplet aggregates are based on the type of semiconductor and the type of vapor phase growth method used.
例えば、熱分解法（ＣＶＤ法）１分子線沈着法。For example, thermal decomposition method (CVD method) single molecule beam deposition method.
プラズマ沈着法又はスパッタ法、又は絶縁基板表面粗度
などによって異なるとともに、そのときの処理温度条件
によっても左右され、温度が高くなるにつれて外形寸法
が大きくなる傾向にある。例えば、Ｓｉを用いた熱分解
法によれば９５０ｃ以上でなけれは液滴集合体が形成さ
れないので１本発明によりＳｉ単結晶層を形成させるた
めには少なくとも９５０Ｃ以上の処理温度下で気相成長
させなければならない。It varies depending on the plasma deposition method or sputtering method, the surface roughness of the insulating substrate, etc., and also depends on the processing temperature conditions at that time, and the external dimensions tend to increase as the temperature increases. For example, according to the thermal decomposition method using Si, droplet aggregates are not formed unless the temperature is 950C or higher.1 In order to form a Si single crystal layer according to the present invention, vapor phase growth is required at a processing temperature of at least 950C or higher. I have to let it happen.
また、前述した構形状によって（１００）面を有するＳ
ｉ単結晶層を得ることができたのであるが、形成される
単結晶層の面方位は、液滴集合体の面方位を規定する絶
縁基板上の少なくとも２面のなす角度及びその配列によ
って定まってくることは、前述し九単結晶層の成長機構
からいって当然のことである。Moreover, due to the above-mentioned structural shape, S having a (100) plane
i was able to obtain a single crystal layer, but the plane orientation of the formed single crystal layer is determined by the angle formed by at least two planes on the insulating substrate that define the plane orientation of the droplet aggregate and their arrangement. This is natural from the growth mechanism of the nine single crystal layers mentioned above.
例えば、（１００）面の単結晶層を形成させるためには
絶縁基板上の凹凸形状は、第２図図示の溝４に表わされ
た形状の他、同様の溝を格子状に配設したもの、あるい
は、直方体の凹嵌部を夫々平行に穿設したものであって
もよく、要は、形成させる単結晶層の上表面とこの結晶
層上表面と直交する面とを基準としてそれらに平行な面
から成る凹凸部本しくは、さらにそれらの面と直交する
面とからなる凹凸部が形成されていればよいのである。For example, in order to form a single crystal layer with a (100) plane, the uneven shape on the insulating substrate should be such that, in addition to the shape shown in the groove 4 shown in FIG. 2, similar grooves are arranged in a lattice pattern. Alternatively, it may be a rectangular parallelepiped with recessed parts bored in parallel to each other, and in short, the upper surface of the single crystal layer to be formed and the plane perpendicular to the upper surface of this crystal layer are used as reference points. It is only necessary to form an uneven portion consisting of parallel planes, or more preferably, an uneven portion consisting of a plane perpendicular to these planes.
また、（１１０）面のものを形成させるためには、例え
ば第３図に示されたように、絶縁基板３上に断面Ｖ字形
の溝６を又ストライプ状に隣接して配列し、且つ溝６を
構成する斜面６ａ、５ｂは互いに直交し、且つ形成させ
る単結晶層の上表面に対して４５°の角度をもたせて穿
設したものとすればよい。一方、（１１１）面方位のも
のを形成させるためには、例えば第４図囚、＠に示され
たように、絶縁基板上に三角錐状の凹嵌部７を隣接させ
て配接することによシ形成される凹凸部とすればよい。In addition, in order to form the (110) plane, for example, as shown in FIG. The slopes 6a and 5b constituting the groove 6 may be perpendicular to each other and formed at an angle of 45° with respect to the upper surface of the single crystal layer to be formed. On the other hand, in order to form one with a (111) plane orientation, for example, as shown in Figure 4, @, triangular pyramid-shaped recessed fittings 7 are placed adjacent to each other on an insulating substrate. It is sufficient if the uneven portion is formed in a well-formed manner.
なお、第４図囚は平面図、第４図面は断面図である。Note that FIG. 4 is a plan view, and the fourth drawing is a sectional view.
以下、本発明の一実施例に基づいて説明する。Hereinafter, an explanation will be given based on one embodiment of the present invention.
第５図（ａ）〜（ｄ）に本発明製法の一実施例の工程図
が示されている。FIGS. 5(a) to 5(d) show process diagrams of an embodiment of the manufacturing method of the present invention.
第５図は、絶縁基板上に（Ｚｏｏ）面の半導体単結晶層
を形成させた半導体基体の製法を示すものである。工程
（ａ） において絶縁基板としての石英板１１の表面を
光学研磨する。工程（ｂ）において２石英板１１表面に
ホトレジストを塗布し、ホトリソグラフィによって２μ
ｍ関隔０ストライプ状のレジスト１２を残留形成させる
。工程（Ｃ）において。FIG. 5 shows a method for manufacturing a semiconductor substrate in which a (Zoo) plane semiconductor single crystal layer is formed on an insulating substrate. In step (a), the surface of the quartz plate 11 serving as an insulating substrate is optically polished. In step (b), a photoresist is applied to the surface of the two quartz plates 11, and a 2μ
A resist 12 in the form of a stripe with an m distance of 0 is formed as a residual resist. In step (C).
反応性スパッタによシ深さ０．２μｍの溝１３を形成せ
しめた後、レジスト１２を剥離除去する。このようにし
て形成された、所定の凹凸部を有する石英板１１０表面
上に、工程（ｄ）において、熱分解処理温度１１００Ｃ
の条件下でｓｔＨｗとＨｌとの混合ガスを分解させて気
相成長させる。このようにしてｓ ８ ’単結晶層１４
が形成されるのである。After forming grooves 13 with a depth of 0.2 μm by reactive sputtering, the resist 12 is peeled off. In step (d), the surface of the quartz plate 110 having the predetermined unevenness formed in this manner is subjected to a thermal decomposition treatment at a temperature of 1100C.
A mixed gas of stHw and Hl is decomposed and vapor phase grown under these conditions. In this way, s 8 ′ single crystal layer 14
is formed.
なお、上述の製法によシ形成された半導体基体のＢｔ結
晶層１４を、電子線回折で観察したところ（１００）面
を有する単結晶層であることを確認することができた。Note that when the Bt crystal layer 14 of the semiconductor substrate formed by the above manufacturing method was observed by electron beam diffraction, it was confirmed that it was a single crystal layer having a (100) plane.
従って、本実施例によれば、極めて簡単な工程によって
、所望とする面方位の半導体単結晶層を形成させること
ができ、絶縁基板を有して成る半導体基体ＳＯＩを極め
て安価に形成させることができる。Therefore, according to this example, a semiconductor single crystal layer having a desired plane orientation can be formed by an extremely simple process, and a semiconductor substrate SOI having an insulating substrate can be formed at an extremely low cost. can.
なお１本実施例によって形成されたＳＯＩを適用してＮ
チャンネルＭＯ８形ＥＦＴを１通常の熱拡散、熱酸化な
どの工程により製作し九ところ。Note that by applying the SOI formed according to this embodiment, N
Nine channel MO8 type EFTs were manufactured using conventional processes such as thermal diffusion and thermal oxidation.
キャリヤの表面移動度は約６００ ｃｍ” ／ｖｓとな
っておシ、従来のＭＯ８形ＥＦＴと同様の特性が得られ
た。従って、このＳＯＩを適用してＭＯ８形ＥＦＴから
成るＬＳＩ装置を形成させれば、従来のＳＯ８を用いた
ものと同様に、従来のバルクＳｉ基板を用いたものに比
較して、演算速度を２〜３倍の速度に高めることができ
ることを容易に想定することができ、集積度をさらに高
めることができる。The surface mobility of the carrier was approximately 600 cm"/vs, and the same characteristics as the conventional MO8 type EFT were obtained. Therefore, this SOI was applied to form an LSI device consisting of the MO8 type EFT. If so, it can be easily assumed that the calculation speed can be increased to 2 to 3 times that of the conventional one using a bulk Si substrate, similar to the one using the conventional SO8. , the degree of integration can be further increased.
また、上述した実施例においては説明しなかったが、絶
縁基板上にＳｔ結晶層を形成させる前に、例えばＣＶ
Ｄ （Ｃ，ｈａｍｊｃａｌ ＶａｐＯｒ Ｄｅｐｏｓｉ
ｔｊｏｎ）法などによシ、予め８”ＭＮ４膜又はＳｔＯ
，膜を形成させておくことは、Ｓｉ単結晶化の容易性を
高めるうえで効果がある。Further, although not explained in the above embodiment, before forming the St crystal layer on the insulating substrate, for example, CV
D (C, hamjcal VapOr Deposit
8" MN4 film or StO
, is effective in increasing the ease of Si single crystallization.
さらにまた、ストライプ状の溝の間隔は２μｍに限られ
るものでないことは前述したとおシであ＃）１溝深さに
ついてもα２μｍに限定される吃のではない。Furthermore, as mentioned above, the interval between the striped grooves is not limited to 2 μm, and the depth of one groove is not limited to α2 μm either.
勿論１本発明はＢｔに限られるものではなく。Of course, the present invention is not limited to Bt.
他の半導体１例えばＧ ｅ 、 Ｇｅｌｋｍ、 Ｇａｐ
ｅどにも適用されるものであシ、絶縁基板についても
石英板に限定されるものではなく、例えば、バルクＳｉ
基板上ＶｃＳ：Ｏ，膜又は５１１Ｎ４ 膜など絶縁性
膜を形成したものであってもよく、このような場合凹凸
部は、予めバルクＳｉ基板に形成させても。Other semiconductors 1 such as Ge, Gelkm, Gap
The insulating substrate is not limited to quartz plates, for example, bulk Si
An insulating film such as a VcS:O film or a 511N4 film may be formed on the substrate, and in such a case, the uneven portions may be formed in advance on the bulk Si substrate.
あるいは絶縁性膜に形成させても同じ効果が得られる。Alternatively, the same effect can be obtained by forming it on an insulating film.
以上説明したように１本発明によれば、所望とする半導
体単結晶層を簡単な工程で形成させることができるとい
う著しい効果を有する。As described above, the present invention has the remarkable effect that a desired semiconductor single crystal layer can be formed in a simple process.
第１図〜第４図囚、■は本発明の詳細な説明するための
図であシ、第２図はストライプ状の溝を有する絶縁基板
上に形成された液滴集合体の初期状態を模式的に示した
図、第３図はストライプ状のＶ字形溝を有する絶縁基板
例、第４図囚、■は三角錐状の凹嵌部を有する絶縁基板
例であり同図囚は平面図、同図■は断面図、第５図は本
発明の一実施例の製法工程を示す図である。
３・・・石英板（絶縁基板）、４・・・溝、５・・・液
滴集合体、６・・・＃１．７・・・凹嵌部、１１・・・
石英板、１２・・・茅ｌ 目
２
／
夢２ 目
芽３ 目
′！Ｊ４目Figures 1 to 4 are diagrams for explaining the present invention in detail, and Figure 2 shows the initial state of a droplet aggregate formed on an insulating substrate having striped grooves. The schematic diagrams shown in Fig. 3 are an example of an insulating substrate having a striped V-shaped groove, and Fig. 4 (2) is an example of an insulating substrate having a triangular pyramid-shaped concave fitting part, and the figure (5) is a plan view. , 2 is a sectional view, and FIG. 5 is a diagram showing the manufacturing process of an embodiment of the present invention. 3... Quartz plate (insulating substrate), 4... Groove, 5... Droplet aggregate, 6... #1.7... Recessed fitting part, 11...
Quartz plate, 12... 2 eyes / dream 2 eyes bud 3 eyes'! J4th
Claims (1)
面方位に応じて該単結晶層の等価（１００）面の少なく
とも２つの面と夫々接合する面から成る凹凸部が当該基
板表面に形成された基板と、前記基板表面に気相成長さ
れた半導体単結晶層と。 から成ることを特徴とする半導体基体。 ｚ４！許請求の範囲第１項記載の発明において。 前記基板は少なくとも前記表面が絶縁材料から形成され
た絶縁基板であることを特徴とする半導体基体。 ＆ 特許請求の範囲第２項記載の発明において。 前記絶縁基板は石英板から形成されたものであることを
特徴とする半導体基体。 表 特許請求の範囲ｆｓ２項記載の発明（おいて。 前記絶縁基板は当該表面に絶縁薄膜を有する８１基板か
ら形成されたものであることを特徴とする半導体基体。 ＆ 特許請求の範囲第１項乃至第４項記載の発明におい
て、前記凹凸部はストライプ状又は格子状に配設された
断面矩形の溝から形成されたものであることを％黴とす
る半導体基体。 ６、特許請求の範ｉ！！第１項乃至第４項記載の発明に
おいて、前記凹凸部は一ストライプ状に隣接配設された
断面が対象なＶ字形の溝であって鉄構の傾斜面を直交さ
せて形成させ九本のであることを特徴とする半導体基体
。 ７、 ４Ｉ許請求の範囲第１項乃至第４項記載の発明に
おいて、前記凹凸部は隣接配設された三角錐状の凹嵌部
であって該凹嵌部の傾斜面を互いに直交させ且つ等斜辺
状に形成させたものであることを特徴とする半導体基体
。 ＆ 当該基板表面に形成させる半導体単結晶層の主表面
面方位に応じて該単結晶層の等価（１００）面の少なく
とも２つの面と夫々接合する面から成る凹凸部が当該基
板表面に形成された基板を用いて該基板表面に半導体単
結晶層を形成させるにあえって、温度条件、半導体種類
及び前記基板表面粗度などの気相成長条件に応じて定ま
る大きさを有して初期に沈着形成される液滴集合体が前
記凹凸部を形成する少なくとも異なる２つの面と接合す
るように前記気相成長条件を制御することを特徴とする
半導体基体の製法。[Claims] 1. An uneven portion consisting of a surface that joins with at least two surfaces of the equivalent (100) plane of the semiconductor single crystal layer, depending on the main surface orientation of the semiconductor single crystal layer to be formed on the surface of the substrate. is formed on the surface of the substrate, and a semiconductor single crystal layer that is vapor-phase grown on the surface of the substrate. A semiconductor substrate characterized by comprising: z4! In the invention described in claim 1. A semiconductor substrate, wherein the substrate is an insulating substrate in which at least the surface thereof is formed of an insulating material. & In the invention described in claim 2. A semiconductor substrate, wherein the insulating substrate is formed from a quartz plate. Table: The invention as claimed in claim fs 2 (in) A semiconductor substrate characterized in that the insulating substrate is formed from an 81 substrate having an insulating thin film on the surface thereof. & Claim 1 In the invention according to any one of claims 1 to 4, the semiconductor substrate is characterized in that the uneven portion is formed of grooves having a rectangular cross section arranged in a striped or lattice pattern. !!In the invention described in Items 1 to 4, the uneven portions are V-shaped grooves with symmetrical cross sections arranged adjacently in a stripe shape, and are formed so as to orthogonally intersect the inclined surfaces of the steel structure. A semiconductor substrate characterized in that it is a book.7.4I In the invention according to claims 1 to 4, the uneven portions are triangular pyramid-shaped recessed fitting portions disposed adjacent to each other. A semiconductor substrate characterized in that the sloped surfaces of the recessed fitting portions are orthogonal to each other and are formed in the shape of equal hypotenuses. Forming a semiconductor single crystal layer on the surface of the substrate using a substrate in which a concavo-convex portion is formed on the surface of the substrate, each consisting of a surface that joins at least two surfaces of the equivalent (100) plane of the crystal layer, Droplet aggregates initially deposited and having a size determined depending on vapor growth conditions such as temperature conditions, semiconductor type, and substrate surface roughness form at least two different surfaces forming the uneven portions. A method for manufacturing a semiconductor substrate, characterized in that the vapor phase growth conditions are controlled so as to achieve bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5965282A JPS58176921A (en) | 1982-04-12 | 1982-04-12 | Semiconductor substrate and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5965282A JPS58176921A (en) | 1982-04-12 | 1982-04-12 | Semiconductor substrate and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58176921A true JPS58176921A (en) | 1983-10-17 |
Family
ID=13119342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5965282A Pending JPS58176921A (en) | 1982-04-12 | 1982-04-12 | Semiconductor substrate and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58176921A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5105260A (en) * | 1989-10-31 | 1992-04-14 | Sgs-Thomson Microelectronics, Inc. | Rf transistor package with nickel oxide barrier |
| US5156995A (en) * | 1988-04-01 | 1992-10-20 | Cornell Research Foundation, Inc. | Method for reducing or eliminating interface defects in mismatched semiconductor epilayers |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54137486A (en) * | 1978-04-13 | 1979-10-25 | Massachusetts Inst Technology | Method of enhancing epiconfiguration and good orientation ofsolid coating |
-
1982
- 1982-04-12 JP JP5965282A patent/JPS58176921A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54137486A (en) * | 1978-04-13 | 1979-10-25 | Massachusetts Inst Technology | Method of enhancing epiconfiguration and good orientation ofsolid coating |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5156995A (en) * | 1988-04-01 | 1992-10-20 | Cornell Research Foundation, Inc. | Method for reducing or eliminating interface defects in mismatched semiconductor epilayers |
| US5105260A (en) * | 1989-10-31 | 1992-04-14 | Sgs-Thomson Microelectronics, Inc. | Rf transistor package with nickel oxide barrier |
| USRE37082E1 (en) | 1989-10-31 | 2001-03-06 | Stmicroelectronics, Inc. | RF transistor package with nickel oxide barrier |
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