JPS58175192A - Read/write memory circuit - Google Patents

Abstract

PURPOSE:To obtain a memory circuit where the diagnosis of access to all addresses and all words is possible, by providing an address switching circuit which uses a write address as a read address during the diagnosis, a data switching circuit which switches data on a shift path to normal input data, and a write controlling circuit which writes an inverted value of input data. CONSTITUTION:A memory circuit 1 is provided with a one-bit fourword read/ write memory circuit 2, a data switching circuit 3 which switches the shift path and the normal path by a shift signal to output data, a read address switching circuit 4 which switches a stored write address and a normal read address to output one of them by a diagnostic signal, and a write controlling circuit 5 which writes the inverted value of input data in words other than the word indicated by the write address or writes input data only in the word indicated by the write address in accordance with the diagnostic signal. Therefore, the diagnosis on the shift path where the write address is changed at random is possible, and all addresses and all words of the memory circuit are diagnosed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field to Which the Invention Pertains The present invention relates to a read/write memory circuit using a shift path for the purpose of improving diagnosis.

(2) Description of the prior art Conventionally, the shift path method has been effective in package testing, but when the circuit under test of the package includes a read/write memory circuit, the shift path of this circuit is Since reading/writing of the memory circuit is limited to the address, the fan-in and fan-out circuits of the memory circuit have been sufficiently tested by shift-in and shift-out operations. However, this memory circuit itself has a drawback in that sufficient read/write tests cannot be performed for all addresses.

(3) Object of the Invention The object of the present invention is to provide a read address switching circuit in which, in a read/write memory circuit, once writing is performed during diagnosis, the write address becomes the read address until the next write operation. and,
A data switching circuit that switches the shift path data to the input data of the memory circuit when there is a shift during diagnosis, and normal data when it is not 7 feet, and all words other than those indicated by the write address during diagnosis. By providing a write control circuit that writes the inverted value of the input data to be written to the word indicated by the write address, the above drawback is eliminated and the shift path of the read/write memory circuit is changed during diagnosis. It is not limited to the word specified by a specific fixed address (i° address can be changed randomly, and all words other than the address specified by the write address can be changed to the word specified by the write address. It is an object of the present invention to provide a read/write memory circuit that allows read/write tests of all addresses and all words even during diagnosis by always writing an inverted value of data to be written.

(4) Structure of the Invention The present invention is a read/write circuit that is composed of a plurality of words of memory, uses one word of the memory as a shift path, and has an input data switching circuit that switches between the shift path and the normal path using a shift signal. a circuit that stores a write address; a selection circuit that selects the storage circuit as the read address of the memory circuit when diagnosing based on the diagnostic signal; and a selection circuit that selects a normal read address when not diagnosing; When diagnosing, write the inverted value of the input data written to the word indicated by the write address to all words other than those indicated by the write address, and when not diagnosing, write the inverted value of the input data written to the word indicated by the write address. The present invention is characterized in that it includes a write control circuit that writes input data only to words.

(5) Principle and operation of the invention The present invention provides a read/write memory circuit with a built-in shift path, and during diagnosis, once writing is performed in the memory circuit, the write address remains unchanged until the next write operation. By becoming a read address, writing/reading can be performed regardless of the address. Furthermore, the inverted value of the input data to be written in the word specified by the write address is also written in words other than those specified by the write address. Therefore, the shift path of one word passing through the memory circuit can be any address, and it is no longer necessary to fix the address for the shift path during diagnosis, making it possible to perform random all-address, all-word access diagnosis. .

(6) Embodiment Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
6 is a detailed diagram of the data switching circuit 3 of FIG. 1, FIG. 4 is a detailed diagram of the read address switching circuit 4 of FIG. 1, and FIG. 5 is a detailed diagram of the read/write memory circuit 2 of FIG. 2 is a detailed diagram of the write control circuit 5 of FIG. 1. FIG.

As shown in FIG. 1, a read/write memory circuit 1 includes a 1-pit, 4-word read/write memory circuit 2, and a shift signal to switch between a shift path and a normal path to transfer data to the read/write memory circuit 2. and a data switching circuit 3 which outputs a data switching circuit 3, which switches between the stored write address of the read/write memory circuit 2 and the read address of the normal read/write memory circuit 2 according to the diagnostic signal. A read address switching circuit 4 which outputs a read address to 2, and an inverted value of the input data to be written to the word indicated by the write address to all words other than the one indicated by the write address by the above-mentioned cutoff signal. A write control circuit 5 is provided for writing or writing input data only to the word indicated by the write address.

As shown in FIG. 2, the read/write memory circuit 2 is a memory circuit that stores data signals 501, 502', 505, 504 using a write pulse signal 009 in accordance with write control signals 505, 506, 507, 508. 22.23.24.
25 and the output signals 221 from the memory circuits 22.23, 24.25 by decoding the read addresses 401 and 402.
Selection signals 211 and 21 for selecting one of ゜231.241 and 251 as the output signal of the read/write memory circuit 2
2°215.214, selection signals 221.231, 241, 251 and selection signals 211.
Input 212゜213.214 respectively and NAND
26.27, 28.29 that takes logic, and output signals 261, 271,
281. ,? 91 to read/write the signal from the memory circuit selected by the read address 401 and 402 through the NAND logic. Output signal 20 of the memory circuit 2
It is composed of a NAND gate 2A that generates a 1.

The gate switching circuit 6 receives a shift signal 00 as shown in FIG.
A gate 31 inputs a signal 3 and outputs a positive polarity signal 311 and a negative polarity signal 312 of the shift signal, and a positive polarity signal 311.
and the shift pass data signal 002, and the NAND gate 32, which inputs the negative polarity signal 312 and the normal pass data signal 001, and outputs the NAND signal, and the NAND gate 62. Output signal 321 and output signal 331 of NAND gate 33
and a NAND gate 34 which takes the NAND logic by inputting and outputs the data signal 301 to the read/write memory circuit 2. When the shift signal 003 is 1, the shift pass data signal 002 is set, and the shift signal 003 is set to 1. 00, the normal pass data signal 001 becomes the data signal 301 of the read/write memory circuit 2.

As shown in FIG. 4, the read address switching circuit 4 has a gate 41 which inputs the diagnostic signal 008 and outputs a positive polarity signal 411 and a negative polarity signal 412 of a cut-off signal, and a gate 41 which outputs a positive polarity signal 411 and a negative polarity signal 412, and a gate 41 which inputs the diagnostic signal 008 and outputs the write address 004, 005. Write address storage circuits 42 and 43 each store according to the write pulse signal 009, output signals 421 and 451 of the circuits 42 and 43, and positive polarity signal 4.
11 and a NAND game that takes NAND logic respectively) 44
, 45, NAND gates 46 and 47 which take NAND logic with the normal read addresses 006 and 007 and the negative polarity signal 412, respectively, and the output signal 44 of the NAND gate 44.
1 and the output signal 461 of the NAND gate 46, performs NAND logic, and outputs the read address 401.
ND gate 48 and output signal 45 of NAND gate 45
1 and the output signal 471 of the NAND gate 47, performs NAND logic, and outputs the read address 402.
When the diagnostic signal 0[]8 is 1, the write address 004. O'
05, and when the diagnostic signal 008 is O, the normal read addresses 006 and 007 become the read addresses 401 and 402 of the read/write memory circuit 2.

The write control circuit 5 receives a diagnostic signal 008 as shown in FIG.
a gate 51 which inputs the negative polarity signal 511 of the diagnostic signal, a decoder 52 which inputs the write address signals 004, 005 and generates decode signals 521, 522, 523, 524, and a decode signal 521°. 522.5
23. '524 and data switching circuit 3 data signal 3
01 and take exclusive Noah logic,
When the decode signal is 1, a positive polarity signal of the data signal 301 is generated, and when it is 0, a negative polarity signal is generated.
, 502, 503, 504 to the read/write memory circuit 2, respectively.
3, 55, 57.59 and decoded signals 521, 522
．． ．． 523 and 524 respectively to generate a negative polarity signal 54.
A game that outputs 1,561,581.5 AI) 54
, 56, 58.5A, the negative polarity signal 511 of the diagnostic signal, and the negative polarity signal 541 of the decode signal 561.581.5
Each takes NAND logic with AI, that is, when the diagnostic signal is 1 or when the decode signal output is 11, it generates 1, and outputs it to the read/write memory circuit 2 as a write control signal 505.506°5072.508. NAND'y
'-5B, 5'C, 5D, 5B,! : A color is formed.

Next, the operation of the present invention will be explained.
When 8 is 0, the read address switching circuit 4 sets the read addresses 401 and 402 to normal read addresses vy, 006, 09.
7 is selected, the write address 004.005 and the read addresses 401 and 402 operate on the read/write memory circuit 2 without affecting each other. Moreover, the write control signal makes writing possible only for the word selected by the write address.

When the diagnostic signal 008 is 1, the read address switching circuit 4 selects the read addresses 401 and 402 from the write address storage circuit 4.
2. Since t3 is selected, the read address is 401.40.
2 always indicates the latest write address where a write operation was performed. Therefore, once certain data is written to the read/write memory circuit 2, regardless of the write address, that data continues to be read until the next write. It appears as if the read/write memory circuit 1 is just a register without a write address or subsequent address. Furthermore, when the prohibition signal is 1, the write control and - control signals enable writing to all words, and all input data is inverted by the exclusive NOR gate except for the word indicated by the write address. . That is, when the diagnostic signal is 1 (during diagnosis), the written word continues to be read in the next write, and all other words are inverted values of the data of the written word.

This is effective for detecting failures in read/write memory circuits in shift bus type diagnosis using scan-in/out. If a read/write memory circuit is inserted in the middle of a shift path that connects multiple registers, there is a risk that the shift bus will be interrupted at this read/write memory circuit if a mismatch between the write address and the read address occurs. Conventionally, the address was fixed and only one word out of multiple words was accessed during diagnosis, but according to the present invention, all hoods can be accessed, and moreover, the address is fixed and only one word out of multiple words is accessed during diagnosis. Because words and other words are always written with inverted data, the read/write memory circuit randomly tests all words and addresses during diagnosis.

(7) Effects of the Invention As explained above, the present invention has a circuit that stores a write address and uses it as a read address during diagnosis, and a circuit that always inverts the word indicated by the write address and other words and the write data. Since this is added to a memory circuit having a shift bus, it is possible to perform diagnosis using a shift bus in which all write addresses can be randomly changed), and has the effect of being able to diagnose all addresses and all words of the memory circuit.

[Brief explanation of the drawing]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed diagram of the read/load memory circuit of FIG. 1, and FIG. 3 is a detailed diagram of the data switching circuit of FIG. 4 is a detailed diagram of the read address switching circuit of FIG. 1, and FIG. 5 is a detailed diagram of the write control circuit of FIG. 1. 1... Read/write memory circuit 2... Read/write memory circuit 3... Data switching circuit 4... Read address switching circuit, 5... Write control circuit 21.52... Decoders 22.23, 24.25...memory circuits 26, 27.
2B, 29.2A, 31.62.55.34°41
．． 44, 45, 46, 47, 48, 49, 51, 54゜56, 58.5A, 5B, 5C, sD, 5E...
・NAND gate 42.43...Write address storage circuit 53.55, 5
7゜59...Exclusive Noake Patent Applicant Nippon Electric Co., Ltd.

Claims (1)

[Claims] (1) In a read/write memory circuit comprising a plurality of words of memory, using one word of the memory as a shift path, and having an input data switching circuit that switches between the shift path and the normal path by a shift signal, the memory circuit a selection circuit that selects the storage circuit as the read address of the memory circuit when diagnosing based on a diagnostic signal and selects a normal read address when not diagnosing; When diagnosing, the signal writes the inverted value of the input data written to the word indicated by the write address to all words other than those indicated by the write address, and when not diagnosing, the inverted value of the input data written to the word indicated by the write address is written to all words other than the one indicated by the write address. A read/write memory circuit comprising a built-in write control circuit that writes input data only to words that have been read.