JPS58170117A - Serial/parallel-parallel/serial converting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a series-parallel/parallel-serial conversion circuit that can arbitrarily set the number of bits constituting an l word.

Prior Art and Problems] ゛When transferring data using a serial interface, data is transferred in units of words. For example, 1 word is 1
Consisting of 4 bits or 8 bits - In the prior art, 1. The number of bits of a word is fixed, and the word structure cannot be made usable. [Objective of the Invention] 9. The present invention is based on the above considerations, and An object of the present invention is to provide a serial-parallel/parallel-serial converter circuit in which the number of bits of - can be made variable.

[Structure of the invention]

Therefore, the serial-parallel/parallel-serial conversion circuit of the present invention has a shift register connected to a serial interface, and in the case of reception, when a set signal is generated, the data in the shift register is set and transmitted. In this case, a buffer register whose own data is set in the shift register when a set signal is generated, a shift signal generation circuit that generates a shift signal for the shift register, and a shift signal generation circuit that counts the shift signal. 2, a bit counter whose contents are cleared when a set signal is generated, a bit number setting circuit to which the number of bits constituting one word is set, and a bit counter whose contents are set to the number of bits constituting one word; The processor described in I above includes a set signal generation means for generating a set signal when the contents match, and a processor. Ya, t is the above pa, 7a0
．． The bit number setting circuit is characterized in that it is configured to be able to read and write the bit number setting circuit, and to set an arbitrary value in the bit number setting circuit.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, jlI! 2 is a time chart explaining the operation at the time of reception, and the third wA is a time chart explaining the operation at the time of transmission.

In Figure 1, 1 is a shift register, 2-O and 2-
1 is a buffer register, 3 is a shift signal generation circuit, 4
5 is a bit counter, 5 is a bit number setting n path, s is an i-cycloprocessor, and 7 is a comparison circuit.

The shift register 1 can be shifted either leftward or rightward, and is also capable of parallel data input and parallel data output. shift·
The serial input/output terminals of register 1 are connected to a serial interface.

The contents of shift register 1 are buffer register 2-0
and 2-IK are settable, and the contents of sofa registers 2-0 and 2-1 are
It can be set to . The shift signal generating means 3 is
It generates a shift signal for shift register 1. bit-color/ri4c, pip input to shift register l)? , or counts the number of bits output from the shift register 1, and this bit counter 3 is cleared by a set signal. In the bit number setting circuit 5, the number of bits constituting one word is set by the microprocessor 6.

The number of bits constituting one word is variable. Microprocessor 6 has buffer registers 2-0 and 2-1.
It is possible to write data to buffer Q registers 2-0 and 2-1 as well as read the contents of buffer Q registers 2-0 and 2-1. The microprocessor 6 also instructs whether to transmit or receive, etc. The comparison circuit 7 compares the contents of the bit counter 4 and the contents of the bit setting circuit 5, and outputs a set signal when the two match. Output. In the case of transmission, when the set signal is generated, buffer registers 2-0 and 2-
1 data is set in shift register 1, and in the case of reception, when a set signal is generated, shift register 1 is set.
The data is set in the sofa registers 2-0 and 2-1. At the time of reception, the serial input data is sequentially taken into shift register 1, and the contents of shift register 1 are set in the sofa registers 2-0 and 2-1. Moved to 2-0 and 2-1,
(The contents of sofa registers 2-0 and 2-1 are read by the microprocessor 6. At the time of transmission,
The microprocessor 6 writes data to sofa registers 2-0 and 2-1, sets the data in buffer registers 2-0 and 2-1 to shift register 1, and sets the data in shift register 1 to are sequentially output one bit at a time.The entire circuit shown in FIG. 1 is an LSL.

FIG. 2 is a time chart for explaining the operation at the time of reception. In the example shown in FIG. 2, it is assumed that one word is composed of 5 bits. As can be seen from FIG. 2, the serial input data is represented by a series of pulses, with logic "1" pulses having a long width and logic "0" pulses having a short width. A shift signal is generated at a time point in one pulse period. The serial input data is loaded into the shift register 1 bit by bit each time the signal is generated.

The contents of the bit counter 4 are incremented by 1 each time a shift signal is generated. When one word consists of 5 bits, the bit number setting circuit 5 has a numeric value @41. When the contents of the bit counter 4 become the number digit @4'', it becomes the same as the contents of the bit number setting circuit 5, so a set signal is generated, and the contents of the shift register 1 are transferred to the buffer register, register 2-0. 2-1 cod was transferred.

FIG. 3 is a tie chart for explaining the operation during transmission. Shift register 1 has buffer register 2
The contents of -0 and 2-1 are shifted, and the data in shift register 1 is output one bit at a time each time a shift 1 signal is generated. The format of the shift output data "i" is the same as the shift input data. In the example shown in Figure 1, one word is also composed of 5 bits. When the contents of bit counter 4 and bit number setting circuit 5 match, buffer register 2
The next word preloaded in -0 and 2-1 is placed in the shift register.

〔Effect of the invention〕

As is clear from the above explanation, the original 1jllKyore 1
For example, you can arbitrarily change the number of bits that make up one word1.
It becomes possible to

[[4. Brief explanation of the drawings] Figure 1 is a block diagram of one embodiment of the present invention, Figure 2 is a block diagram of one embodiment of the present invention.
The figure is a time chart explaining the operation at the time of reception, and FIG. 3 is the time chart explaining the operation at the time of transmission.

1... Shift register, 2-0 and 2-1... Buffer register, 3... Shift signal generation circuit, 4...
・Bit counter, 5...Bit number setting circuit, 6.
...r Microprocessor, 7... Comparison circuit.

License applicant: Fujitsu Limited Agent Bento Attorney Kyo Tani Yobe )

Claims (1)

[Claims] In the case of reception, when a set signal is generated, the data in the shift register is set to the shift register connected to the serial interface KII, and in the case of transmission, when a set signal is generated, the data in the shift register is set. The above shift/
A buffer register that is set in the register, a shift signal generation circuit for generating a shift signal for the shift register, and a bit counter that counts the shift signal and whose contents are cleared when a set signal is generated. a bit number setting time for setting the number of bits constituting one word; and set signal generation means for generating a set signal when the contents of the bit counter match the contents of the bit number setting time; a processor, wherein the i-processor is configured to be able to read and write the buffer register and set an arbitrary value to the bit number setting circuit. conversion circuit.