JPS58170012A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58170012A JPS58170012A JP5330182A JP5330182A JPS58170012A JP S58170012 A JPS58170012 A JP S58170012A JP 5330182 A JP5330182 A JP 5330182A JP 5330182 A JP5330182 A JP 5330182A JP S58170012 A JPS58170012 A JP S58170012A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon dioxide
- antimony
- substrate
- buried diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000010408 film Substances 0.000 claims abstract description 36
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 239000011521 glass Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000013039 cover film Substances 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 26
- 229910052787 antimony Inorganic materials 0.000 abstract description 16
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 abstract description 16
- 238000000034 method Methods 0.000 abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 13
- 239000000377 silicon dioxide Substances 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 239000007790 solid phase Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、埋没拡散領域を有する半導体装置を製造する
方法の改良に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to improvements in methods of manufacturing semiconductor devices having buried diffusion regions.
従来技術と問題点
埋没拡散領域を形成する技術の一つとして、同相拡散に
依るものが知られている。即ち、第1図に見られるよう
に、シリコン半導体基板1の埋没拡散領域形成予定部分
に例えばアンチモン・ガラス(Sbガラス)膜2を形成
し、次いで、熱処理を行なってアンチモンを基板1内に
拡散し、?型埋没拡散領域5を形成するものである。Prior art and problems As one of the techniques for forming a buried diffusion region, one based on in-phase diffusion is known. That is, as shown in FIG. 1, for example, an antimony glass (Sb glass) film 2 is formed on a portion of a silicon semiconductor substrate 1 where a buried diffusion region is to be formed, and then a heat treatment is performed to diffuse antimony into the substrate 1. death,? This forms a mold buried diffusion region 5.
ところが、前記のような技法を採った場合、不純物ソー
スであるアンチモン・ガラス膜2から、図に矢印で示し
であるようにアンチモンの外方拡散を生じ、基板10表
面に舊型不純物拡散層が形成されてしまう。その部分が
導電性になると素子間分離に支障を来たすことは云うま
でもない。However, when the above technique is adopted, antimony is diffused out from the antimony glass film 2 as an impurity source as shown by the arrow in the figure, and a hollow-shaped impurity diffusion layer is formed on the surface of the substrate 10. It will be formed. Needless to say, if that part becomes conductive, isolation between elements will be hindered.
そこで、次に、第2図に見られるような方法が考えられ
九。即ち、アンチモン・ガラス膜2の上に例えば窒化シ
リコンのカバー膜4を形成し、次いで、熱酸化を行なっ
て二酸化シリコン膜5を形成しつつアンチモン・ガラス
膜2からアンチモンの拡散を行なって%+型埋没拡散領
域3を形成するものである。Therefore, the next method that can be considered is the one shown in Figure 2. That is, a cover film 4 made of silicon nitride, for example, is formed on the antimony glass film 2, and then thermal oxidation is performed to form a silicon dioxide film 5, while antimony is diffused from the antimony glass film 2. This forms a mold buried diffusion region 3.
この技法に依ると、第1図に関して説明した外型不純物
拡散層は形成されないが、アンチモン・ガラス膜2、カ
バー膜4、二酸化シリコン膜5を除去した後の基板1は
第3図に見られるように段差五を有している。従来は、
この段差五を位置合せマークとして利用している。しか
しながら、本来、このような段差hB存在しない方が後
の工程の為には望ましい。According to this technique, the outer mold impurity diffusion layer described in connection with FIG. 1 is not formed, but the substrate 1 after removing the antimony glass film 2, the cover film 4, and the silicon dioxide film 5 can be seen in FIG. It has five steps like this. conventionally,
This step 5 is used as a positioning mark. However, it is originally desirable for the subsequent steps that such a step hB does not exist.
発明の目的
本発明は、埋没拡散領域な固相拡散で形成しても、半導
体基板表面に不所望の不純物拡散層や段差が形成される
ことのないように、また、位置合せマークも形感される
ようにするものである。Purpose of the Invention The present invention aims to prevent the formation of an undesired impurity diffusion layer or step on the surface of a semiconductor substrate even when a buried diffusion region is formed by solid-phase diffusion, and also to form alignment marks with a textured shape. The purpose is to ensure that
発明の実施施
第4図乃至第6図は本発明−実施例を説明する為の工程
要所に於ける半導体装置の要部断面図でToシ、次に、
これ等の図を参照しつつ説明する。Embodiment of the Invention FIGS. 4 to 6 are cross-sectional views of main parts of a semiconductor device at key points in the process for explaining embodiments of the present invention.
This will be explained with reference to these figures.
第4図参照
(1) シリコン半導体基板11上にアンチモン・ガ
ラスを塗布してアンチモン・ガラス膜12ヲ厚)
さ例えば2000 (、;:)程度に形成する。(See Figure 4) (1) Antimony glass is coated on the silicon semiconductor substrate 11 to make the antimony glass film 12 thick)
For example, it is formed to about 2000 (,;:).
(2) 化学気相堆積法に例えに二酸化シリコン膜1
5を厚さ例えば2000 (j)程度に成長させる。(2) Silicon dioxide film 1 as an example of chemical vapor deposition method
5 is grown to a thickness of, for example, about 2000 (j).
(3) フォト・リング2フイ技術にて二酸化シリコ
ン膜15のパターニングを行ない、埋没拡散領域形成が
不要である部分及び位置合せマーク形成予定部分に窓を
形成する。(3) The silicon dioxide film 15 is patterned using the photo ring 2-fi technique to form windows in areas where buried diffusion region formation is unnecessary and in areas where alignment marks are to be formed.
(4) 前記窓を介してアンチモン・ガラス膜12の
エツチングを行なって同様な窓を形成し、基板11の表
面を篇出させる。(4) Etching the antimony glass film 12 through the window to form a similar window and expose the surface of the substrate 11;
(5)フォト・レジストからなるマスク膜14を形成し
、これをパターニングして位置合せマーク形成予定部分
に窓を形成し、再びそこに基板11の表面を裏山させる
。伺、このときのカバー膜15に於けるパターンは然程
精密であることを要しない。(5) A mask film 14 made of photoresist is formed, and this is patterned to form a window in a portion where an alignment mark is to be formed, and the surface of the substrate 11 is again raised there. However, the pattern on the cover film 15 at this time does not need to be very precise.
161 基板11のエツチングを行ない位置合せマー
ク11,4を形成する。161 Etching the substrate 11 to form alignment marks 11 and 4.
第5図参照
(7) フォト・レジストのマスク膜14、二酸化シ
リコン膜13を除去する。See FIG. 5 (7) Remove the photoresist mask film 14 and silicon dioxide film 13.
(8)化学気相堆積法にて二酸化シリコンのカバー膜1
5を厚さ例えば2000 (A)程度に形成する。(8) Cover film 1 of silicon dioxide by chemical vapor deposition method
5 is formed to have a thickness of, for example, about 2000 (A).
第6図参照
(9) 温度1200 (C,l、時間40 (分〕
の熱処理を行なってアンチモン・ガラス膜12からアン
チモンを基板11中に拡散して@”ffi埋没拡散領域
16を形成する。See Figure 6 (9) Temperature 1200 (C, l, time 40 (minutes)
A heat treatment is performed to diffuse antimony from the antimony glass film 12 into the substrate 11 to form a buried diffusion region 16.
陶、前記実施例に於ける二酸化シリコン膜15はアンチ
モン・ガラス膜12をパターニングする為のマスクであ
るから他のマスク膜、例えば窒化シリョン膜などに代え
ても良い。まえ、二酸化シリコンのカバー膜15は、当
初、多結晶シリコン膜を形成し、それを酸化させたもの
であっても曳く、要は熱処理時に酸素が透過するもので
あれけ曳い。However, since the silicon dioxide film 15 in the above embodiment is a mask for patterning the antimony glass film 12, it may be replaced with another mask film, such as a nitride silicon film. The silicon dioxide cover film 15 may be a polycrystalline silicon film that is initially formed and then oxidized; in other words, it may be a film through which oxygen permeates during heat treatment.
発明の効果
以上の説明で判るように、本発明に依れば、不純物含有
ガラスをソースとする固相の埋没拡散領域形成方法を採
るものでありながら、表面は平坦に維持されるのて、後
の工程に不都合を招来することもなく、不所望の不純物
層も形成されないので特性良好な装置を製造することが
可能である。Effects of the Invention As can be seen from the above explanation, according to the present invention, although the method of forming a solid-phase buried diffusion region using impurity-containing glass as a source is adopted, the surface is maintained flat. Since no inconvenience is caused in subsequent steps and no undesired impurity layer is formed, it is possible to manufacture a device with good characteristics.
また、同時に、明確な位置合せマークを形成できるので
、後の工程、例えば分離領域の形成時の位置合せに困難
を感じることもない。Furthermore, since a clear alignment mark can be formed at the same time, there is no difficulty in alignment during subsequent steps, for example, when forming separation regions.
第1図乃至第3図は従来技術を説明する為の工程要所に
於ける半導体装置の要部断面図、第4図乃至第6図は本
発明一実施例を説明する為の工程要所に於ける半導体装
置の要部断面図である。
図に於いて、11はシリコン半導体基板、12はアンチ
モン・ガラス膜、13は二酸化シリコン膜、14はマス
ク膜、15はカッ(−膜、16はゞ型埋没拡散領域であ
る。
特許出願人 富士通株式会社1 to 3 are cross-sectional views of main parts of a semiconductor device at key process points for explaining the conventional technology, and FIGS. 4 to 6 are key process steps for explaining an embodiment of the present invention. 1 is a sectional view of a main part of a semiconductor device in FIG. In the figure, 11 is a silicon semiconductor substrate, 12 is an antimony glass film, 13 is a silicon dioxide film, 14 is a mask film, 15 is a cut-off film, and 16 is a ゜-shaped buried diffusion region. Patent applicant: Fujitsu Co., Ltd.
Claims (1)
K、前記半導体基板を選択的にエツチングして凹所から
なる位皺合せマークを形成し、次に、全面にカバー膜を
化学気相成長してから熱処理を行ない前記不純物源ガラ
ス膜より不純物を前記半導体基板に拡散して埋没拡散領
域を形成する工程が含まれてなることを特徴とする半導
体装置の製造方法。An impurity source glass film is selectively formed on the semiconductor substrate, and then the semiconductor substrate is selectively etched to form alignment marks consisting of recesses, and then a cover film is applied over the entire surface using chemical vapor. 1. A method of manufacturing a semiconductor device, comprising the step of performing heat treatment after phase growth to diffuse impurities from the impurity source glass film into the semiconductor substrate to form a buried diffusion region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5330182A JPS58170012A (en) | 1982-03-31 | 1982-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5330182A JPS58170012A (en) | 1982-03-31 | 1982-03-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58170012A true JPS58170012A (en) | 1983-10-06 |
Family
ID=12938897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5330182A Pending JPS58170012A (en) | 1982-03-31 | 1982-03-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58170012A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61195096A (en) * | 1985-02-25 | 1986-08-29 | Victor Co Of Japan Ltd | Color video signal recording and reproducing device |
US4757391A (en) * | 1985-02-28 | 1988-07-12 | Victor Company Of Japan, Ltd. | Helical scan type magnetic recording and reproducing apparatus recording multiple signals on multiple axially displaced tape tracks |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5512709A (en) * | 1978-07-12 | 1980-01-29 | Toshiba Corp | Manufactiring method of semiconductor device |
-
1982
- 1982-03-31 JP JP5330182A patent/JPS58170012A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5512709A (en) * | 1978-07-12 | 1980-01-29 | Toshiba Corp | Manufactiring method of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61195096A (en) * | 1985-02-25 | 1986-08-29 | Victor Co Of Japan Ltd | Color video signal recording and reproducing device |
US4757391A (en) * | 1985-02-28 | 1988-07-12 | Victor Company Of Japan, Ltd. | Helical scan type magnetic recording and reproducing apparatus recording multiple signals on multiple axially displaced tape tracks |
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