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JPS58169969A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58169969A
JPS58169969A JP57052096A JP5209682A JPS58169969A JP S58169969 A JPS58169969 A JP S58169969A JP 57052096 A JP57052096 A JP 57052096A JP 5209682 A JP5209682 A JP 5209682A JP S58169969 A JPS58169969 A JP S58169969A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
voltage
diode
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57052096A
Other languages
Japanese (ja)
Inventor
Shuichi Miura
秀一 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57052096A priority Critical patent/JPS58169969A/en
Publication of JPS58169969A publication Critical patent/JPS58169969A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60Impurity distributions or concentrations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes

Landscapes

  • Bipolar Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (t )発明の技術分野 本発明は半導体装置に係り、特にl’N接合よりなるダ
イオードを直列に′多段接続した半導体装置の特殊構造
に関する。
DETAILED DESCRIPTION OF THE INVENTION (t) Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a special structure of a semiconductor device in which diodes made of l'N junctions are connected in series in multiple stages.

(2)技術の背景 従来GaA、s(ガリウムヒ素) 、 G a、 A 
I A s(ガリウムアルミニウムヒ素)、1nP(イ
ンジウム燐)等を用いた集積化半導体装置内にPN接合
よりなるグイオートを直列接続した回路が多く用いられ
、通席シジソトキ、−バリアダイオード等か用いられ−
Cいる。しかし、このような直列接続グイオートを安定
に動作さ・せるためは大面積のショア)キーメタルを蒸
着する必要があり、集積化する場合の隘路となっていた
(2) Background of technology Conventional GaA, s (gallium arsenide), Ga, A
A circuit in which a group of PN junctions are connected in series in an integrated semiconductor device using IAs (gallium aluminum arsenide), 1nP (indium phosphide), etc. is often used. −
There is C. However, in order to operate such series-connected guides stably, it is necessary to deposit a large area of Shore key metal, which has been a bottleneck in integrating them.

(3)従来技術と問題点。(3) Conventional technology and problems.

第1図は直列に接続したダイオードを集積回路に組み込
んだB F L (Buffered FET Log
ic)回路で単位NORゲートを示すものである。
Figure 1 shows a BUF L (Buffered FET Log) that incorporates series-connected diodes into an integrated circuit.
ic) shows a unit NOR gate in the circuit.

上記BFL回路では電源としてプラスVC)C1とマイ
ナスVssの2電源を用いるが通常V9Dは数tOV、
−VSSはマイナス数■であるが出力端Cからの出力は
次段のNORゲートとなるために出力端Cの出力はマイ
ナス数■に下げる必要があり、このためF 15 TI
と出力端C間にダイオードの直列回路D+、D2.l)
3よりなる電圧シフターlを介在させ“Cいる。なお、
A、Bは入力端子を示4゛。
In the above BFL circuit, two power supplies, positive VC)C1 and negative Vss, are used as power supplies, but normally V9D is several tOV,
-VSS is a negative number ■, but since the output from the output terminal C becomes a NOR gate in the next stage, the output from the output terminal C needs to be lowered to a negative number ■.For this reason, F 15 TI
A series circuit of diodes D+, D2 . l)
A voltage shifter L consisting of 3 is interposed,
A and B indicate input terminals.

=一般に集積回路ではこのような電圧シフターを−1,
記回路に限らず多く利用するがこれらダイl−トとしζ
はショソトキーハリアダイオートに用いられ、その構造
は第2図に示す如く、半絶縁性基板2ヒに第1乃至第3
のダイオードD1.i)2゜D Jを構成するPN接合
層3.4を設け、各素イは晶抵抗層によって分離し、互
いのダイオ−1を直列接続するためには最初のダイオ−
FD+のPl−に形成した金属電極5及び最後のダイオ
ードD3のN層に形成した゛金属電極6に人力及び出力
端子7.8を接続するように構成されCいる。
= Generally, in integrated circuits, such a voltage shifter is set to −1,
Although it is often used not only in the circuit described above, these die l-
is used in the Shosotokhi Haria diode, and its structure is as shown in Fig. 2, in which the first to third
The diode D1. i) A PN junction layer 3.4 constituting the 2°D J is provided, each element is separated by a crystal resistance layer, and in order to connect the diodes 1 in series, the first diode
The power and output terminals 7.8 are connected to the metal electrode 5 formed on the Pl- of the FD+ and the metal electrode 6 formed on the N layer of the last diode D3.

このためにPN接合ダイオードを互いに分離する手段と
互いにダイオードを直列接続するための接続用ラインパ
ターンと金属電極5.6の形成が必要となり、大面積化
して集積化の障害となる欠点を有していた。
This requires the formation of a means for separating the PN junction diodes from each other, a connecting line pattern for connecting the diodes in series, and a metal electrode 5.6, which has the drawback of increasing the area and impeding integration. was.

(4)発明の目的 本発明は上記従来の欠点に鑑み、集積化において面積を
とらず金属電極配線を用いずに複数のダイオードを直列
接続した半導体装置を提供することを目的とするもので
ある。
(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide a semiconductor device in which a plurality of diodes are connected in series without taking up much space in integration and without using metal electrode wiring. .

(5)発明の構成 本発明の特徴とするところは、第1のPN接合のNl’
iiに接してN層層を配するとともに該N層層に接して
P1層を配し該P+層に接して第2のPN接合の2層を
接するように形成した接合構造としてなる半導体装置を
提供することである。
(5) Structure of the Invention The feature of the present invention is that Nl' of the first PN junction
A semiconductor device having a junction structure in which an N layer is disposed in contact with ii, a P1 layer is disposed in contact with the N layer, and two layers of a second PN junction are formed in contact with the P+ layer. It is to provide.

(El)発明の実施例 以下、本発明の実施例を図面によって説明する。(El) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

第3図は本発明の原理的構成を示すもので二つのPN接
合ダイオードD1及びD2を縦方向に直列接続したもの
である。
FIG. 3 shows the basic configuration of the present invention, in which two PN junction diodes D1 and D2 are connected in series in the vertical direction.

すなわち第1のダイオードD1は8層4とN層3よりな
り、該第1のダイオード[)IのNttiにはN+N層
1が接し、該N層層にP+層11を対接させ分離接続層
を構成し、さらに第2のダ・イオード1) 2 (D 
P M 4 ト該P ” rim 11を対接サセ、P
 IM 4 ニN層3を対接させて第2のダイオードl
)2を構成する。5及び6は第1及び第2の2層及びN
Nに形成し7た入出力端接続用の金属電極であり電飾1
2に接続される。一般には第1及び第2のダイオ−i’
D+、D2のPN接合に順方向バイアスされるように電
圧が印加され、第1及び第2のダ(1−トD+及びD2
の電圧−電流特性は第4図(alに示すダイオードの特
性13を示すが分離接IA1m Hl、 I 1にはI
Q  cm  以上の不純物をドープしCあるので第4
図+biに示すような直線的な特性14を示す。
That is, the first diode D1 consists of eight layers 4 and an N layer 3, the N+N layer 1 is in contact with the Ntti of the first diode [)I, the P+ layer 11 is in contact with the N layer, and an isolation connection layer is formed. and a second diode 1) 2 (D
P M 4 P ” rim 11, P
IM 4 The second diode l is placed in contact with the N layer 3.
) 2. 5 and 6 are the first and second two layers and N
It is a metal electrode for connecting the input and output terminals formed in the shape of N, and is an electric decoration 1.
Connected to 2. Generally, the first and second diodes i'
A voltage is applied to forward bias the PN junctions of D+ and D2, and the first and second D+ and D2
The voltage-current characteristics of the diode shown in Figure 4 (al) are shown in Figure 4 (al).
Since it is doped with impurities of Q cm or more, the fourth
It shows a linear characteristic 14 as shown in Figure +bi.

第5図は第3図に示すダイオードl)1及びl) 2が
分前接続層10.11を介して直列接続され、[1つバ
イアス電圧を与えないゼロバイアス時のハント図を示す
ものであり符号15はフェルミ−/III位を。
Figure 5 shows a Hunt diagram at zero bias when the diodes l)1 and l)2 shown in Figure 3 are connected in series via the connection layer 10.11 and no bias voltage is applied. Dovetail code 15 indicates Fermi/III rank.

16は伝導帯、17は充満帯を示す。第1及び第2のダ
イオードD+、D2に順方向バイアスとなる電圧が加え
られた場合に分離接続riilO,11は逆バイアスさ
れた状態となるが上記したようにN”+P+P+層、 
11に旧ozf cm−i以上の不純物をドーピングし
であるために分離接続110..11では第6図に示す
ようにP+層−の充満帯からはフェルミ−準位15以ト
となりことN1層の伝導帯に電子はトンネルする。
16 is a conduction band, and 17 is a charging band. When a forward bias voltage is applied to the first and second diodes D+ and D2, the separated connection riilO,11 becomes reverse biased, but as described above, the N''+P+P+ layer,
11 is doped with an impurity higher than the old ozf cm-i, so that the isolation connection 110. .. 11, electrons tunnel from the full band of the P+ layer to the Fermi level 15 or higher, as shown in FIG. 6, to the conduction band of the N1 layer.

ゆえに、ダイオードDI、D2が順方向バイアスされた
場合は分離接Vt層10.11を介して第4図(blに
示すように直線的な電圧−電流特性において電流を流す
ことができる。
Therefore, when the diodes DI and D2 are forward biased, current can flow through the isolation junction Vt layer 10.11 in a linear voltage-current characteristic as shown in FIG. 4 (bl).

一方、第1及び第2のダイオ−)’l) 1. I) 
2に逆バイアスが印加された場合は分離接続rIII0
,11のN”、F”層は順方向バイアスとなる。この場
合も第4図(blに示すにようにN層層、P+層間には
電流が流れる。すなわち、分離接続1iii10. I
Iは順、逆両方向のバイアスに対し°(金属配線の如く
同様に電流を流す。
On the other hand, the first and second diodes)'l)1. I)
If reverse bias is applied to 2, separate connection rIII0
, 11 are forward biased. In this case as well, current flows between the N layer and the P+ layer as shown in FIG.
I is biased in both forward and reverse directions (current flows in the same way as in metal wiring).

第7図は第1図に示ずFETIと3個のダイオードDI
、D2.D3を直列接続した電圧シフター1部分の半導
体装置(集積回路)を示すものである。第7図において
、半絶縁性基板18を部分的にエツチングし、エツチン
グを施した部分に分子線エピタキシャル(MBE)によ
って第1のダイオードD IのN層3として0.5p 
m厚で濃度10″cm’、P層4として1μmで濃度1
0/? cm−jの1ンN接合を形成し、該第1のダイ
オード1)tのPl−4上に不純物濃度が10 /F 
cm−jで厚さが0.3μmのPJt#11の分離接続
層SC+を形成し、さらにその−Lに不純物濃度が10
’ cro−’で厚さが0.3tt’mQ)N“1−1
OのPN層を形成する。以後第1のダイオ−Fと同じよ
うに第2のダイオ−F r、) 1.第20)分離接続
層SC2,第3のダイオ−1’ D Jを形成して電圧
シフター1の接合層を得る。
Figure 7 shows the FETI and three diodes DI, which are not shown in Figure 1.
, D2. This figure shows a semiconductor device (integrated circuit) of a voltage shifter 1 portion in which D3 are connected in series. In FIG. 7, a semi-insulating substrate 18 is partially etched, and a 0.5p N layer 3 of the first diode DI is formed on the etched portion by molecular beam epitaxial (MBE).
m thickness and concentration 10 cm', P layer 4 has a concentration of 1 μm and 1 μm.
0/? cm-j, and an impurity concentration of 10/F is formed on Pl-4 of the first diode 1)t.
A separation connection layer SC+ of PJt #11 with a thickness of 0.3 μm in cm-j is formed, and an impurity concentration of 10
'cro-' thickness is 0.3tt'mQ)N"1-1
A PN layer of O is formed. Thereafter, in the same way as the first diode F, the second diode F r, ) 1. 20th) A bonding layer of the voltage shifter 1 is obtained by forming a separation connection layer SC2 and a third diode-1' D J.

次にMBEした上記層の内で電圧シフターとなる部分と
FETIの活性層部分22のみ残して他をエツチングす
る。
Next, of the MBE-treated layer, only the portion that will become the voltage shifter and the active layer portion 22 of the FETI are left, and the rest are etched.

次に金属電極5. 6. 19.20としてA u (
J eを蒸着アロイし、次にSiO2をスパッタリング
によっ゛(成膜パターン形成して電圧シフター1とFE
T1間に8102層24を珍成し、該S i 02層2
41を電圧シフターlとFETIを橋絡するようにAu
等よりなる配線金属23を蒸着及びバターニングによっ
て形成する。なお21はショットキー金属電極である。
Next, metal electrode 5. 6. 19.20 as A u (
Je is vapor-deposited and alloyed, and then SiO2 is sputtered (film formation pattern is formed and voltage shifter 1 and FE
8102 layer 24 is formed between T1, and the S i 02 layer 2
41 to bridge the voltage shifter l and FETI.
A wiring metal 23 made of the like is formed by vapor deposition and patterning. Note that 21 is a Schottky metal electrode.

第8図は本発明の変形例を示すものであり第1のダイオ
ードDI及び第2のダイオ−F’ D 2の■)N接合
を1いに逆にして半絶縁性基板tuLに形成し、第1の
ダイオードD1と第2のダイオード1) 7 (2) 
P及びN層の側面に分離接続j−sc、のl)+及びN
+層11.10を介在さ−ロたちのであり回路形式によ
ってはこのように構成することが好ましい場合も生ずる
FIG. 8 shows a modification of the present invention, in which the N junctions of the first diode DI and the second diode F'D2 are reversed to 1 and formed on the semi-insulating substrate tuL, First diode D1 and second diode 1) 7 (2)
Separate connections j-sc, l) + and N on the sides of the P and N layers
+layers 11 and 10 are interposed, and depending on the circuit type, it may be preferable to configure in this manner.

F述の如く例えば3個のグイオートを直列接続すれば一
段、二段と増加する毎に直列回路両端の電圧は0.8V
 tI位で上昇し第9図に示すような電圧−電流特性を
示すことは明らかであり、多段構成すれば第9図の電流
−電圧特性における湾曲点をダイオードを直列接続した
段数倍だけ電圧を高い方向に移動させることが可能であ
る。
As mentioned in F, for example, if three guiots are connected in series, the voltage across the series circuit will be 0.8V each time the stage increases by one or two stages.
It is clear that the voltage rises at about tI and exhibits the voltage-current characteristics shown in Figure 9.If a multi-stage configuration is used, the curve point in the current-voltage characteristics shown in Figure 9 is increased by a voltage equal to the number of stages in which diodes are connected in series. It is possible to move it in a higher direction.

(7)発明の効果 以上、詳細に説明したように本発明によれば分子線エピ
タキシーによってI) N接合部間を分離接M層によっ
て金属電極を用いることなくエピタキシャル構造のまま
で積層または並設させることが0J能となるために小面
積内に電圧シフターを構成できるだけでなく金属電極間
を接続する導線が不用でプ11セスを簡略化できる等の
特徴を自”=1″る。
(7) Effects of the Invention As explained in detail above, according to the present invention, by molecular beam epitaxy, the I) N junctions can be stacked or placed in parallel with the epitaxial structure without using metal electrodes by separating and contacting the M layer. Since the voltage shifter has a 0J capability, not only can a voltage shifter be constructed within a small area, but also the process can be simplified by eliminating the need for conductive wires to connect between metal electrodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電圧シフターを用いた°回路の1例を小
ず回路図、第2図は第1[aに示−4電11ンソターを
構成する半導体装置の側断面図、第、3図は本発明の半
導体装置である電圧シフターの19即を説明するための
側断面図、第4図fa)は第;3図に小ずt導体装置中
のPN接合グイオートの電流 電r−E特性図、第4図
(blは第3図に示す分1iII接続1−0)P”l−
及びN層層が示す電流−電圧特性図、第5図は第3図の
半導体電圧シフターのバイアスをかけない場合のバント
図、第6図は分離接続1−古傍のトンネル効果を説明す
るためのバント図、第7図は本発明の半導体電圧シフタ
ーを築積回路に形成した場合の第1図回路図中のFE”
rlとの接続状態を示す側断面図、第8図は本発明の甲
導体電圧ジッターの他の実施例を示す側断面図、第51
図は第7図の電流−電圧特性を説明する特性図(ある。 l・・・電圧シフター、 2・・・半絶縁性基板、 I
)l、D2.D3・・・ダイオード、 3−−−Nr*
、 4−・・P’ifA、 5.6・−・M属電極、 
10・・・N層層、 11・・・P1層、12・・・電
源、 15・・・フェルミ−準位、 16・・・伝導帯
、 17・・・充満帯、 18・・・半絶縁性基板、 
19.20・・・金属電極、 24・・・5iO2rl
ii。 特許出願人  富士通株式会社
Fig. 1 is a small circuit diagram of an example of a circuit using a conventional voltage shifter, Fig. 2 is a side sectional view of a semiconductor device constituting the soter shown in Fig. The figure is a side sectional view for explaining the voltage shifter, which is a semiconductor device of the present invention. Characteristic diagram, Fig. 4 (bl is the minute 1iII connection 1-0 shown in Fig. 3) P"l-
and the current-voltage characteristic diagram shown by the N layer, Figure 5 is a Bunt diagram of the semiconductor voltage shifter in Figure 3 when no bias is applied, and Figure 6 is to explain the tunnel effect in the separation connection 1-old neighborhood. FE in the circuit diagram of FIG. 1 when the semiconductor voltage shifter of the present invention is formed in a built-in circuit.
FIG. 8 is a side sectional view showing another embodiment of the A conductor voltage jitter of the present invention; FIG.
The figure is a characteristic diagram explaining the current-voltage characteristics of Fig. 7. l...voltage shifter, 2... semi-insulating substrate,
)l, D2. D3...diode, 3---Nr*
, 4-...P'ifA, 5.6...M-group electrode,
10...N layer, 11...P1 layer, 12...power supply, 15...Fermi level, 16...conduction band, 17...full band, 18...semi-insulating sexual substrate,
19.20...metal electrode, 24...5iO2rl
ii. Patent applicant Fujitsu Limited

Claims (1)

【特許請求の範囲】 (1)第1のPN接合のN層に接してN層層を配すると
共に該N層層に接してP+層を配し該P+層に接して第
2のPN接合のP層を接するように形成した接合構造と
してなることを特徴とする半導体装置。 (2)第1及び第2.第2及び第3.・・・、第n−1
及び第nのPN接合間にN層層及びP+層よりなる分離
接続層を介在させてなることを特徴とする特許請求の範
囲第1項記載の半導体装1L(3)分子線エピタキシー
によってPN接合及びN ” 1473及びP+層を形
成してなることを特徴とする特許請求の範囲第1項及び
第2項記載の半導体装置。 (4)N層層及びP+層をPN接合の主面で接するよう
に配設してなることを特徴とする特許請求の範囲第1項
及び第2項記載の半導体装置。 (5)N層層及びP+層PN接合の側面で接するように
配設してなることを特徴とする特許請求の範囲第1項及
び第2項記載の半導体装置。
[Claims] (1) An N layer is arranged in contact with the N layer of the first PN junction, a P+ layer is arranged in contact with the N layer, and a second PN junction is arranged in contact with the P+ layer. 1. A semiconductor device characterized in that the semiconductor device has a junction structure in which P layers are formed so as to be in contact with each other. (2) First and second. 2nd and 3rd. ..., n-1st
and the n-th PN junction, a separation connection layer consisting of an N layer and a P+ layer is interposed between the semiconductor device 1L (3) and the n-th PN junction by molecular beam epitaxy. and N'' 1473 and a P+ layer. (4) The N layer and the P+ layer are in contact with each other at the main surface of the PN junction. The semiconductor device according to claims 1 and 2, characterized in that the semiconductor device is arranged as follows. A semiconductor device according to claims 1 and 2, characterized in that:
JP57052096A 1982-03-30 1982-03-30 Semiconductor device Pending JPS58169969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052096A JPS58169969A (en) 1982-03-30 1982-03-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052096A JPS58169969A (en) 1982-03-30 1982-03-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58169969A true JPS58169969A (en) 1983-10-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052096A Pending JPS58169969A (en) 1982-03-30 1982-03-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58169969A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989011734A1 (en) * 1988-05-21 1989-11-30 Robert Bosch Gmbh Manufacture of diodes
JP2020161661A (en) * 2019-03-27 2020-10-01 富士通株式会社 Compound semiconductor device and manufacturing method therefor, and detector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989011734A1 (en) * 1988-05-21 1989-11-30 Robert Bosch Gmbh Manufacture of diodes
JP2020161661A (en) * 2019-03-27 2020-10-01 富士通株式会社 Compound semiconductor device and manufacturing method therefor, and detector

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