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JPS5816596A - High density multilayer circuit board - Google Patents

High density multilayer circuit board

Info

Publication number
JPS5816596A
JPS5816596A JP11549881A JP11549881A JPS5816596A JP S5816596 A JPS5816596 A JP S5816596A JP 11549881 A JP11549881 A JP 11549881A JP 11549881 A JP11549881 A JP 11549881A JP S5816596 A JPS5816596 A JP S5816596A
Authority
JP
Japan
Prior art keywords
multilayer wiring
multilayer
wiring board
signal line
main body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11549881A
Other languages
Japanese (ja)
Inventor
矢部 勝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11549881A priority Critical patent/JPS5816596A/en
Publication of JPS5816596A publication Critical patent/JPS5816596A/en
Pending legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は高密度多層配線基板、411に配線パターンの
電気抵抗および信号線−電源間の電気容量が低く寸法精
度が良好な外部端子ビン付高書度゛多層配線基板の構造
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a high-density multilayer wiring board, 411, a high-density multilayer wiring board with external terminal bins, which has low electrical resistance of wiring patterns and low capacitance between signal lines and power sources, and has good dimensional accuracy. Regarding the structure of

近年電子計算機の発達によシ、高速演算回路においては
演算速度の向上および高密度化の要請が増大している。
In recent years, with the development of electronic computers, there has been an increasing demand for improved calculation speed and higher density in high-speed calculation circuits.

この要請を満たすために信号線を多層化した多層配線基
板が用いられているが、こO場合、高速演算には基板上
の信号線−電源パターン量の電気容量の低下、信号線の
電気抵抗の低下を実現することが必要である。また多層
配線基板に高密度に集積回路をIIF載する丸め、多層
配線基板は多数の外部端子を有する必要がある。
In order to meet this requirement, multilayer wiring boards with multiple layers of signal lines are used. It is necessary to achieve a reduction in In addition, the multilayer wiring board, in which integrated circuits are mounted on the multilayer wiring board at high density, needs to have a large number of external terminals.

とζろでこのような多層配線基板を、Mo(モリブデン
)、W(タングステン)等の耐熱金属を導体層として用
いたグリーンシート法による多層セラミック基板で構成
しえ場合、セラ電ツタ材料の比誘電率が大きいため(S
2%アルミナ基板で8〜!l)、信号線−電源間の電気
容量を低くする−ことができない。まえ、Mo%W等耐
熱金属は電気抵抗が非常に大きいという欠点がある0例
えば鋼ノ固有抵抗x、yxlo’o・m(20℃)に対
し、M。
If such a multilayer wiring board can be constructed from a multilayer ceramic board using the green sheet method using heat-resistant metals such as Mo (molybdenum) and W (tungsten) as conductor layers, the Because the dielectric constant is large (S
8~ with 2% alumina substrate! l) It is not possible to lower the capacitance between the signal line and the power supply. First, heat-resistant metals such as Mo%W have the disadvantage of extremely high electrical resistance.For example, compared to the specific resistance of steel x,yxlo'o·m (at 20°C), M.

で5.6X1(r’Ω・1(20℃)、Wでs、5xt
r”Ω・cx (20℃)である。さらK MQ 、Y
は酸化しやすいため空気中で実温にさらすことができな
く、ま九焼き縮み率のコントロールが雛かしいため、寸
法精度が悪いという欠点がある。
at 5.6X1 (r'Ω・1 (20℃), W at s, 5xt
r”Ω・cx (20℃). Moreover, K MQ , Y
Since it is easily oxidized, it cannot be exposed to actual temperature in the air, and the shrinkage rate during baking is difficult to control, resulting in poor dimensional accuracy.

本発明の目的は、このような欠点をなくシ、信号線の電
気抵抗および信号線−電源間の電気容量が低くま九基板
本体の裏面全体に外部端子用ビンを形成して多数個の外
部端子接線の接続が可能な寸法精度のよい高精度多層配
線基板を提供するところKある。
It is an object of the present invention to eliminate such drawbacks, reduce the electric resistance of the signal line and the electric capacitance between the signal line and the power source, and form external terminal bins on the entire back surface of the board main body to connect a large number of external terminals. There are several companies that provide high-precision multilayer wiring boards with good dimensional accuracy that allow connection of terminal tangents.

この目的のために本発明に係る高密度多層配線基板は、
MO%W等耐熱金属を導体層として表層および内層に有
する多層セラミック基板本体の表面に、’t(チッソ)
−囲気焼成可能1k Cu (銅)導体、比誘電率の低
いガラスもしくはガラスとセラミックの混合による絶縁
層用無機物ペースF1抵抗体ペーストのうち全部ま九は
一部を厚膜印刷法および(tたは)フォトリソグラフィ
ック法で配線島信号線を多層化し、前記基板本体の裏面
に外部端子としての複数個のビンを形成したものである
For this purpose, the high-density multilayer wiring board according to the present invention is
't (Chisso) is applied to the surface of the multilayer ceramic substrate body, which has a heat-resistant metal such as MO%W as a conductive layer on the surface and inner layers.
- Inorganic paste for insulating layer F1 resistor paste made of 1K Cu (copper) conductor, low dielectric constant glass or a mixture of glass and ceramic which can be fired in an atmosphere 2) Wiring island signal lines are multilayered using a photolithographic method, and a plurality of vias as external terminals are formed on the back surface of the substrate body.

以下、本発明を、図面を参照、しながら、実施例につい
て説明する。
Hereinafter, the present invention will be described by way of embodiments with reference to the drawings.

第1図は本発明の第1の実施例に係る多層配線基板の概
略的な縦断面図である。グリーン?−ト法を用いて製造
し九多層セラミック基板本体IL内層パターンとしてW
を導体とする第1電源層2およびII2電源層3を有し
、この基板本体の表面から裏面に達する信号線用貫通ヴ
イア4および電源用貫通グイア5を有する。電源用貫通
ヴイア5は符号6で示す如く各電源層2.3の電源パタ
ーンと接続されている。まえ前記基板本体10表面には
上部形成パターンとの接続部パッド8、裏面には外部端
子用ビン14が取付パッド7を介して符号13で示す如
く半田付けされている。さらに基板本体10表面にはC
uペーストを厚膜印刷法によりパターン化しこれを夏!
雰囲気焼成するかまたはメッキ法によシ形成し九〇u配
線パターン9が有り、この配線パターンの層間は比誘電
率の低いガラスおよびセラミックを素材としてn、 を
囲気焼成用絶縁ペーストを用い厚膜印剣法またはフォト
リソグラフィック法によりパターン化しM。
FIG. 1 is a schematic longitudinal sectional view of a multilayer wiring board according to a first embodiment of the present invention. green? - W as the inner layer pattern of the IL of the main body of the multilayer ceramic substrate manufactured using the method
It has a first power supply layer 2 and an II2 power supply layer 3 which are conductors, and has a signal line through via 4 and a power supply through via 5 which reach from the front surface to the back surface of the substrate main body. The power supply through via 5 is connected to the power supply pattern of each power supply layer 2.3 as shown by reference numeral 6. On the front surface of the board main body 10, there are soldered pads 8 for connection to the upper forming pattern, and on the back surface, external terminal pins 14 are soldered via mounting pads 7, as shown by reference numeral 13. Furthermore, the surface of the board body 10 has C
Pattern U paste using thick film printing method and make it summer!
There is a 90μ wiring pattern 9 formed by firing in an atmosphere or by a plating method, and between the layers of this wiring pattern, a thick film is formed using an insulating paste for firing in an atmosphere. M made into a pattern using the seal method or photolithographic method.

雰囲気焼成した絶縁層12が有り、さらにその最上面に
はICC搭載用ICリードポンディダグパッド11同ダ
イパッド10を有する。第2図は第一1図に示す実施例
の高密度多層配線基板上1fCXC15を搭載した状態
を示し友ものである。符号16け工C15のリードであ
る。
There is an insulating layer 12 fired in an atmosphere, and furthermore, an IC lead pond pad 11 and a die pad 10 for mounting an ICC are provided on the uppermost surface thereof. FIG. 2 shows a state in which the 1fCXC15 is mounted on the high-density multilayer wiring board of the embodiment shown in FIG. 11. This is the lead with the code 16 wire C15.

第3図は本発明の第2の実施例を示した多層配線基板の
縦断面図である。この実施例では前記第1の実施例の多
層配線基板にさらにN、雰囲気焼成で形成し九〇u抵抗
体用電極17.18とN!・雰囲気焼成用抵抗体ペース
トで形成した抵抗体19を有し丸構成となっている。第
4図は第3図に示した第2の実施例の抵抗体付き高密度
多層配線基板上にXCl3を搭載した例である。
FIG. 3 is a longitudinal sectional view of a multilayer wiring board showing a second embodiment of the present invention. In this embodiment, N! is further formed on the multilayer wiring board of the first embodiment by firing in an atmosphere to form 90μ resistor electrodes 17, 18 and N! - It has a circular configuration and has a resistor 19 formed from a resistor paste for atmosphere firing. FIG. 4 shows an example in which XCl3 is mounted on the high-density multilayer wiring board with resistors of the second embodiment shown in FIG.

本発明は以上説明した如く、空気中で酸化しゃすいW導
体をもちかつ寸法精度の悪い多層セラミック基板表面上
に、Cu配線パターンおよび比誘電率の低い絶縁層を用
いて寸法精度の喪い厚膜印刷法または7オトリソグラフ
イツク法でパターン化しかつw、 11囲気焼成しだ多
層配線を補完することにより、寸法精度がよく、配線パ
ターンの電気抵抗および信号線−電源間の電気容量が低
く、基板本体の裏面に多数個の外部端子ビンを有する高
密度な多層配線基板が得られる効果がある。
As explained above, the present invention uses a Cu wiring pattern and an insulating layer with a low dielectric constant on the surface of a multilayer ceramic substrate that has a W conductor that easily oxidizes in the air and has poor dimensional accuracy, thereby reducing the dimensional accuracy of the thick film. By patterning using a printing method or an otolithographic method and complementing the multilayer wiring by baking in an atmosphere, the wiring pattern has good dimensional accuracy, the electrical resistance of the wiring pattern and the electrical capacitance between the signal line and the power supply are low, and This has the effect of providing a high-density multilayer wiring board having a large number of external terminal bins on the back surface of the main body.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本−発明の1実施例に係る高密度
多層配線基板の縦断面図、第3図および鞘4図は本発明
の他の実施例を示した縦断面図である。 1・・・多層セライック基板本体、 2・・・第1電源層、   3・・・第2電源層、4・
・・信号線用貫通ヴイア、 5・・・電源用貫通ヴイア、9・−・Cu配線パターン
、12・・・h雰囲気焼成用絶縁ペーストによる無機物
絶縁層、 14・・・外部端子用ビン・ 代理人 弁理士 染 川 利 吉
1 and 2 are longitudinal cross-sectional views of a high-density multilayer wiring board according to one embodiment of the present invention, and FIG. 3 and sheath 4 are longitudinal cross-sectional views showing other embodiments of the present invention. . DESCRIPTION OF SYMBOLS 1...Multilayer ceramic board main body, 2...1st power layer, 3...2nd power layer, 4...
...Through via for signal line, 5...Through via for power supply, 9...Cu wiring pattern, 12...Inorganic insulation layer made of insulating paste for h atmosphere firing, 14...Bin/substitute for external terminal People Patent Attorney Rikichi Somekawa

Claims (1)

【特許請求の範囲】[Claims] 耐熱金属を導体層として表層および内層に有する多層重
ラミック基板本体の表両に、銅導体と低地−電率の無機
物絶縁層とを配置して多層信号線を形成し、前記基板本
体の裏面に複数個の外部端子用ビンを設けえことを特徴
とする高密度多層配線基板。
A copper conductor and an inorganic insulating layer with low electrical conductivity are arranged on both surfaces of a multilayer laminated laminated board main body having heat-resistant metal as a conductive layer on the surface and inner layers to form a multilayer signal line, and a multilayer signal line is formed on the back surface of the board main body. A high-density multilayer wiring board characterized by being able to provide a plurality of external terminal bins.
JP11549881A 1981-07-23 1981-07-23 High density multilayer circuit board Pending JPS5816596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11549881A JPS5816596A (en) 1981-07-23 1981-07-23 High density multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11549881A JPS5816596A (en) 1981-07-23 1981-07-23 High density multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS5816596A true JPS5816596A (en) 1983-01-31

Family

ID=14663992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11549881A Pending JPS5816596A (en) 1981-07-23 1981-07-23 High density multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS5816596A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047496A (en) * 1983-08-26 1985-03-14 日立化成工業株式会社 Ceramic board
JPS60178695A (en) * 1984-02-17 1985-09-12 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Electric mutual connecting package
JPS61149336U (en) * 1985-03-06 1986-09-16
JPH0316247A (en) * 1989-06-14 1991-01-24 Hitachi Ltd Package for semiconductor element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS5686204A (en) * 1979-12-14 1981-07-13 Bergens Mek Verksted Hydraulic pressure control valve gear

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5586195A (en) * 1978-12-25 1980-06-28 Fujitsu Ltd Method of fabricating multilayer circuit board
JPS5686204A (en) * 1979-12-14 1981-07-13 Bergens Mek Verksted Hydraulic pressure control valve gear

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6047496A (en) * 1983-08-26 1985-03-14 日立化成工業株式会社 Ceramic board
JPS60178695A (en) * 1984-02-17 1985-09-12 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Electric mutual connecting package
JPS61149336U (en) * 1985-03-06 1986-09-16
JPH0316247A (en) * 1989-06-14 1991-01-24 Hitachi Ltd Package for semiconductor element

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