JPS58164094A - Memory test method - Google Patents

Abstract

PURPOSE:To speed up the test and clarify faulty memory area, by selecting one address for every line of IC memory chips and checking the normality of every chip line by performing reading and writing to the selected addresses. CONSTITUTION:In the case of confirming the normality of memory 2, each IC chip line can be checked without omission at a high speed by performing the same test on all IC memory chip lines after changing the address so as to perform the test on all chip lines, instead of performing the test only on one address X.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory testing method in a system equipped with a processor and a memory IJY, and more particularly to a memory testing method suitable for use when restarting the system.

When restarting operation of an electronic converter system, etc., a memory test is performed, but in the conventional test method, the memory is read and written at one location for each special electric block size of the installed memory.
Either read and write 2 to the entire memory area and compare the input and output data, and check the normality of the memory (parity error, parity error,
I was checking the memory (NOASW). However, this conventional method has the disadvantage that it is impossible to confirm the normality of all memories and that it takes time to complete the confirmation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory testing method that eliminates the above-mentioned drawbacks of the prior art, allows high-speed testing, and clarifies faulty memory areas.

In the present invention, each IC memory chip column [1
This feature is characterized in that addresses are selected one by one and the normality of each chip row is checked by reading and writing to these selected addresses.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 1 shows an example of a memory configuration as a test target of the present invention.
0 to A'16 is one IC memory chip row, for example 1
I have a word 8 jl n M on 6th.

Each word is arranged with one pit in each of AO to A16. One word has a 17-bit structure consisting of 16 bits and a parity bit. Other IC memory chip rows BO to B16
．． The same goes for CO~C16, Do~DI6, for example,
There are 16×4=64 words.

When checking the normality of memory 2 like this.

If the test is performed only on one address cannot be checked.

Therefore, in the present invention, this test 2 is performed once for all chip rows by changing the address and performing a similar test for all IC memory chip rows to quickly check the generality of the entire memory. It is something to do.

FIG. 2 shows a memory address control method for performing such address selection 7. The memory address to be tested is the memory control device 1 that performs normal memory address control 7.
depends on the chip row selection method. Therefore, access address information ADD~AD1 from the central control unit (CPU) is now
5 (16 bits here), the lower 2 bits (ADD.

ADl)'4 If it is used as chip column information, the check address ADCH is (ADl, ADO
) = 0.1, 2.3, it is possible to access all chips one by one and test each chip individually. In this case, the top 14 bits of address information from the CPU (AD2 to AD corresponding to words in 16)
15 (14 bits) is the address ADC in each chip column.
Indicate XY finger as HP.

Figures 3A to 3C show a checking method using specified addresses. For the four addresses mentioned above, a certain pattern of data nryr is sent, the same address information is output again to obtain data DRY, and this input/output data is D1. D
Compare R. FIG. 5A shows the read data DR when the input data DI is all 0 (the numerical value is 16 bits 'jgr: 4 digits in hexadecimal; the same applies hereafter) or 1.
are exactly the same.

If normal! It shows. In the case of FIG. 3B, for the same input data Dr, an overflow occurs in the 8th bit from the bottom in the corresponding address of any IC memory tech, and this position can be easily detected from the comparison result.

Regarding the parity pit, input data DI in which 1 is set in the parity pit, that is, a numerical value such as 1.3, is input to check the result of the parity check. If there is a parity error, an IC chip abnormality in the parity pit is detected. (However, if the data part has already been checked). This case is the third
This is shown in Figure C.

It goes without saying that one or more checks and address selection can be easily realized through processing by CPH.

According to the above method, for example, one chip 16 has a word I
When using a 64-word memory using C memory, the present invention can check all memory chips by testing at four locations, so compared to the all-address check method, the time required is 16x.
It is possible to scroll 10 times faster. Furthermore, in the method of only checking only one place, there are areas that cannot be checked, but according to the present invention, this is not a concern.

As is clear from the above description, according to the present invention, each IC chip array can be processed at high speed and without exception.

It has the effect of being able to tsuku.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a memory to which the present invention is applied, FIG. 2 is a diagram showing a memory address control method for carrying out the method of the present invention, and FIGS. 3A to 3C are diagrams showing a checking method. It is an explanatory diagram. An~A16, BO~B16, Co~CI
6, Do ~D16・IC memory chip, ADO~
AD15...Access memory address, 1...Memory control device.

Claims (1)

[Claims] IC Memo IJ 7. - Checking the normality of the IC memory by selecting at least one address for each constituent IC chip and comparing the input test data and the read data for each selected address. A memory testing method featuring several features.