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JPS58163045A - Program counter control device - Google Patents

Program counter control device

Info

Publication number
JPS58163045A
JPS58163045A JP4584682A JP4584682A JPS58163045A JP S58163045 A JPS58163045 A JP S58163045A JP 4584682 A JP4584682 A JP 4584682A JP 4584682 A JP4584682 A JP 4584682A JP S58163045 A JPS58163045 A JP S58163045A
Authority
JP
Japan
Prior art keywords
loop
program
register
program counter
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4584682A
Other languages
Japanese (ja)
Inventor
Takeshi Shinoki
剛 篠木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4584682A priority Critical patent/JPS58163045A/en
Publication of JPS58163045A publication Critical patent/JPS58163045A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To shorten the processing time covering from the end through the initiation of a loop, by adding a simple hardware to reset the end to the initiation of the loop when the program of the loop is executed repetitively and many times. CONSTITUTION:Two registers 14 and 15 are provided to control the value of a program. The start address BRTOREG of a loop and an address 200 are set previously to the register 14; while the end address 300 of the loop is set to the register 15, respectively. Then the contents of the register 15 are fed to a comparator 16 together with the output of a program counter replacing circuit 13. When coincidence is obtained between the contents of the register 15 and the circuit 13, 1 is delivered to reset an adder 11 and then set the contents of the register 14.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明はプログラムカウンタ方式のデジタル計ＪＩｌｄ
Ａニおいて、ループのプログラムを高速実行するプログ
ラムカウンタ制御装置に関するものである。Detailed Description of the Invention (1) Technical field of the invention The present invention relates to a program counter type digital meter JIld.
A and D relate to a program counter control device that executes a loop program at high speed.

（２）従来技術と問題点 （１） 従来、プログラムカウンタを用いてプログラムの命令を
順次実行するデジタル計算機が多用されダラムの始めの
アドレス（２００）と終りのアドレス（３００）間を繰
り返す時、終シのアドレス（６００）に漣すると通常の
命令と同様にプログラムメモリからブランチループ（Ｂ
ＲＡＮＣｆ（ＬＯＯＰ）命令を読出しデコードしプログ
ラムカウンタを歩進し再びループの始めに戻る。しかし
このループを構成する手ノ員が短かく、まわる回数が多
いときブランチ命令を実行する時間が相対的にかな）の
オーバヘッドを占めてしまう。(2) Prior art and problems (1) Conventionally, digital computers that sequentially execute program instructions using a program counter are often used, and when repeating between the start address (200) and end address (300) of Durham, When written to the end address (600), the branch loop (B
The RANCf (LOOP) instruction is read and decoded, the program counter is incremented, and the process returns to the beginning of the loop. However, when the number of members making up this loop is short and the number of loops is large, the time it takes to execute branch instructions takes up a relatively large amount of overhead.

これに対し、本発明者はブランチ命令の処理によらずハ
ードウェアで繰返しを制御し高速化することを考えたも
のである。In response to this, the inventor of the present invention considered increasing the speed by controlling repetition using hardware instead of processing branch instructions.

（３）発明の目的 本発明の目的はループのプログラムの手順が短かく多数
回繰返す場合、ハードウェアを用いて繰返しの時間を短
縮するようにしたプログラムカラ（２） ンタ制御装置を提供することである。(3) Object of the Invention The object of the present invention is to provide a program controller that uses hardware to shorten the repetition time when a loop program procedure is short and repeated many times. It is.

（４）発明の構成 前記目的を達成するため、本発明のプログラムカウンタ
制御装置はプログラムカウンタを用いてプログラムの命
令を順次実行するデジタル計算機において、ループのプ
ログラムを実行するため、該ループの始めと終シのアド
レスを設定するレジスタと、該レジスタとプログラムカ
ウンタの内容の一致を検出しループのプログラムの終シ
から始めに戻すように制御する手段とを具えたことを特
徴とするものである。(4) Structure of the Invention In order to achieve the above object, the program counter control device of the present invention executes a loop program in a digital computer that uses a program counter to sequentially execute program instructions. The present invention is characterized by comprising a register for setting the end address, and means for detecting a match between the contents of the register and a program counter and controlling the loop to return from the end to the beginning of the program.

（５）発明の実施例 第２図は本発明の実施例の構成説明図でるる。(5) Examples of the invention FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention.

同図において、従来のプログラムカウンタ方式のデジタ
ル計ＪＩ機では、加算器１１とプログラムカウンタ（Ｐ
Ｃ）１２とプログラムカウンタ更新回路１６より成るプ
ログラムカウンタ回路を設け、加算器１１からたとえば
第１図に示す繰返しループのプログラムの始めのアドレ
ス（２００）を入力してＰＣｌ３をセットし、順次ルー
プのプログラムの命令の入力（３） 毎にＰＣｌ３がプログラムカウンタ更新回路１６によシ
＋１歩進され、順次プログラムが実行される。そして、
ループのプログラムの終シのアドレス（３００）に達す
ると、ＢＲＡＭＣｆ（ＬＯＯＰ命令によシ再び始めのア
ドレス（２００）が読出され、ループのプログラムの実
行が繰返えされる。本発明ではこのＢＲＡＮＣＨＬＯＯ
Ｐ命令の実行手順を省きハードウェアでループの終シを
始めに戻すように制御し高速化を図ったものである。In the same figure, in the conventional program counter type digital meter JI machine, an adder 11 and a program counter (P
C) A program counter circuit consisting of 12 and a program counter update circuit 16 is provided, and the start address (200) of the repeat loop program shown in FIG. Each time a program command is input (3), PCl3 is incremented by +1 by the program counter update circuit 16, and the program is sequentially executed. and,
When the end address (300) of the loop program is reached, the start address (200) is read again by the BRAMCf (LOOP instruction), and the execution of the loop program is repeated.In the present invention, this BRANCHLOO
The execution procedure of the P instruction is omitted and the end of the loop is controlled by hardware to return to the beginning, thereby increasing the speed.

そのため、同図に示すように、プログラムからその１直
を制御できる２つのレジスタ１４．１５　’ｔ−１ｆＱ
ｆｆ、レジスタ１４にはループの始めのアドレス（ＢＲ
ＴＯＲＥＧ　）　、たとえば第１図のアドレス（２００
）を、レジスタ１５にはループの終シのアドレス（ＢＲ
ｆｉ’ＲＯＭＲＥＧ）、たとえば第１図のアドレス（３
００）をセットしておく。そしてレジスタ１５の内容を
プログラムカウンタ更新回Ｍ！５１３の出力とともに比
較回路１６に入力し、この両者の内容が一致した時”１
″を出力し、加算器１１をリセットしてレジスタ１４の
内容をセットする。従ってプログラムからレジスタ１４
゜（４） １５にセットされるループの始めと終シのアドレスが変
らない限シ、このループのプログラムの実行がハードウ
ェアにより自動的に繰返えされ、高速化の目的が達せら
れる。Therefore, as shown in the same figure, there are two registers 14.15't-1fQ that can control the first shift from the program.
ff, register 14 contains the loop start address (BR
TOREG), for example, the address (200
), and register 15 contains the end address of the loop (BR
fi'ROMREG), for example, the address (3
00). Then, the contents of register 15 are updated M! It is input to the comparison circuit 16 along with the output of 513, and when the contents of both match, "1"
'', resets the adder 11, and sets the contents of the register 14. Therefore, the program outputs the contents of the register 14.
(4) As long as the start and end addresses of the loop set to 15 do not change, the execution of the program in this loop is automatically repeated by the hardware, achieving the purpose of speeding up.

（６）発明の詳細 な説明したように、本発明によれば、プログラムカウン
タ方式のデジタル計ｎ機において、ループのプログラム
を多数回繰返して実行する場合、該ループの終シから始
めに戻すことをプログラムの通常の命令によることなく
簡単なノ為−ドウェアの付加により行なうことによシ、
この部分の処理時間を数分の１に短縮することができる
。とくに繰返し数が多い場合に有効である。(6) As described in detail, according to the present invention, when a loop program is repeatedly executed many times in a program counter type digital meter, it is possible to return to the beginning from the end of the loop. This can be done by simply adding hardware, without using the program's normal commands.
The processing time for this part can be reduced to several times. This is particularly effective when the number of repetitions is large.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明で用いるループのアドレスレジスタの説
明図、第２図は本発明の実施例の構成説明図であシ、図
中１はアドレスレジスタ、１１は加算器、１２はプログ
ラムカウンタ、１６はプログラムカウンタ更新回路、１
４．　ｉｓはレジスタ、１６は比較回路を示す。 （５） 第１図 第２図FIG. 1 is an explanatory diagram of the address register of a loop used in the present invention, and FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention. In the figure, 1 is an address register, 11 is an adder, 12 is a program counter, 16 is a program counter update circuit, 1
4. is is a register, and 16 is a comparison circuit. (5) Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] プログラムカウンタを用いてプログラムの命令を順次実
行するデジタル計算機において、ループのプログラムを
実行するため、該ループの始めと終漫のアドレスを設定
するレジスタと、該レジスタとプログラムカウンタの内
容の一致を検出しループのプログラムの終ジから始めに
戻すように制御する手段とを具えたことを特徴とするプ
ログラムカウンタ市１ｊ御装置。In a digital computer that sequentially executes program instructions using a program counter, in order to execute a loop program, a register that sets the start and end addresses of the loop is detected, and a match between the contents of the register and the program counter is detected. A program counter control device characterized in that it comprises means for controlling the program to return from the end of the loop to the beginning.
JP4584682A 1982-03-23 1982-03-23 Program counter control device Pending JPS58163045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4584682A JPS58163045A (en) 1982-03-23 1982-03-23 Program counter control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4584682A JPS58163045A (en) 1982-03-23 1982-03-23 Program counter control device

Publications (1)

Publication Number Publication Date
JPS58163045A true JPS58163045A (en) 1983-09-27

Family

ID=12730571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4584682A Pending JPS58163045A (en) 1982-03-23 1982-03-23 Program counter control device

Country Status (1)

Country Link
JP (1) JPS58163045A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60168243A (en) * 1983-09-29 1985-08-31 タンデム　コンピユ−タ−ズ　インコ−ポレ−テツド Tester

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60168243A (en) * 1983-09-29 1985-08-31 タンデム　コンピユ−タ−ズ　インコ−ポレ−テツド Tester

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